lcd.c 31 KB

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  1. /*
  2. * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
  3. * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public
  6. * License as published by the Free Software Foundation;
  7. * either version 2, or (at your option) any later version.
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
  10. * the implied warranty of MERCHANTABILITY or FITNESS FOR
  11. * A PARTICULAR PURPOSE.See the GNU General Public License
  12. * for more details.
  13. * You should have received a copy of the GNU General Public License
  14. * along with this program; if not, write to the Free Software
  15. * Foundation, Inc.,
  16. * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  17. */
  18. #include <linux/via-core.h>
  19. #include <linux/via_i2c.h>
  20. #include "global.h"
  21. #define viafb_compact_res(x, y) (((x)<<16)|(y))
  22. /* CLE266 Software Power Sequence */
  23. /* {Mask}, {Data}, {Delay} */
  24. static const int PowerSequenceOn[3][3] = {
  25. {0x10, 0x08, 0x06}, {0x10, 0x08, 0x06}, {0x19, 0x1FE, 0x01}
  26. };
  27. static const int PowerSequenceOff[3][3] = {
  28. {0x06, 0x08, 0x10}, {0x00, 0x00, 0x00}, {0xD2, 0x19, 0x01}
  29. };
  30. static struct _lcd_scaling_factor lcd_scaling_factor = {
  31. /* LCD Horizontal Scaling Factor Register */
  32. {LCD_HOR_SCALING_FACTOR_REG_NUM,
  33. {{CR9F, 0, 1}, {CR77, 0, 7}, {CR79, 4, 5} } },
  34. /* LCD Vertical Scaling Factor Register */
  35. {LCD_VER_SCALING_FACTOR_REG_NUM,
  36. {{CR79, 3, 3}, {CR78, 0, 7}, {CR79, 6, 7} } }
  37. };
  38. static struct _lcd_scaling_factor lcd_scaling_factor_CLE = {
  39. /* LCD Horizontal Scaling Factor Register */
  40. {LCD_HOR_SCALING_FACTOR_REG_NUM_CLE, {{CR77, 0, 7}, {CR79, 4, 5} } },
  41. /* LCD Vertical Scaling Factor Register */
  42. {LCD_VER_SCALING_FACTOR_REG_NUM_CLE, {{CR78, 0, 7}, {CR79, 6, 7} } }
  43. };
  44. static bool lvds_identify_integratedlvds(void);
  45. static void fp_id_to_vindex(int panel_id);
  46. static int lvds_register_read(int index);
  47. static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres,
  48. int panel_vres);
  49. static void lcd_patch_skew_dvp0(struct lvds_setting_information
  50. *plvds_setting_info,
  51. struct lvds_chip_information *plvds_chip_info);
  52. static void lcd_patch_skew_dvp1(struct lvds_setting_information
  53. *plvds_setting_info,
  54. struct lvds_chip_information *plvds_chip_info);
  55. static void lcd_patch_skew(struct lvds_setting_information
  56. *plvds_setting_info, struct lvds_chip_information *plvds_chip_info);
  57. static void integrated_lvds_disable(struct lvds_setting_information
  58. *plvds_setting_info,
  59. struct lvds_chip_information *plvds_chip_info);
  60. static void integrated_lvds_enable(struct lvds_setting_information
  61. *plvds_setting_info,
  62. struct lvds_chip_information *plvds_chip_info);
  63. static void lcd_powersequence_off(void);
  64. static void lcd_powersequence_on(void);
  65. static void fill_lcd_format(void);
  66. static void check_diport_of_integrated_lvds(
  67. struct lvds_chip_information *plvds_chip_info,
  68. struct lvds_setting_information
  69. *plvds_setting_info);
  70. static inline bool check_lvds_chip(int device_id_subaddr, int device_id)
  71. {
  72. return lvds_register_read(device_id_subaddr) == device_id;
  73. }
  74. void viafb_init_lcd_size(void)
  75. {
  76. DEBUG_MSG(KERN_INFO "viafb_init_lcd_size()\n");
  77. fp_id_to_vindex(viafb_lcd_panel_id);
  78. viaparinfo->lvds_setting_info2->lcd_panel_hres =
  79. viaparinfo->lvds_setting_info->lcd_panel_hres;
  80. viaparinfo->lvds_setting_info2->lcd_panel_vres =
  81. viaparinfo->lvds_setting_info->lcd_panel_vres;
  82. viaparinfo->lvds_setting_info2->device_lcd_dualedge =
  83. viaparinfo->lvds_setting_info->device_lcd_dualedge;
  84. viaparinfo->lvds_setting_info2->LCDDithering =
  85. viaparinfo->lvds_setting_info->LCDDithering;
  86. }
  87. static bool lvds_identify_integratedlvds(void)
  88. {
  89. if (viafb_display_hardware_layout == HW_LAYOUT_LCD_EXTERNAL_LCD2) {
  90. /* Two dual channel LCD (Internal LVDS + External LVDS): */
  91. /* If we have an external LVDS, such as VT1636, we should
  92. have its chip ID already. */
  93. if (viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
  94. viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name =
  95. INTEGRATED_LVDS;
  96. DEBUG_MSG(KERN_INFO "Support two dual channel LVDS! "
  97. "(Internal LVDS + External LVDS)\n");
  98. } else {
  99. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
  100. INTEGRATED_LVDS;
  101. DEBUG_MSG(KERN_INFO "Not found external LVDS, "
  102. "so can't support two dual channel LVDS!\n");
  103. }
  104. } else if (viafb_display_hardware_layout == HW_LAYOUT_LCD1_LCD2) {
  105. /* Two single channel LCD (Internal LVDS + Internal LVDS): */
  106. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
  107. INTEGRATED_LVDS;
  108. viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name =
  109. INTEGRATED_LVDS;
  110. DEBUG_MSG(KERN_INFO "Support two single channel LVDS! "
  111. "(Internal LVDS + Internal LVDS)\n");
  112. } else if (viafb_display_hardware_layout != HW_LAYOUT_DVI_ONLY) {
  113. /* If we have found external LVDS, just use it,
  114. otherwise, we will use internal LVDS as default. */
  115. if (!viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
  116. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
  117. INTEGRATED_LVDS;
  118. DEBUG_MSG(KERN_INFO "Found Integrated LVDS!\n");
  119. }
  120. } else {
  121. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
  122. NON_LVDS_TRANSMITTER;
  123. DEBUG_MSG(KERN_INFO "Do not support LVDS!\n");
  124. return false;
  125. }
  126. return true;
  127. }
  128. bool viafb_lvds_trasmitter_identify(void)
  129. {
  130. if (viafb_lvds_identify_vt1636(VIA_PORT_31)) {
  131. viaparinfo->chip_info->lvds_chip_info.i2c_port = VIA_PORT_31;
  132. DEBUG_MSG(KERN_INFO
  133. "Found VIA VT1636 LVDS on port i2c 0x31\n");
  134. } else {
  135. if (viafb_lvds_identify_vt1636(VIA_PORT_2C)) {
  136. viaparinfo->chip_info->lvds_chip_info.i2c_port =
  137. VIA_PORT_2C;
  138. DEBUG_MSG(KERN_INFO
  139. "Found VIA VT1636 LVDS on port gpio 0x2c\n");
  140. }
  141. }
  142. if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
  143. lvds_identify_integratedlvds();
  144. if (viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
  145. return true;
  146. /* Check for VT1631: */
  147. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name = VT1631_LVDS;
  148. viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr =
  149. VT1631_LVDS_I2C_ADDR;
  150. if (check_lvds_chip(VT1631_DEVICE_ID_REG, VT1631_DEVICE_ID)) {
  151. DEBUG_MSG(KERN_INFO "\n VT1631 LVDS ! \n");
  152. DEBUG_MSG(KERN_INFO "\n %2d",
  153. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
  154. DEBUG_MSG(KERN_INFO "\n %2d",
  155. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
  156. return true;
  157. }
  158. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
  159. NON_LVDS_TRANSMITTER;
  160. viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr =
  161. VT1631_LVDS_I2C_ADDR;
  162. return false;
  163. }
  164. static void fp_id_to_vindex(int panel_id)
  165. {
  166. DEBUG_MSG(KERN_INFO "fp_get_panel_id()\n");
  167. if (panel_id > LCD_PANEL_ID_MAXIMUM)
  168. viafb_lcd_panel_id = panel_id =
  169. viafb_read_reg(VIACR, CR3F) & 0x0F;
  170. switch (panel_id) {
  171. case 0x0:
  172. viaparinfo->lvds_setting_info->lcd_panel_hres = 640;
  173. viaparinfo->lvds_setting_info->lcd_panel_vres = 480;
  174. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  175. viaparinfo->lvds_setting_info->LCDDithering = 1;
  176. break;
  177. case 0x1:
  178. viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
  179. viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
  180. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  181. viaparinfo->lvds_setting_info->LCDDithering = 1;
  182. break;
  183. case 0x2:
  184. viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
  185. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  186. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  187. viaparinfo->lvds_setting_info->LCDDithering = 1;
  188. break;
  189. case 0x3:
  190. viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
  191. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  192. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  193. viaparinfo->lvds_setting_info->LCDDithering = 1;
  194. break;
  195. case 0x4:
  196. viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
  197. viaparinfo->lvds_setting_info->lcd_panel_vres = 1024;
  198. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  199. viaparinfo->lvds_setting_info->LCDDithering = 1;
  200. break;
  201. case 0x5:
  202. viaparinfo->lvds_setting_info->lcd_panel_hres = 1400;
  203. viaparinfo->lvds_setting_info->lcd_panel_vres = 1050;
  204. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  205. viaparinfo->lvds_setting_info->LCDDithering = 1;
  206. break;
  207. case 0x6:
  208. viaparinfo->lvds_setting_info->lcd_panel_hres = 1600;
  209. viaparinfo->lvds_setting_info->lcd_panel_vres = 1200;
  210. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  211. viaparinfo->lvds_setting_info->LCDDithering = 1;
  212. break;
  213. case 0x8:
  214. viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
  215. viaparinfo->lvds_setting_info->lcd_panel_vres = 480;
  216. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  217. viaparinfo->lvds_setting_info->LCDDithering = 1;
  218. break;
  219. case 0x9:
  220. viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
  221. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  222. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  223. viaparinfo->lvds_setting_info->LCDDithering = 1;
  224. break;
  225. case 0xA:
  226. viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
  227. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  228. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  229. viaparinfo->lvds_setting_info->LCDDithering = 0;
  230. break;
  231. case 0xB:
  232. viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
  233. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  234. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  235. viaparinfo->lvds_setting_info->LCDDithering = 0;
  236. break;
  237. case 0xC:
  238. viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
  239. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  240. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  241. viaparinfo->lvds_setting_info->LCDDithering = 0;
  242. break;
  243. case 0xD:
  244. viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
  245. viaparinfo->lvds_setting_info->lcd_panel_vres = 1024;
  246. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  247. viaparinfo->lvds_setting_info->LCDDithering = 0;
  248. break;
  249. case 0xE:
  250. viaparinfo->lvds_setting_info->lcd_panel_hres = 1400;
  251. viaparinfo->lvds_setting_info->lcd_panel_vres = 1050;
  252. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  253. viaparinfo->lvds_setting_info->LCDDithering = 0;
  254. break;
  255. case 0xF:
  256. viaparinfo->lvds_setting_info->lcd_panel_hres = 1600;
  257. viaparinfo->lvds_setting_info->lcd_panel_vres = 1200;
  258. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  259. viaparinfo->lvds_setting_info->LCDDithering = 0;
  260. break;
  261. case 0x10:
  262. viaparinfo->lvds_setting_info->lcd_panel_hres = 1366;
  263. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  264. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  265. viaparinfo->lvds_setting_info->LCDDithering = 0;
  266. break;
  267. case 0x11:
  268. viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
  269. viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
  270. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  271. viaparinfo->lvds_setting_info->LCDDithering = 1;
  272. break;
  273. case 0x12:
  274. viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
  275. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  276. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  277. viaparinfo->lvds_setting_info->LCDDithering = 1;
  278. break;
  279. case 0x13:
  280. viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
  281. viaparinfo->lvds_setting_info->lcd_panel_vres = 800;
  282. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  283. viaparinfo->lvds_setting_info->LCDDithering = 1;
  284. break;
  285. case 0x14:
  286. viaparinfo->lvds_setting_info->lcd_panel_hres = 1360;
  287. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  288. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  289. viaparinfo->lvds_setting_info->LCDDithering = 0;
  290. break;
  291. case 0x15:
  292. viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
  293. viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
  294. viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
  295. viaparinfo->lvds_setting_info->LCDDithering = 0;
  296. break;
  297. case 0x16:
  298. viaparinfo->lvds_setting_info->lcd_panel_hres = 480;
  299. viaparinfo->lvds_setting_info->lcd_panel_vres = 640;
  300. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  301. viaparinfo->lvds_setting_info->LCDDithering = 1;
  302. break;
  303. case 0x17:
  304. /* OLPC XO-1.5 panel */
  305. viaparinfo->lvds_setting_info->lcd_panel_hres = 1200;
  306. viaparinfo->lvds_setting_info->lcd_panel_vres = 900;
  307. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  308. viaparinfo->lvds_setting_info->LCDDithering = 0;
  309. break;
  310. default:
  311. viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
  312. viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
  313. viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
  314. viaparinfo->lvds_setting_info->LCDDithering = 1;
  315. }
  316. }
  317. static int lvds_register_read(int index)
  318. {
  319. u8 data;
  320. viafb_i2c_readbyte(VIA_PORT_2C,
  321. (u8) viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr,
  322. (u8) index, &data);
  323. return data;
  324. }
  325. static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres,
  326. int panel_vres)
  327. {
  328. int reg_value = 0;
  329. int viafb_load_reg_num;
  330. struct io_register *reg = NULL;
  331. DEBUG_MSG(KERN_INFO "load_lcd_scaling()!!\n");
  332. /* LCD Scaling Enable */
  333. viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2);
  334. /* Check if expansion for horizontal */
  335. if (set_hres < panel_hres) {
  336. /* Load Horizontal Scaling Factor */
  337. switch (viaparinfo->chip_info->gfx_chip_name) {
  338. case UNICHROME_CLE266:
  339. case UNICHROME_K400:
  340. reg_value =
  341. CLE266_LCD_HOR_SCF_FORMULA(set_hres, panel_hres);
  342. viafb_load_reg_num =
  343. lcd_scaling_factor_CLE.lcd_hor_scaling_factor.
  344. reg_num;
  345. reg = lcd_scaling_factor_CLE.lcd_hor_scaling_factor.reg;
  346. viafb_load_reg(reg_value,
  347. viafb_load_reg_num, reg, VIACR);
  348. break;
  349. case UNICHROME_K800:
  350. case UNICHROME_PM800:
  351. case UNICHROME_CN700:
  352. case UNICHROME_CX700:
  353. case UNICHROME_K8M890:
  354. case UNICHROME_P4M890:
  355. case UNICHROME_P4M900:
  356. case UNICHROME_CN750:
  357. case UNICHROME_VX800:
  358. case UNICHROME_VX855:
  359. case UNICHROME_VX900:
  360. reg_value =
  361. K800_LCD_HOR_SCF_FORMULA(set_hres, panel_hres);
  362. /* Horizontal scaling enabled */
  363. viafb_write_reg_mask(CRA2, VIACR, 0xC0, BIT7 + BIT6);
  364. viafb_load_reg_num =
  365. lcd_scaling_factor.lcd_hor_scaling_factor.reg_num;
  366. reg = lcd_scaling_factor.lcd_hor_scaling_factor.reg;
  367. viafb_load_reg(reg_value,
  368. viafb_load_reg_num, reg, VIACR);
  369. break;
  370. }
  371. DEBUG_MSG(KERN_INFO "Horizontal Scaling value = %d", reg_value);
  372. } else {
  373. /* Horizontal scaling disabled */
  374. viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT7);
  375. }
  376. /* Check if expansion for vertical */
  377. if (set_vres < panel_vres) {
  378. /* Load Vertical Scaling Factor */
  379. switch (viaparinfo->chip_info->gfx_chip_name) {
  380. case UNICHROME_CLE266:
  381. case UNICHROME_K400:
  382. reg_value =
  383. CLE266_LCD_VER_SCF_FORMULA(set_vres, panel_vres);
  384. viafb_load_reg_num =
  385. lcd_scaling_factor_CLE.lcd_ver_scaling_factor.
  386. reg_num;
  387. reg = lcd_scaling_factor_CLE.lcd_ver_scaling_factor.reg;
  388. viafb_load_reg(reg_value,
  389. viafb_load_reg_num, reg, VIACR);
  390. break;
  391. case UNICHROME_K800:
  392. case UNICHROME_PM800:
  393. case UNICHROME_CN700:
  394. case UNICHROME_CX700:
  395. case UNICHROME_K8M890:
  396. case UNICHROME_P4M890:
  397. case UNICHROME_P4M900:
  398. case UNICHROME_CN750:
  399. case UNICHROME_VX800:
  400. case UNICHROME_VX855:
  401. case UNICHROME_VX900:
  402. reg_value =
  403. K800_LCD_VER_SCF_FORMULA(set_vres, panel_vres);
  404. /* Vertical scaling enabled */
  405. viafb_write_reg_mask(CRA2, VIACR, 0x08, BIT3);
  406. viafb_load_reg_num =
  407. lcd_scaling_factor.lcd_ver_scaling_factor.reg_num;
  408. reg = lcd_scaling_factor.lcd_ver_scaling_factor.reg;
  409. viafb_load_reg(reg_value,
  410. viafb_load_reg_num, reg, VIACR);
  411. break;
  412. }
  413. DEBUG_MSG(KERN_INFO "Vertical Scaling value = %d", reg_value);
  414. } else {
  415. /* Vertical scaling disabled */
  416. viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT3);
  417. }
  418. }
  419. static void via_pitch_alignment_patch_lcd(int iga_path, int hres, int bpp)
  420. {
  421. unsigned char cr13, cr35, cr65, cr66, cr67;
  422. unsigned long dwScreenPitch = 0;
  423. unsigned long dwPitch;
  424. dwPitch = hres * (bpp >> 3);
  425. if (dwPitch & 0x1F) {
  426. dwScreenPitch = ((dwPitch + 31) & ~31) >> 3;
  427. if (iga_path == IGA2) {
  428. if (bpp > 8) {
  429. cr66 = (unsigned char)(dwScreenPitch & 0xFF);
  430. viafb_write_reg(CR66, VIACR, cr66);
  431. cr67 = viafb_read_reg(VIACR, CR67) & 0xFC;
  432. cr67 |=
  433. (unsigned
  434. char)((dwScreenPitch & 0x300) >> 8);
  435. viafb_write_reg(CR67, VIACR, cr67);
  436. }
  437. /* Fetch Count */
  438. cr67 = viafb_read_reg(VIACR, CR67) & 0xF3;
  439. cr67 |= (unsigned char)((dwScreenPitch & 0x600) >> 7);
  440. viafb_write_reg(CR67, VIACR, cr67);
  441. cr65 = (unsigned char)((dwScreenPitch >> 1) & 0xFF);
  442. cr65 += 2;
  443. viafb_write_reg(CR65, VIACR, cr65);
  444. } else {
  445. if (bpp > 8) {
  446. cr13 = (unsigned char)(dwScreenPitch & 0xFF);
  447. viafb_write_reg(CR13, VIACR, cr13);
  448. cr35 = viafb_read_reg(VIACR, CR35) & 0x1F;
  449. cr35 |=
  450. (unsigned
  451. char)((dwScreenPitch & 0x700) >> 3);
  452. viafb_write_reg(CR35, VIACR, cr35);
  453. }
  454. }
  455. }
  456. }
  457. static void lcd_patch_skew_dvp0(struct lvds_setting_information
  458. *plvds_setting_info,
  459. struct lvds_chip_information *plvds_chip_info)
  460. {
  461. if (VT1636_LVDS == plvds_chip_info->lvds_chip_name) {
  462. switch (viaparinfo->chip_info->gfx_chip_name) {
  463. case UNICHROME_P4M900:
  464. viafb_vt1636_patch_skew_on_vt3364(plvds_setting_info,
  465. plvds_chip_info);
  466. break;
  467. case UNICHROME_P4M890:
  468. viafb_vt1636_patch_skew_on_vt3327(plvds_setting_info,
  469. plvds_chip_info);
  470. break;
  471. }
  472. }
  473. }
  474. static void lcd_patch_skew_dvp1(struct lvds_setting_information
  475. *plvds_setting_info,
  476. struct lvds_chip_information *plvds_chip_info)
  477. {
  478. if (VT1636_LVDS == plvds_chip_info->lvds_chip_name) {
  479. switch (viaparinfo->chip_info->gfx_chip_name) {
  480. case UNICHROME_CX700:
  481. viafb_vt1636_patch_skew_on_vt3324(plvds_setting_info,
  482. plvds_chip_info);
  483. break;
  484. }
  485. }
  486. }
  487. static void lcd_patch_skew(struct lvds_setting_information
  488. *plvds_setting_info, struct lvds_chip_information *plvds_chip_info)
  489. {
  490. DEBUG_MSG(KERN_INFO "lcd_patch_skew\n");
  491. switch (plvds_chip_info->output_interface) {
  492. case INTERFACE_DVP0:
  493. lcd_patch_skew_dvp0(plvds_setting_info, plvds_chip_info);
  494. break;
  495. case INTERFACE_DVP1:
  496. lcd_patch_skew_dvp1(plvds_setting_info, plvds_chip_info);
  497. break;
  498. case INTERFACE_DFP_LOW:
  499. if (UNICHROME_P4M900 == viaparinfo->chip_info->gfx_chip_name) {
  500. viafb_write_reg_mask(CR99, VIACR, 0x08,
  501. BIT0 + BIT1 + BIT2 + BIT3);
  502. }
  503. break;
  504. }
  505. }
  506. /* LCD Set Mode */
  507. void viafb_lcd_set_mode(const struct fb_var_screeninfo *var, u16 cxres,
  508. u16 cyres, struct lvds_setting_information *plvds_setting_info,
  509. struct lvds_chip_information *plvds_chip_info)
  510. {
  511. int set_iga = plvds_setting_info->iga_path;
  512. int mode_bpp = var->bits_per_pixel;
  513. int set_hres = cxres ? cxres : var->xres;
  514. int set_vres = cyres ? cyres : var->yres;
  515. int panel_hres = plvds_setting_info->lcd_panel_hres;
  516. int panel_vres = plvds_setting_info->lcd_panel_vres;
  517. u32 clock;
  518. struct via_display_timing timing;
  519. struct fb_var_screeninfo panel_var;
  520. const struct fb_videomode *mode_crt_table, *panel_crt_table;
  521. DEBUG_MSG(KERN_INFO "viafb_lcd_set_mode!!\n");
  522. /* Get mode table */
  523. mode_crt_table = viafb_get_best_mode(set_hres, set_vres, 60);
  524. /* Get panel table Pointer */
  525. panel_crt_table = viafb_get_best_mode(panel_hres, panel_vres, 60);
  526. viafb_fill_var_timing_info(&panel_var, panel_crt_table);
  527. DEBUG_MSG(KERN_INFO "bellow viafb_lcd_set_mode!!\n");
  528. if (VT1636_LVDS == plvds_chip_info->lvds_chip_name)
  529. viafb_init_lvds_vt1636(plvds_setting_info, plvds_chip_info);
  530. clock = PICOS2KHZ(panel_crt_table->pixclock) * 1000;
  531. plvds_setting_info->vclk = clock;
  532. if (set_iga == IGA2 && (set_hres < panel_hres || set_vres < panel_vres)
  533. && plvds_setting_info->display_method == LCD_EXPANDSION) {
  534. timing = var_to_timing(&panel_var, panel_hres, panel_vres);
  535. load_lcd_scaling(set_hres, set_vres, panel_hres, panel_vres);
  536. } else {
  537. timing = var_to_timing(&panel_var, set_hres, set_vres);
  538. if (set_iga == IGA2)
  539. /* disable scaling */
  540. via_write_reg_mask(VIACR, 0x79, 0x00,
  541. BIT0 + BIT1 + BIT2);
  542. }
  543. if (set_iga == IGA1)
  544. via_set_primary_timing(&timing);
  545. else if (set_iga == IGA2)
  546. via_set_secondary_timing(&timing);
  547. /* Fetch count for IGA2 only */
  548. viafb_load_fetch_count_reg(set_hres, mode_bpp / 8, set_iga);
  549. if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
  550. && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
  551. viafb_load_FIFO_reg(set_iga, set_hres, set_vres);
  552. fill_lcd_format();
  553. viafb_set_vclock(clock, set_iga);
  554. lcd_patch_skew(plvds_setting_info, plvds_chip_info);
  555. /* If K8M800, enable LCD Prefetch Mode. */
  556. if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
  557. || (UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name))
  558. viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0);
  559. /* Patch for non 32bit alignment mode */
  560. via_pitch_alignment_patch_lcd(plvds_setting_info->iga_path, set_hres,
  561. var->bits_per_pixel);
  562. }
  563. static void integrated_lvds_disable(struct lvds_setting_information
  564. *plvds_setting_info,
  565. struct lvds_chip_information *plvds_chip_info)
  566. {
  567. bool turn_off_first_powersequence = false;
  568. bool turn_off_second_powersequence = false;
  569. if (INTERFACE_LVDS0LVDS1 == plvds_chip_info->output_interface)
  570. turn_off_first_powersequence = true;
  571. if (INTERFACE_LVDS0 == plvds_chip_info->output_interface)
  572. turn_off_first_powersequence = true;
  573. if (INTERFACE_LVDS1 == plvds_chip_info->output_interface)
  574. turn_off_second_powersequence = true;
  575. if (turn_off_second_powersequence) {
  576. /* Use second power sequence control: */
  577. /* Turn off power sequence. */
  578. viafb_write_reg_mask(CRD4, VIACR, 0, BIT1);
  579. /* Turn off back light. */
  580. viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7);
  581. }
  582. if (turn_off_first_powersequence) {
  583. /* Use first power sequence control: */
  584. /* Turn off power sequence. */
  585. viafb_write_reg_mask(CR6A, VIACR, 0, BIT3);
  586. /* Turn off back light. */
  587. viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7);
  588. }
  589. /* Power off LVDS channel. */
  590. switch (plvds_chip_info->output_interface) {
  591. case INTERFACE_LVDS0:
  592. {
  593. viafb_write_reg_mask(CRD2, VIACR, 0x80, BIT7);
  594. break;
  595. }
  596. case INTERFACE_LVDS1:
  597. {
  598. viafb_write_reg_mask(CRD2, VIACR, 0x40, BIT6);
  599. break;
  600. }
  601. case INTERFACE_LVDS0LVDS1:
  602. {
  603. viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7);
  604. break;
  605. }
  606. }
  607. }
  608. static void integrated_lvds_enable(struct lvds_setting_information
  609. *plvds_setting_info,
  610. struct lvds_chip_information *plvds_chip_info)
  611. {
  612. DEBUG_MSG(KERN_INFO "integrated_lvds_enable, out_interface:%d\n",
  613. plvds_chip_info->output_interface);
  614. if (plvds_setting_info->lcd_mode == LCD_SPWG)
  615. viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1);
  616. else
  617. viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1);
  618. switch (plvds_chip_info->output_interface) {
  619. case INTERFACE_LVDS0LVDS1:
  620. case INTERFACE_LVDS0:
  621. /* Use first power sequence control: */
  622. /* Use hardware control power sequence. */
  623. viafb_write_reg_mask(CR91, VIACR, 0, BIT0);
  624. /* Turn on back light. */
  625. viafb_write_reg_mask(CR91, VIACR, 0, BIT6 + BIT7);
  626. /* Turn on hardware power sequence. */
  627. viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
  628. break;
  629. case INTERFACE_LVDS1:
  630. /* Use second power sequence control: */
  631. /* Use hardware control power sequence. */
  632. viafb_write_reg_mask(CRD3, VIACR, 0, BIT0);
  633. /* Turn on back light. */
  634. viafb_write_reg_mask(CRD3, VIACR, 0, BIT6 + BIT7);
  635. /* Turn on hardware power sequence. */
  636. viafb_write_reg_mask(CRD4, VIACR, 0x02, BIT1);
  637. break;
  638. }
  639. /* Power on LVDS channel. */
  640. switch (plvds_chip_info->output_interface) {
  641. case INTERFACE_LVDS0:
  642. {
  643. viafb_write_reg_mask(CRD2, VIACR, 0, BIT7);
  644. break;
  645. }
  646. case INTERFACE_LVDS1:
  647. {
  648. viafb_write_reg_mask(CRD2, VIACR, 0, BIT6);
  649. break;
  650. }
  651. case INTERFACE_LVDS0LVDS1:
  652. {
  653. viafb_write_reg_mask(CRD2, VIACR, 0, BIT6 + BIT7);
  654. break;
  655. }
  656. }
  657. }
  658. void viafb_lcd_disable(void)
  659. {
  660. if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
  661. lcd_powersequence_off();
  662. /* DI1 pad off */
  663. viafb_write_reg_mask(SR1E, VIASR, 0x00, 0x30);
  664. } else if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
  665. if (viafb_LCD2_ON
  666. && (INTEGRATED_LVDS ==
  667. viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name))
  668. integrated_lvds_disable(viaparinfo->lvds_setting_info,
  669. &viaparinfo->chip_info->lvds_chip_info2);
  670. if (INTEGRATED_LVDS ==
  671. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
  672. integrated_lvds_disable(viaparinfo->lvds_setting_info,
  673. &viaparinfo->chip_info->lvds_chip_info);
  674. if (VT1636_LVDS == viaparinfo->chip_info->
  675. lvds_chip_info.lvds_chip_name)
  676. viafb_disable_lvds_vt1636(viaparinfo->lvds_setting_info,
  677. &viaparinfo->chip_info->lvds_chip_info);
  678. } else if (VT1636_LVDS ==
  679. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
  680. viafb_disable_lvds_vt1636(viaparinfo->lvds_setting_info,
  681. &viaparinfo->chip_info->lvds_chip_info);
  682. } else {
  683. /* Backlight off */
  684. viafb_write_reg_mask(SR3D, VIASR, 0x00, 0x20);
  685. /* 24 bit DI data paht off */
  686. viafb_write_reg_mask(CR91, VIACR, 0x80, 0x80);
  687. }
  688. /* Disable expansion bit */
  689. viafb_write_reg_mask(CR79, VIACR, 0x00, 0x01);
  690. /* Simultaneout disabled */
  691. viafb_write_reg_mask(CR6B, VIACR, 0x00, 0x08);
  692. }
  693. static void set_lcd_output_path(int set_iga, int output_interface)
  694. {
  695. switch (output_interface) {
  696. case INTERFACE_DFP:
  697. if ((UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name)
  698. || (UNICHROME_P4M890 ==
  699. viaparinfo->chip_info->gfx_chip_name))
  700. viafb_write_reg_mask(CR97, VIACR, 0x84,
  701. BIT7 + BIT2 + BIT1 + BIT0);
  702. case INTERFACE_DVP0:
  703. case INTERFACE_DVP1:
  704. case INTERFACE_DFP_HIGH:
  705. case INTERFACE_DFP_LOW:
  706. if (set_iga == IGA2)
  707. viafb_write_reg(CR91, VIACR, 0x00);
  708. break;
  709. }
  710. }
  711. void viafb_lcd_enable(void)
  712. {
  713. viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
  714. viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
  715. set_lcd_output_path(viaparinfo->lvds_setting_info->iga_path,
  716. viaparinfo->chip_info->lvds_chip_info.output_interface);
  717. if (viafb_LCD2_ON)
  718. set_lcd_output_path(viaparinfo->lvds_setting_info2->iga_path,
  719. viaparinfo->chip_info->
  720. lvds_chip_info2.output_interface);
  721. if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
  722. /* DI1 pad on */
  723. viafb_write_reg_mask(SR1E, VIASR, 0x30, 0x30);
  724. lcd_powersequence_on();
  725. } else if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
  726. if (viafb_LCD2_ON && (INTEGRATED_LVDS ==
  727. viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name))
  728. integrated_lvds_enable(viaparinfo->lvds_setting_info2, \
  729. &viaparinfo->chip_info->lvds_chip_info2);
  730. if (INTEGRATED_LVDS ==
  731. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
  732. integrated_lvds_enable(viaparinfo->lvds_setting_info,
  733. &viaparinfo->chip_info->lvds_chip_info);
  734. if (VT1636_LVDS == viaparinfo->chip_info->
  735. lvds_chip_info.lvds_chip_name)
  736. viafb_enable_lvds_vt1636(viaparinfo->
  737. lvds_setting_info, &viaparinfo->chip_info->
  738. lvds_chip_info);
  739. } else if (VT1636_LVDS ==
  740. viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
  741. viafb_enable_lvds_vt1636(viaparinfo->lvds_setting_info,
  742. &viaparinfo->chip_info->lvds_chip_info);
  743. } else {
  744. /* Backlight on */
  745. viafb_write_reg_mask(SR3D, VIASR, 0x20, 0x20);
  746. /* 24 bit DI data paht on */
  747. viafb_write_reg_mask(CR91, VIACR, 0x00, 0x80);
  748. /* LCD enabled */
  749. viafb_write_reg_mask(CR6A, VIACR, 0x48, 0x48);
  750. }
  751. }
  752. static void lcd_powersequence_off(void)
  753. {
  754. int i, mask, data;
  755. /* Software control power sequence */
  756. viafb_write_reg_mask(CR91, VIACR, 0x11, 0x11);
  757. for (i = 0; i < 3; i++) {
  758. mask = PowerSequenceOff[0][i];
  759. data = PowerSequenceOff[1][i] & mask;
  760. viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask);
  761. udelay(PowerSequenceOff[2][i]);
  762. }
  763. /* Disable LCD */
  764. viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x08);
  765. }
  766. static void lcd_powersequence_on(void)
  767. {
  768. int i, mask, data;
  769. /* Software control power sequence */
  770. viafb_write_reg_mask(CR91, VIACR, 0x11, 0x11);
  771. /* Enable LCD */
  772. viafb_write_reg_mask(CR6A, VIACR, 0x08, 0x08);
  773. for (i = 0; i < 3; i++) {
  774. mask = PowerSequenceOn[0][i];
  775. data = PowerSequenceOn[1][i] & mask;
  776. viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask);
  777. udelay(PowerSequenceOn[2][i]);
  778. }
  779. udelay(1);
  780. }
  781. static void fill_lcd_format(void)
  782. {
  783. u8 bdithering = 0, bdual = 0;
  784. if (viaparinfo->lvds_setting_info->device_lcd_dualedge)
  785. bdual = BIT4;
  786. if (viaparinfo->lvds_setting_info->LCDDithering)
  787. bdithering = BIT0;
  788. /* Dual & Dithering */
  789. viafb_write_reg_mask(CR88, VIACR, (bdithering | bdual), BIT4 + BIT0);
  790. }
  791. static void check_diport_of_integrated_lvds(
  792. struct lvds_chip_information *plvds_chip_info,
  793. struct lvds_setting_information
  794. *plvds_setting_info)
  795. {
  796. /* Determine LCD DI Port by hardware layout. */
  797. switch (viafb_display_hardware_layout) {
  798. case HW_LAYOUT_LCD_ONLY:
  799. {
  800. if (plvds_setting_info->device_lcd_dualedge) {
  801. plvds_chip_info->output_interface =
  802. INTERFACE_LVDS0LVDS1;
  803. } else {
  804. plvds_chip_info->output_interface =
  805. INTERFACE_LVDS0;
  806. }
  807. break;
  808. }
  809. case HW_LAYOUT_DVI_ONLY:
  810. {
  811. plvds_chip_info->output_interface = INTERFACE_NONE;
  812. break;
  813. }
  814. case HW_LAYOUT_LCD1_LCD2:
  815. case HW_LAYOUT_LCD_EXTERNAL_LCD2:
  816. {
  817. plvds_chip_info->output_interface =
  818. INTERFACE_LVDS0LVDS1;
  819. break;
  820. }
  821. case HW_LAYOUT_LCD_DVI:
  822. {
  823. plvds_chip_info->output_interface = INTERFACE_LVDS1;
  824. break;
  825. }
  826. default:
  827. {
  828. plvds_chip_info->output_interface = INTERFACE_LVDS1;
  829. break;
  830. }
  831. }
  832. DEBUG_MSG(KERN_INFO
  833. "Display Hardware Layout: 0x%x, LCD DI Port: 0x%x\n",
  834. viafb_display_hardware_layout,
  835. plvds_chip_info->output_interface);
  836. }
  837. void viafb_init_lvds_output_interface(struct lvds_chip_information
  838. *plvds_chip_info,
  839. struct lvds_setting_information
  840. *plvds_setting_info)
  841. {
  842. if (INTERFACE_NONE != plvds_chip_info->output_interface) {
  843. /*Do nothing, lcd port is specified by module parameter */
  844. return;
  845. }
  846. switch (plvds_chip_info->lvds_chip_name) {
  847. case VT1636_LVDS:
  848. switch (viaparinfo->chip_info->gfx_chip_name) {
  849. case UNICHROME_CX700:
  850. plvds_chip_info->output_interface = INTERFACE_DVP1;
  851. break;
  852. case UNICHROME_CN700:
  853. plvds_chip_info->output_interface = INTERFACE_DFP_LOW;
  854. break;
  855. default:
  856. plvds_chip_info->output_interface = INTERFACE_DVP0;
  857. break;
  858. }
  859. break;
  860. case INTEGRATED_LVDS:
  861. check_diport_of_integrated_lvds(plvds_chip_info,
  862. plvds_setting_info);
  863. break;
  864. default:
  865. switch (viaparinfo->chip_info->gfx_chip_name) {
  866. case UNICHROME_K8M890:
  867. case UNICHROME_P4M900:
  868. case UNICHROME_P4M890:
  869. plvds_chip_info->output_interface = INTERFACE_DFP_LOW;
  870. break;
  871. default:
  872. plvds_chip_info->output_interface = INTERFACE_DFP;
  873. break;
  874. }
  875. break;
  876. }
  877. }
  878. bool viafb_lcd_get_mobile_state(bool *mobile)
  879. {
  880. unsigned char __iomem *romptr, *tableptr, *biosptr;
  881. u8 core_base;
  882. /* Rom address */
  883. const u32 romaddr = 0x000C0000;
  884. u16 start_pattern;
  885. biosptr = ioremap(romaddr, 0x10000);
  886. start_pattern = readw(biosptr);
  887. /* Compare pattern */
  888. if (start_pattern == 0xAA55) {
  889. /* Get the start of Table */
  890. /* 0x1B means BIOS offset position */
  891. romptr = biosptr + 0x1B;
  892. tableptr = biosptr + readw(romptr);
  893. /* Get the start of biosver structure */
  894. /* 18 means BIOS version position. */
  895. romptr = tableptr + 18;
  896. romptr = biosptr + readw(romptr);
  897. /* The offset should be 44, but the
  898. actual image is less three char. */
  899. /* pRom += 44; */
  900. romptr += 41;
  901. core_base = readb(romptr);
  902. if (core_base & 0x8)
  903. *mobile = false;
  904. else
  905. *mobile = true;
  906. /* release memory */
  907. iounmap(biosptr);
  908. return true;
  909. } else {
  910. iounmap(biosptr);
  911. return false;
  912. }
  913. }