events_2l.c 10 KB

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  1. /*
  2. * Xen event channels (2-level ABI)
  3. *
  4. * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
  5. */
  6. #define pr_fmt(fmt) "xen:" KBUILD_MODNAME ": " fmt
  7. #include <linux/linkage.h>
  8. #include <linux/interrupt.h>
  9. #include <linux/irq.h>
  10. #include <linux/module.h>
  11. #include <asm/sync_bitops.h>
  12. #include <asm/xen/hypercall.h>
  13. #include <asm/xen/hypervisor.h>
  14. #include <xen/xen.h>
  15. #include <xen/xen-ops.h>
  16. #include <xen/events.h>
  17. #include <xen/interface/xen.h>
  18. #include <xen/interface/event_channel.h>
  19. #include "events_internal.h"
  20. /*
  21. * Note sizeof(xen_ulong_t) can be more than sizeof(unsigned long). Be
  22. * careful to only use bitops which allow for this (e.g
  23. * test_bit/find_first_bit and friends but not __ffs) and to pass
  24. * BITS_PER_EVTCHN_WORD as the bitmask length.
  25. */
  26. #define BITS_PER_EVTCHN_WORD (sizeof(xen_ulong_t)*8)
  27. /*
  28. * Make a bitmask (i.e. unsigned long *) of a xen_ulong_t
  29. * array. Primarily to avoid long lines (hence the terse name).
  30. */
  31. #define BM(x) (unsigned long *)(x)
  32. /* Find the first set bit in a evtchn mask */
  33. #define EVTCHN_FIRST_BIT(w) find_first_bit(BM(&(w)), BITS_PER_EVTCHN_WORD)
  34. static DEFINE_PER_CPU(xen_ulong_t [EVTCHN_2L_NR_CHANNELS/BITS_PER_EVTCHN_WORD],
  35. cpu_evtchn_mask);
  36. static unsigned evtchn_2l_max_channels(void)
  37. {
  38. return EVTCHN_2L_NR_CHANNELS;
  39. }
  40. static void evtchn_2l_bind_to_cpu(struct irq_info *info, unsigned cpu)
  41. {
  42. clear_bit(info->evtchn, BM(per_cpu(cpu_evtchn_mask, info->cpu)));
  43. set_bit(info->evtchn, BM(per_cpu(cpu_evtchn_mask, cpu)));
  44. }
  45. static void evtchn_2l_clear_pending(unsigned port)
  46. {
  47. struct shared_info *s = HYPERVISOR_shared_info;
  48. sync_clear_bit(port, BM(&s->evtchn_pending[0]));
  49. }
  50. static void evtchn_2l_set_pending(unsigned port)
  51. {
  52. struct shared_info *s = HYPERVISOR_shared_info;
  53. sync_set_bit(port, BM(&s->evtchn_pending[0]));
  54. }
  55. static bool evtchn_2l_is_pending(unsigned port)
  56. {
  57. struct shared_info *s = HYPERVISOR_shared_info;
  58. return sync_test_bit(port, BM(&s->evtchn_pending[0]));
  59. }
  60. static bool evtchn_2l_test_and_set_mask(unsigned port)
  61. {
  62. struct shared_info *s = HYPERVISOR_shared_info;
  63. return sync_test_and_set_bit(port, BM(&s->evtchn_mask[0]));
  64. }
  65. static void evtchn_2l_mask(unsigned port)
  66. {
  67. struct shared_info *s = HYPERVISOR_shared_info;
  68. sync_set_bit(port, BM(&s->evtchn_mask[0]));
  69. }
  70. static void evtchn_2l_unmask(unsigned port)
  71. {
  72. struct shared_info *s = HYPERVISOR_shared_info;
  73. unsigned int cpu = get_cpu();
  74. int do_hypercall = 0, evtchn_pending = 0;
  75. BUG_ON(!irqs_disabled());
  76. if (unlikely((cpu != cpu_from_evtchn(port))))
  77. do_hypercall = 1;
  78. else {
  79. /*
  80. * Need to clear the mask before checking pending to
  81. * avoid a race with an event becoming pending.
  82. *
  83. * EVTCHNOP_unmask will only trigger an upcall if the
  84. * mask bit was set, so if a hypercall is needed
  85. * remask the event.
  86. */
  87. sync_clear_bit(port, BM(&s->evtchn_mask[0]));
  88. evtchn_pending = sync_test_bit(port, BM(&s->evtchn_pending[0]));
  89. if (unlikely(evtchn_pending && xen_hvm_domain())) {
  90. sync_set_bit(port, BM(&s->evtchn_mask[0]));
  91. do_hypercall = 1;
  92. }
  93. }
  94. /* Slow path (hypercall) if this is a non-local port or if this is
  95. * an hvm domain and an event is pending (hvm domains don't have
  96. * their own implementation of irq_enable). */
  97. if (do_hypercall) {
  98. struct evtchn_unmask unmask = { .port = port };
  99. (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
  100. } else {
  101. struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
  102. /*
  103. * The following is basically the equivalent of
  104. * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
  105. * the interrupt edge' if the channel is masked.
  106. */
  107. if (evtchn_pending &&
  108. !sync_test_and_set_bit(port / BITS_PER_EVTCHN_WORD,
  109. BM(&vcpu_info->evtchn_pending_sel)))
  110. vcpu_info->evtchn_upcall_pending = 1;
  111. }
  112. put_cpu();
  113. }
  114. static DEFINE_PER_CPU(unsigned int, current_word_idx);
  115. static DEFINE_PER_CPU(unsigned int, current_bit_idx);
  116. /*
  117. * Mask out the i least significant bits of w
  118. */
  119. #define MASK_LSBS(w, i) (w & ((~((xen_ulong_t)0UL)) << i))
  120. static inline xen_ulong_t active_evtchns(unsigned int cpu,
  121. struct shared_info *sh,
  122. unsigned int idx)
  123. {
  124. return sh->evtchn_pending[idx] &
  125. per_cpu(cpu_evtchn_mask, cpu)[idx] &
  126. ~sh->evtchn_mask[idx];
  127. }
  128. /*
  129. * Search the CPU's pending events bitmasks. For each one found, map
  130. * the event number to an irq, and feed it into do_IRQ() for handling.
  131. *
  132. * Xen uses a two-level bitmap to speed searching. The first level is
  133. * a bitset of words which contain pending event bits. The second
  134. * level is a bitset of pending events themselves.
  135. */
  136. static void evtchn_2l_handle_events(unsigned cpu)
  137. {
  138. int irq;
  139. xen_ulong_t pending_words;
  140. xen_ulong_t pending_bits;
  141. int start_word_idx, start_bit_idx;
  142. int word_idx, bit_idx;
  143. int i;
  144. struct shared_info *s = HYPERVISOR_shared_info;
  145. struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
  146. /* Timer interrupt has highest priority. */
  147. irq = irq_from_virq(cpu, VIRQ_TIMER);
  148. if (irq != -1) {
  149. unsigned int evtchn = evtchn_from_irq(irq);
  150. word_idx = evtchn / BITS_PER_LONG;
  151. bit_idx = evtchn % BITS_PER_LONG;
  152. if (active_evtchns(cpu, s, word_idx) & (1ULL << bit_idx))
  153. generic_handle_irq(irq);
  154. }
  155. /*
  156. * Master flag must be cleared /before/ clearing
  157. * selector flag. xchg_xen_ulong must contain an
  158. * appropriate barrier.
  159. */
  160. pending_words = xchg_xen_ulong(&vcpu_info->evtchn_pending_sel, 0);
  161. start_word_idx = __this_cpu_read(current_word_idx);
  162. start_bit_idx = __this_cpu_read(current_bit_idx);
  163. word_idx = start_word_idx;
  164. for (i = 0; pending_words != 0; i++) {
  165. xen_ulong_t words;
  166. words = MASK_LSBS(pending_words, word_idx);
  167. /*
  168. * If we masked out all events, wrap to beginning.
  169. */
  170. if (words == 0) {
  171. word_idx = 0;
  172. bit_idx = 0;
  173. continue;
  174. }
  175. word_idx = EVTCHN_FIRST_BIT(words);
  176. pending_bits = active_evtchns(cpu, s, word_idx);
  177. bit_idx = 0; /* usually scan entire word from start */
  178. /*
  179. * We scan the starting word in two parts.
  180. *
  181. * 1st time: start in the middle, scanning the
  182. * upper bits.
  183. *
  184. * 2nd time: scan the whole word (not just the
  185. * parts skipped in the first pass) -- if an
  186. * event in the previously scanned bits is
  187. * pending again it would just be scanned on
  188. * the next loop anyway.
  189. */
  190. if (word_idx == start_word_idx) {
  191. if (i == 0)
  192. bit_idx = start_bit_idx;
  193. }
  194. do {
  195. xen_ulong_t bits;
  196. int port;
  197. bits = MASK_LSBS(pending_bits, bit_idx);
  198. /* If we masked out all events, move on. */
  199. if (bits == 0)
  200. break;
  201. bit_idx = EVTCHN_FIRST_BIT(bits);
  202. /* Process port. */
  203. port = (word_idx * BITS_PER_EVTCHN_WORD) + bit_idx;
  204. irq = get_evtchn_to_irq(port);
  205. if (irq != -1)
  206. generic_handle_irq(irq);
  207. bit_idx = (bit_idx + 1) % BITS_PER_EVTCHN_WORD;
  208. /* Next caller starts at last processed + 1 */
  209. __this_cpu_write(current_word_idx,
  210. bit_idx ? word_idx :
  211. (word_idx+1) % BITS_PER_EVTCHN_WORD);
  212. __this_cpu_write(current_bit_idx, bit_idx);
  213. } while (bit_idx != 0);
  214. /* Scan start_l1i twice; all others once. */
  215. if ((word_idx != start_word_idx) || (i != 0))
  216. pending_words &= ~(1UL << word_idx);
  217. word_idx = (word_idx + 1) % BITS_PER_EVTCHN_WORD;
  218. }
  219. }
  220. irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
  221. {
  222. struct shared_info *sh = HYPERVISOR_shared_info;
  223. int cpu = smp_processor_id();
  224. xen_ulong_t *cpu_evtchn = per_cpu(cpu_evtchn_mask, cpu);
  225. int i;
  226. unsigned long flags;
  227. static DEFINE_SPINLOCK(debug_lock);
  228. struct vcpu_info *v;
  229. spin_lock_irqsave(&debug_lock, flags);
  230. printk("\nvcpu %d\n ", cpu);
  231. for_each_online_cpu(i) {
  232. int pending;
  233. v = per_cpu(xen_vcpu, i);
  234. pending = (get_irq_regs() && i == cpu)
  235. ? xen_irqs_disabled(get_irq_regs())
  236. : v->evtchn_upcall_mask;
  237. printk("%d: masked=%d pending=%d event_sel %0*"PRI_xen_ulong"\n ", i,
  238. pending, v->evtchn_upcall_pending,
  239. (int)(sizeof(v->evtchn_pending_sel)*2),
  240. v->evtchn_pending_sel);
  241. }
  242. v = per_cpu(xen_vcpu, cpu);
  243. printk("\npending:\n ");
  244. for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
  245. printk("%0*"PRI_xen_ulong"%s",
  246. (int)sizeof(sh->evtchn_pending[0])*2,
  247. sh->evtchn_pending[i],
  248. i % 8 == 0 ? "\n " : " ");
  249. printk("\nglobal mask:\n ");
  250. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
  251. printk("%0*"PRI_xen_ulong"%s",
  252. (int)(sizeof(sh->evtchn_mask[0])*2),
  253. sh->evtchn_mask[i],
  254. i % 8 == 0 ? "\n " : " ");
  255. printk("\nglobally unmasked:\n ");
  256. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
  257. printk("%0*"PRI_xen_ulong"%s",
  258. (int)(sizeof(sh->evtchn_mask[0])*2),
  259. sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
  260. i % 8 == 0 ? "\n " : " ");
  261. printk("\nlocal cpu%d mask:\n ", cpu);
  262. for (i = (EVTCHN_2L_NR_CHANNELS/BITS_PER_EVTCHN_WORD)-1; i >= 0; i--)
  263. printk("%0*"PRI_xen_ulong"%s", (int)(sizeof(cpu_evtchn[0])*2),
  264. cpu_evtchn[i],
  265. i % 8 == 0 ? "\n " : " ");
  266. printk("\nlocally unmasked:\n ");
  267. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
  268. xen_ulong_t pending = sh->evtchn_pending[i]
  269. & ~sh->evtchn_mask[i]
  270. & cpu_evtchn[i];
  271. printk("%0*"PRI_xen_ulong"%s",
  272. (int)(sizeof(sh->evtchn_mask[0])*2),
  273. pending, i % 8 == 0 ? "\n " : " ");
  274. }
  275. printk("\npending list:\n");
  276. for (i = 0; i < EVTCHN_2L_NR_CHANNELS; i++) {
  277. if (sync_test_bit(i, BM(sh->evtchn_pending))) {
  278. int word_idx = i / BITS_PER_EVTCHN_WORD;
  279. printk(" %d: event %d -> irq %d%s%s%s\n",
  280. cpu_from_evtchn(i), i,
  281. get_evtchn_to_irq(i),
  282. sync_test_bit(word_idx, BM(&v->evtchn_pending_sel))
  283. ? "" : " l2-clear",
  284. !sync_test_bit(i, BM(sh->evtchn_mask))
  285. ? "" : " globally-masked",
  286. sync_test_bit(i, BM(cpu_evtchn))
  287. ? "" : " locally-masked");
  288. }
  289. }
  290. spin_unlock_irqrestore(&debug_lock, flags);
  291. return IRQ_HANDLED;
  292. }
  293. static void evtchn_2l_resume(void)
  294. {
  295. int i;
  296. for_each_online_cpu(i)
  297. memset(per_cpu(cpu_evtchn_mask, i), 0, sizeof(xen_ulong_t) *
  298. EVTCHN_2L_NR_CHANNELS/BITS_PER_EVTCHN_WORD);
  299. }
  300. static const struct evtchn_ops evtchn_ops_2l = {
  301. .max_channels = evtchn_2l_max_channels,
  302. .nr_channels = evtchn_2l_max_channels,
  303. .bind_to_cpu = evtchn_2l_bind_to_cpu,
  304. .clear_pending = evtchn_2l_clear_pending,
  305. .set_pending = evtchn_2l_set_pending,
  306. .is_pending = evtchn_2l_is_pending,
  307. .test_and_set_mask = evtchn_2l_test_and_set_mask,
  308. .mask = evtchn_2l_mask,
  309. .unmask = evtchn_2l_unmask,
  310. .handle_events = evtchn_2l_handle_events,
  311. .resume = evtchn_2l_resume,
  312. };
  313. void __init xen_evtchn_2l_init(void)
  314. {
  315. pr_info("Using 2-level ABI\n");
  316. evtchn_ops = &evtchn_ops_2l;
  317. }