qcom,gcc-msm8660.h 4.0 KB

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  1. /*
  2. * Copyright (c) 2013, The Linux Foundation. All rights reserved.
  3. *
  4. * This software is licensed under the terms of the GNU General Public
  5. * License version 2, as published by the Free Software Foundation, and
  6. * may be copied, distributed, and modified under those terms.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #ifndef _DT_BINDINGS_RESET_MSM_GCC_8660_H
  14. #define _DT_BINDINGS_RESET_MSM_GCC_8660_H
  15. #define AFAB_CORE_RESET 0
  16. #define SCSS_SYS_RESET 1
  17. #define SCSS_SYS_POR_RESET 2
  18. #define AFAB_SMPSS_S_RESET 3
  19. #define AFAB_SMPSS_M1_RESET 4
  20. #define AFAB_SMPSS_M0_RESET 5
  21. #define AFAB_EBI1_S_RESET 6
  22. #define SFAB_CORE_RESET 7
  23. #define SFAB_ADM0_M0_RESET 8
  24. #define SFAB_ADM0_M1_RESET 9
  25. #define SFAB_ADM0_M2_RESET 10
  26. #define ADM0_C2_RESET 11
  27. #define ADM0_C1_RESET 12
  28. #define ADM0_C0_RESET 13
  29. #define ADM0_PBUS_RESET 14
  30. #define ADM0_RESET 15
  31. #define SFAB_ADM1_M0_RESET 16
  32. #define SFAB_ADM1_M1_RESET 17
  33. #define SFAB_ADM1_M2_RESET 18
  34. #define MMFAB_ADM1_M3_RESET 19
  35. #define ADM1_C3_RESET 20
  36. #define ADM1_C2_RESET 21
  37. #define ADM1_C1_RESET 22
  38. #define ADM1_C0_RESET 23
  39. #define ADM1_PBUS_RESET 24
  40. #define ADM1_RESET 25
  41. #define IMEM0_RESET 26
  42. #define SFAB_LPASS_Q6_RESET 27
  43. #define SFAB_AFAB_M_RESET 28
  44. #define AFAB_SFAB_M0_RESET 29
  45. #define AFAB_SFAB_M1_RESET 30
  46. #define DFAB_CORE_RESET 31
  47. #define SFAB_DFAB_M_RESET 32
  48. #define DFAB_SFAB_M_RESET 33
  49. #define DFAB_SWAY0_RESET 34
  50. #define DFAB_SWAY1_RESET 35
  51. #define DFAB_ARB0_RESET 36
  52. #define DFAB_ARB1_RESET 37
  53. #define PPSS_PROC_RESET 38
  54. #define PPSS_RESET 39
  55. #define PMEM_RESET 40
  56. #define DMA_BAM_RESET 41
  57. #define SIC_RESET 42
  58. #define SPS_TIC_RESET 43
  59. #define CFBP0_RESET 44
  60. #define CFBP1_RESET 45
  61. #define CFBP2_RESET 46
  62. #define EBI2_RESET 47
  63. #define SFAB_CFPB_M_RESET 48
  64. #define CFPB_MASTER_RESET 49
  65. #define SFAB_CFPB_S_RESET 50
  66. #define CFPB_SPLITTER_RESET 51
  67. #define TSIF_RESET 52
  68. #define CE1_RESET 53
  69. #define CE2_RESET 54
  70. #define SFAB_SFPB_M_RESET 55
  71. #define SFAB_SFPB_S_RESET 56
  72. #define RPM_PROC_RESET 57
  73. #define RPM_BUS_RESET 58
  74. #define RPM_MSG_RAM_RESET 59
  75. #define PMIC_ARB0_RESET 60
  76. #define PMIC_ARB1_RESET 61
  77. #define PMIC_SSBI2_RESET 62
  78. #define SDC1_RESET 63
  79. #define SDC2_RESET 64
  80. #define SDC3_RESET 65
  81. #define SDC4_RESET 66
  82. #define SDC5_RESET 67
  83. #define USB_HS1_RESET 68
  84. #define USB_HS2_XCVR_RESET 69
  85. #define USB_HS2_RESET 70
  86. #define USB_FS1_XCVR_RESET 71
  87. #define USB_FS1_RESET 72
  88. #define USB_FS2_XCVR_RESET 73
  89. #define USB_FS2_RESET 74
  90. #define GSBI1_RESET 75
  91. #define GSBI2_RESET 76
  92. #define GSBI3_RESET 77
  93. #define GSBI4_RESET 78
  94. #define GSBI5_RESET 79
  95. #define GSBI6_RESET 80
  96. #define GSBI7_RESET 81
  97. #define GSBI8_RESET 82
  98. #define GSBI9_RESET 83
  99. #define GSBI10_RESET 84
  100. #define GSBI11_RESET 85
  101. #define GSBI12_RESET 86
  102. #define SPDM_RESET 87
  103. #define SEC_CTRL_RESET 88
  104. #define TLMM_H_RESET 89
  105. #define TLMM_RESET 90
  106. #define MARRM_PWRON_RESET 91
  107. #define MARM_RESET 92
  108. #define MAHB1_RESET 93
  109. #define SFAB_MSS_S_RESET 94
  110. #define MAHB2_RESET 95
  111. #define MODEM_SW_AHB_RESET 96
  112. #define MODEM_RESET 97
  113. #define SFAB_MSS_MDM1_RESET 98
  114. #define SFAB_MSS_MDM0_RESET 99
  115. #define MSS_SLP_RESET 100
  116. #define MSS_MARM_SAW_RESET 101
  117. #define MSS_WDOG_RESET 102
  118. #define TSSC_RESET 103
  119. #define PDM_RESET 104
  120. #define SCSS_CORE0_RESET 105
  121. #define SCSS_CORE0_POR_RESET 106
  122. #define SCSS_CORE1_RESET 107
  123. #define SCSS_CORE1_POR_RESET 108
  124. #define MPM_RESET 109
  125. #define EBI1_1X_DIV_RESET 110
  126. #define EBI1_RESET 111
  127. #define SFAB_SMPSS_S_RESET 112
  128. #define USB_PHY0_RESET 113
  129. #define USB_PHY1_RESET 114
  130. #define PRNG_RESET 115
  131. #endif