max77686-private.h 13 KB

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  1. /*
  2. * max77686-private.h - Voltage regulator driver for the Maxim 77686/802
  3. *
  4. * Copyright (C) 2012 Samsung Electrnoics
  5. * Chiwoong Byun <woong.byun@samsung.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20. */
  21. #ifndef __LINUX_MFD_MAX77686_PRIV_H
  22. #define __LINUX_MFD_MAX77686_PRIV_H
  23. #include <linux/i2c.h>
  24. #include <linux/regmap.h>
  25. #include <linux/module.h>
  26. #define MAX77686_REG_INVALID (0xff)
  27. /* MAX77686 PMIC registers */
  28. enum max77686_pmic_reg {
  29. MAX77686_REG_DEVICE_ID = 0x00,
  30. MAX77686_REG_INTSRC = 0x01,
  31. MAX77686_REG_INT1 = 0x02,
  32. MAX77686_REG_INT2 = 0x03,
  33. MAX77686_REG_INT1MSK = 0x04,
  34. MAX77686_REG_INT2MSK = 0x05,
  35. MAX77686_REG_STATUS1 = 0x06,
  36. MAX77686_REG_STATUS2 = 0x07,
  37. MAX77686_REG_PWRON = 0x08,
  38. MAX77686_REG_ONOFF_DELAY = 0x09,
  39. MAX77686_REG_MRSTB = 0x0A,
  40. /* Reserved: 0x0B-0x0F */
  41. MAX77686_REG_BUCK1CTRL = 0x10,
  42. MAX77686_REG_BUCK1OUT = 0x11,
  43. MAX77686_REG_BUCK2CTRL1 = 0x12,
  44. MAX77686_REG_BUCK234FREQ = 0x13,
  45. MAX77686_REG_BUCK2DVS1 = 0x14,
  46. MAX77686_REG_BUCK2DVS2 = 0x15,
  47. MAX77686_REG_BUCK2DVS3 = 0x16,
  48. MAX77686_REG_BUCK2DVS4 = 0x17,
  49. MAX77686_REG_BUCK2DVS5 = 0x18,
  50. MAX77686_REG_BUCK2DVS6 = 0x19,
  51. MAX77686_REG_BUCK2DVS7 = 0x1A,
  52. MAX77686_REG_BUCK2DVS8 = 0x1B,
  53. MAX77686_REG_BUCK3CTRL1 = 0x1C,
  54. /* Reserved: 0x1D */
  55. MAX77686_REG_BUCK3DVS1 = 0x1E,
  56. MAX77686_REG_BUCK3DVS2 = 0x1F,
  57. MAX77686_REG_BUCK3DVS3 = 0x20,
  58. MAX77686_REG_BUCK3DVS4 = 0x21,
  59. MAX77686_REG_BUCK3DVS5 = 0x22,
  60. MAX77686_REG_BUCK3DVS6 = 0x23,
  61. MAX77686_REG_BUCK3DVS7 = 0x24,
  62. MAX77686_REG_BUCK3DVS8 = 0x25,
  63. MAX77686_REG_BUCK4CTRL1 = 0x26,
  64. /* Reserved: 0x27 */
  65. MAX77686_REG_BUCK4DVS1 = 0x28,
  66. MAX77686_REG_BUCK4DVS2 = 0x29,
  67. MAX77686_REG_BUCK4DVS3 = 0x2A,
  68. MAX77686_REG_BUCK4DVS4 = 0x2B,
  69. MAX77686_REG_BUCK4DVS5 = 0x2C,
  70. MAX77686_REG_BUCK4DVS6 = 0x2D,
  71. MAX77686_REG_BUCK4DVS7 = 0x2E,
  72. MAX77686_REG_BUCK4DVS8 = 0x2F,
  73. MAX77686_REG_BUCK5CTRL = 0x30,
  74. MAX77686_REG_BUCK5OUT = 0x31,
  75. MAX77686_REG_BUCK6CTRL = 0x32,
  76. MAX77686_REG_BUCK6OUT = 0x33,
  77. MAX77686_REG_BUCK7CTRL = 0x34,
  78. MAX77686_REG_BUCK7OUT = 0x35,
  79. MAX77686_REG_BUCK8CTRL = 0x36,
  80. MAX77686_REG_BUCK8OUT = 0x37,
  81. MAX77686_REG_BUCK9CTRL = 0x38,
  82. MAX77686_REG_BUCK9OUT = 0x39,
  83. /* Reserved: 0x3A-0x3F */
  84. MAX77686_REG_LDO1CTRL1 = 0x40,
  85. MAX77686_REG_LDO2CTRL1 = 0x41,
  86. MAX77686_REG_LDO3CTRL1 = 0x42,
  87. MAX77686_REG_LDO4CTRL1 = 0x43,
  88. MAX77686_REG_LDO5CTRL1 = 0x44,
  89. MAX77686_REG_LDO6CTRL1 = 0x45,
  90. MAX77686_REG_LDO7CTRL1 = 0x46,
  91. MAX77686_REG_LDO8CTRL1 = 0x47,
  92. MAX77686_REG_LDO9CTRL1 = 0x48,
  93. MAX77686_REG_LDO10CTRL1 = 0x49,
  94. MAX77686_REG_LDO11CTRL1 = 0x4A,
  95. MAX77686_REG_LDO12CTRL1 = 0x4B,
  96. MAX77686_REG_LDO13CTRL1 = 0x4C,
  97. MAX77686_REG_LDO14CTRL1 = 0x4D,
  98. MAX77686_REG_LDO15CTRL1 = 0x4E,
  99. MAX77686_REG_LDO16CTRL1 = 0x4F,
  100. MAX77686_REG_LDO17CTRL1 = 0x50,
  101. MAX77686_REG_LDO18CTRL1 = 0x51,
  102. MAX77686_REG_LDO19CTRL1 = 0x52,
  103. MAX77686_REG_LDO20CTRL1 = 0x53,
  104. MAX77686_REG_LDO21CTRL1 = 0x54,
  105. MAX77686_REG_LDO22CTRL1 = 0x55,
  106. MAX77686_REG_LDO23CTRL1 = 0x56,
  107. MAX77686_REG_LDO24CTRL1 = 0x57,
  108. MAX77686_REG_LDO25CTRL1 = 0x58,
  109. MAX77686_REG_LDO26CTRL1 = 0x59,
  110. /* Reserved: 0x5A-0x5F */
  111. MAX77686_REG_LDO1CTRL2 = 0x60,
  112. MAX77686_REG_LDO2CTRL2 = 0x61,
  113. MAX77686_REG_LDO3CTRL2 = 0x62,
  114. MAX77686_REG_LDO4CTRL2 = 0x63,
  115. MAX77686_REG_LDO5CTRL2 = 0x64,
  116. MAX77686_REG_LDO6CTRL2 = 0x65,
  117. MAX77686_REG_LDO7CTRL2 = 0x66,
  118. MAX77686_REG_LDO8CTRL2 = 0x67,
  119. MAX77686_REG_LDO9CTRL2 = 0x68,
  120. MAX77686_REG_LDO10CTRL2 = 0x69,
  121. MAX77686_REG_LDO11CTRL2 = 0x6A,
  122. MAX77686_REG_LDO12CTRL2 = 0x6B,
  123. MAX77686_REG_LDO13CTRL2 = 0x6C,
  124. MAX77686_REG_LDO14CTRL2 = 0x6D,
  125. MAX77686_REG_LDO15CTRL2 = 0x6E,
  126. MAX77686_REG_LDO16CTRL2 = 0x6F,
  127. MAX77686_REG_LDO17CTRL2 = 0x70,
  128. MAX77686_REG_LDO18CTRL2 = 0x71,
  129. MAX77686_REG_LDO19CTRL2 = 0x72,
  130. MAX77686_REG_LDO20CTRL2 = 0x73,
  131. MAX77686_REG_LDO21CTRL2 = 0x74,
  132. MAX77686_REG_LDO22CTRL2 = 0x75,
  133. MAX77686_REG_LDO23CTRL2 = 0x76,
  134. MAX77686_REG_LDO24CTRL2 = 0x77,
  135. MAX77686_REG_LDO25CTRL2 = 0x78,
  136. MAX77686_REG_LDO26CTRL2 = 0x79,
  137. /* Reserved: 0x7A-0x7D */
  138. MAX77686_REG_BBAT_CHG = 0x7E,
  139. MAX77686_REG_32KHZ = 0x7F,
  140. MAX77686_REG_PMIC_END = 0x80,
  141. };
  142. enum max77686_rtc_reg {
  143. MAX77686_RTC_INT = 0x00,
  144. MAX77686_RTC_INTM = 0x01,
  145. MAX77686_RTC_CONTROLM = 0x02,
  146. MAX77686_RTC_CONTROL = 0x03,
  147. MAX77686_RTC_UPDATE0 = 0x04,
  148. /* Reserved: 0x5 */
  149. MAX77686_WTSR_SMPL_CNTL = 0x06,
  150. MAX77686_RTC_SEC = 0x07,
  151. MAX77686_RTC_MIN = 0x08,
  152. MAX77686_RTC_HOUR = 0x09,
  153. MAX77686_RTC_WEEKDAY = 0x0A,
  154. MAX77686_RTC_MONTH = 0x0B,
  155. MAX77686_RTC_YEAR = 0x0C,
  156. MAX77686_RTC_DATE = 0x0D,
  157. MAX77686_ALARM1_SEC = 0x0E,
  158. MAX77686_ALARM1_MIN = 0x0F,
  159. MAX77686_ALARM1_HOUR = 0x10,
  160. MAX77686_ALARM1_WEEKDAY = 0x11,
  161. MAX77686_ALARM1_MONTH = 0x12,
  162. MAX77686_ALARM1_YEAR = 0x13,
  163. MAX77686_ALARM1_DATE = 0x14,
  164. MAX77686_ALARM2_SEC = 0x15,
  165. MAX77686_ALARM2_MIN = 0x16,
  166. MAX77686_ALARM2_HOUR = 0x17,
  167. MAX77686_ALARM2_WEEKDAY = 0x18,
  168. MAX77686_ALARM2_MONTH = 0x19,
  169. MAX77686_ALARM2_YEAR = 0x1A,
  170. MAX77686_ALARM2_DATE = 0x1B,
  171. };
  172. /* MAX77802 PMIC registers */
  173. enum max77802_pmic_reg {
  174. MAX77802_REG_DEVICE_ID = 0x00,
  175. MAX77802_REG_INTSRC = 0x01,
  176. MAX77802_REG_INT1 = 0x02,
  177. MAX77802_REG_INT2 = 0x03,
  178. MAX77802_REG_INT1MSK = 0x04,
  179. MAX77802_REG_INT2MSK = 0x05,
  180. MAX77802_REG_STATUS1 = 0x06,
  181. MAX77802_REG_STATUS2 = 0x07,
  182. MAX77802_REG_PWRON = 0x08,
  183. /* Reserved: 0x09 */
  184. MAX77802_REG_MRSTB = 0x0A,
  185. MAX77802_REG_EPWRHOLD = 0x0B,
  186. /* Reserved: 0x0C-0x0D */
  187. MAX77802_REG_BOOSTCTRL = 0x0E,
  188. MAX77802_REG_BOOSTOUT = 0x0F,
  189. MAX77802_REG_BUCK1CTRL = 0x10,
  190. MAX77802_REG_BUCK1DVS1 = 0x11,
  191. MAX77802_REG_BUCK1DVS2 = 0x12,
  192. MAX77802_REG_BUCK1DVS3 = 0x13,
  193. MAX77802_REG_BUCK1DVS4 = 0x14,
  194. MAX77802_REG_BUCK1DVS5 = 0x15,
  195. MAX77802_REG_BUCK1DVS6 = 0x16,
  196. MAX77802_REG_BUCK1DVS7 = 0x17,
  197. MAX77802_REG_BUCK1DVS8 = 0x18,
  198. /* Reserved: 0x19 */
  199. MAX77802_REG_BUCK2CTRL1 = 0x1A,
  200. MAX77802_REG_BUCK2CTRL2 = 0x1B,
  201. MAX77802_REG_BUCK2PHTRAN = 0x1C,
  202. MAX77802_REG_BUCK2DVS1 = 0x1D,
  203. MAX77802_REG_BUCK2DVS2 = 0x1E,
  204. MAX77802_REG_BUCK2DVS3 = 0x1F,
  205. MAX77802_REG_BUCK2DVS4 = 0x20,
  206. MAX77802_REG_BUCK2DVS5 = 0x21,
  207. MAX77802_REG_BUCK2DVS6 = 0x22,
  208. MAX77802_REG_BUCK2DVS7 = 0x23,
  209. MAX77802_REG_BUCK2DVS8 = 0x24,
  210. /* Reserved: 0x25-0x26 */
  211. MAX77802_REG_BUCK3CTRL1 = 0x27,
  212. MAX77802_REG_BUCK3DVS1 = 0x28,
  213. MAX77802_REG_BUCK3DVS2 = 0x29,
  214. MAX77802_REG_BUCK3DVS3 = 0x2A,
  215. MAX77802_REG_BUCK3DVS4 = 0x2B,
  216. MAX77802_REG_BUCK3DVS5 = 0x2C,
  217. MAX77802_REG_BUCK3DVS6 = 0x2D,
  218. MAX77802_REG_BUCK3DVS7 = 0x2E,
  219. MAX77802_REG_BUCK3DVS8 = 0x2F,
  220. /* Reserved: 0x30-0x36 */
  221. MAX77802_REG_BUCK4CTRL1 = 0x37,
  222. MAX77802_REG_BUCK4DVS1 = 0x38,
  223. MAX77802_REG_BUCK4DVS2 = 0x39,
  224. MAX77802_REG_BUCK4DVS3 = 0x3A,
  225. MAX77802_REG_BUCK4DVS4 = 0x3B,
  226. MAX77802_REG_BUCK4DVS5 = 0x3C,
  227. MAX77802_REG_BUCK4DVS6 = 0x3D,
  228. MAX77802_REG_BUCK4DVS7 = 0x3E,
  229. MAX77802_REG_BUCK4DVS8 = 0x3F,
  230. /* Reserved: 0x40 */
  231. MAX77802_REG_BUCK5CTRL = 0x41,
  232. MAX77802_REG_BUCK5OUT = 0x42,
  233. /* Reserved: 0x43 */
  234. MAX77802_REG_BUCK6CTRL = 0x44,
  235. MAX77802_REG_BUCK6DVS1 = 0x45,
  236. MAX77802_REG_BUCK6DVS2 = 0x46,
  237. MAX77802_REG_BUCK6DVS3 = 0x47,
  238. MAX77802_REG_BUCK6DVS4 = 0x48,
  239. MAX77802_REG_BUCK6DVS5 = 0x49,
  240. MAX77802_REG_BUCK6DVS6 = 0x4A,
  241. MAX77802_REG_BUCK6DVS7 = 0x4B,
  242. MAX77802_REG_BUCK6DVS8 = 0x4C,
  243. /* Reserved: 0x4D */
  244. MAX77802_REG_BUCK7CTRL = 0x4E,
  245. MAX77802_REG_BUCK7OUT = 0x4F,
  246. /* Reserved: 0x50 */
  247. MAX77802_REG_BUCK8CTRL = 0x51,
  248. MAX77802_REG_BUCK8OUT = 0x52,
  249. /* Reserved: 0x53 */
  250. MAX77802_REG_BUCK9CTRL = 0x54,
  251. MAX77802_REG_BUCK9OUT = 0x55,
  252. /* Reserved: 0x56 */
  253. MAX77802_REG_BUCK10CTRL = 0x57,
  254. MAX77802_REG_BUCK10OUT = 0x58,
  255. /* Reserved: 0x59-0x5F */
  256. MAX77802_REG_LDO1CTRL1 = 0x60,
  257. MAX77802_REG_LDO2CTRL1 = 0x61,
  258. MAX77802_REG_LDO3CTRL1 = 0x62,
  259. MAX77802_REG_LDO4CTRL1 = 0x63,
  260. MAX77802_REG_LDO5CTRL1 = 0x64,
  261. MAX77802_REG_LDO6CTRL1 = 0x65,
  262. MAX77802_REG_LDO7CTRL1 = 0x66,
  263. MAX77802_REG_LDO8CTRL1 = 0x67,
  264. MAX77802_REG_LDO9CTRL1 = 0x68,
  265. MAX77802_REG_LDO10CTRL1 = 0x69,
  266. MAX77802_REG_LDO11CTRL1 = 0x6A,
  267. MAX77802_REG_LDO12CTRL1 = 0x6B,
  268. MAX77802_REG_LDO13CTRL1 = 0x6C,
  269. MAX77802_REG_LDO14CTRL1 = 0x6D,
  270. MAX77802_REG_LDO15CTRL1 = 0x6E,
  271. /* Reserved: 0x6F */
  272. MAX77802_REG_LDO17CTRL1 = 0x70,
  273. MAX77802_REG_LDO18CTRL1 = 0x71,
  274. MAX77802_REG_LDO19CTRL1 = 0x72,
  275. MAX77802_REG_LDO20CTRL1 = 0x73,
  276. MAX77802_REG_LDO21CTRL1 = 0x74,
  277. MAX77802_REG_LDO22CTRL1 = 0x75,
  278. MAX77802_REG_LDO23CTRL1 = 0x76,
  279. MAX77802_REG_LDO24CTRL1 = 0x77,
  280. MAX77802_REG_LDO25CTRL1 = 0x78,
  281. MAX77802_REG_LDO26CTRL1 = 0x79,
  282. MAX77802_REG_LDO27CTRL1 = 0x7A,
  283. MAX77802_REG_LDO28CTRL1 = 0x7B,
  284. MAX77802_REG_LDO29CTRL1 = 0x7C,
  285. MAX77802_REG_LDO30CTRL1 = 0x7D,
  286. /* Reserved: 0x7E */
  287. MAX77802_REG_LDO32CTRL1 = 0x7F,
  288. MAX77802_REG_LDO33CTRL1 = 0x80,
  289. MAX77802_REG_LDO34CTRL1 = 0x81,
  290. MAX77802_REG_LDO35CTRL1 = 0x82,
  291. /* Reserved: 0x83-0x8F */
  292. MAX77802_REG_LDO1CTRL2 = 0x90,
  293. MAX77802_REG_LDO2CTRL2 = 0x91,
  294. MAX77802_REG_LDO3CTRL2 = 0x92,
  295. MAX77802_REG_LDO4CTRL2 = 0x93,
  296. MAX77802_REG_LDO5CTRL2 = 0x94,
  297. MAX77802_REG_LDO6CTRL2 = 0x95,
  298. MAX77802_REG_LDO7CTRL2 = 0x96,
  299. MAX77802_REG_LDO8CTRL2 = 0x97,
  300. MAX77802_REG_LDO9CTRL2 = 0x98,
  301. MAX77802_REG_LDO10CTRL2 = 0x99,
  302. MAX77802_REG_LDO11CTRL2 = 0x9A,
  303. MAX77802_REG_LDO12CTRL2 = 0x9B,
  304. MAX77802_REG_LDO13CTRL2 = 0x9C,
  305. MAX77802_REG_LDO14CTRL2 = 0x9D,
  306. MAX77802_REG_LDO15CTRL2 = 0x9E,
  307. /* Reserved: 0x9F */
  308. MAX77802_REG_LDO17CTRL2 = 0xA0,
  309. MAX77802_REG_LDO18CTRL2 = 0xA1,
  310. MAX77802_REG_LDO19CTRL2 = 0xA2,
  311. MAX77802_REG_LDO20CTRL2 = 0xA3,
  312. MAX77802_REG_LDO21CTRL2 = 0xA4,
  313. MAX77802_REG_LDO22CTRL2 = 0xA5,
  314. MAX77802_REG_LDO23CTRL2 = 0xA6,
  315. MAX77802_REG_LDO24CTRL2 = 0xA7,
  316. MAX77802_REG_LDO25CTRL2 = 0xA8,
  317. MAX77802_REG_LDO26CTRL2 = 0xA9,
  318. MAX77802_REG_LDO27CTRL2 = 0xAA,
  319. MAX77802_REG_LDO28CTRL2 = 0xAB,
  320. MAX77802_REG_LDO29CTRL2 = 0xAC,
  321. MAX77802_REG_LDO30CTRL2 = 0xAD,
  322. /* Reserved: 0xAE */
  323. MAX77802_REG_LDO32CTRL2 = 0xAF,
  324. MAX77802_REG_LDO33CTRL2 = 0xB0,
  325. MAX77802_REG_LDO34CTRL2 = 0xB1,
  326. MAX77802_REG_LDO35CTRL2 = 0xB2,
  327. /* Reserved: 0xB3 */
  328. MAX77802_REG_BBAT_CHG = 0xB4,
  329. MAX77802_REG_32KHZ = 0xB5,
  330. MAX77802_REG_PMIC_END = 0xB6,
  331. };
  332. enum max77802_rtc_reg {
  333. MAX77802_RTC_INT = 0xC0,
  334. MAX77802_RTC_INTM = 0xC1,
  335. MAX77802_RTC_CONTROLM = 0xC2,
  336. MAX77802_RTC_CONTROL = 0xC3,
  337. MAX77802_RTC_UPDATE0 = 0xC4,
  338. MAX77802_RTC_UPDATE1 = 0xC5,
  339. MAX77802_WTSR_SMPL_CNTL = 0xC6,
  340. MAX77802_RTC_SEC = 0xC7,
  341. MAX77802_RTC_MIN = 0xC8,
  342. MAX77802_RTC_HOUR = 0xC9,
  343. MAX77802_RTC_WEEKDAY = 0xCA,
  344. MAX77802_RTC_MONTH = 0xCB,
  345. MAX77802_RTC_YEAR = 0xCC,
  346. MAX77802_RTC_DATE = 0xCD,
  347. MAX77802_RTC_AE1 = 0xCE,
  348. MAX77802_ALARM1_SEC = 0xCF,
  349. MAX77802_ALARM1_MIN = 0xD0,
  350. MAX77802_ALARM1_HOUR = 0xD1,
  351. MAX77802_ALARM1_WEEKDAY = 0xD2,
  352. MAX77802_ALARM1_MONTH = 0xD3,
  353. MAX77802_ALARM1_YEAR = 0xD4,
  354. MAX77802_ALARM1_DATE = 0xD5,
  355. MAX77802_RTC_AE2 = 0xD6,
  356. MAX77802_ALARM2_SEC = 0xD7,
  357. MAX77802_ALARM2_MIN = 0xD8,
  358. MAX77802_ALARM2_HOUR = 0xD9,
  359. MAX77802_ALARM2_WEEKDAY = 0xDA,
  360. MAX77802_ALARM2_MONTH = 0xDB,
  361. MAX77802_ALARM2_YEAR = 0xDC,
  362. MAX77802_ALARM2_DATE = 0xDD,
  363. MAX77802_RTC_END = 0xDF,
  364. };
  365. enum max77686_irq_source {
  366. PMIC_INT1 = 0,
  367. PMIC_INT2,
  368. RTC_INT,
  369. MAX77686_IRQ_GROUP_NR,
  370. };
  371. enum max77686_irq {
  372. MAX77686_PMICIRQ_PWRONF,
  373. MAX77686_PMICIRQ_PWRONR,
  374. MAX77686_PMICIRQ_JIGONBF,
  375. MAX77686_PMICIRQ_JIGONBR,
  376. MAX77686_PMICIRQ_ACOKBF,
  377. MAX77686_PMICIRQ_ACOKBR,
  378. MAX77686_PMICIRQ_ONKEY1S,
  379. MAX77686_PMICIRQ_MRSTB,
  380. MAX77686_PMICIRQ_140C,
  381. MAX77686_PMICIRQ_120C,
  382. MAX77686_RTCIRQ_RTC60S = 0,
  383. MAX77686_RTCIRQ_RTCA1,
  384. MAX77686_RTCIRQ_RTCA2,
  385. MAX77686_RTCIRQ_SMPL,
  386. MAX77686_RTCIRQ_RTC1S,
  387. MAX77686_RTCIRQ_WTSR,
  388. };
  389. #define MAX77686_INT1_PWRONF_MSK BIT(0)
  390. #define MAX77686_INT1_PWRONR_MSK BIT(1)
  391. #define MAX77686_INT1_JIGONBF_MSK BIT(2)
  392. #define MAX77686_INT1_JIGONBR_MSK BIT(3)
  393. #define MAX77686_INT1_ACOKBF_MSK BIT(4)
  394. #define MAX77686_INT1_ACOKBR_MSK BIT(5)
  395. #define MAX77686_INT1_ONKEY1S_MSK BIT(6)
  396. #define MAX77686_INT1_MRSTB_MSK BIT(7)
  397. #define MAX77686_INT2_140C_MSK BIT(0)
  398. #define MAX77686_INT2_120C_MSK BIT(1)
  399. #define MAX77686_RTCINT_RTC60S_MSK BIT(0)
  400. #define MAX77686_RTCINT_RTCA1_MSK BIT(1)
  401. #define MAX77686_RTCINT_RTCA2_MSK BIT(2)
  402. #define MAX77686_RTCINT_SMPL_MSK BIT(3)
  403. #define MAX77686_RTCINT_RTC1S_MSK BIT(4)
  404. #define MAX77686_RTCINT_WTSR_MSK BIT(5)
  405. struct max77686_dev {
  406. struct device *dev;
  407. struct i2c_client *i2c; /* 0xcc / PMIC, Battery Control, and FLASH */
  408. struct i2c_client *rtc; /* slave addr 0x0c */
  409. unsigned long type;
  410. struct regmap *regmap; /* regmap for mfd */
  411. struct regmap *rtc_regmap; /* regmap for rtc */
  412. struct regmap_irq_chip_data *irq_data;
  413. struct regmap_irq_chip_data *rtc_irq_data;
  414. int irq;
  415. struct mutex irqlock;
  416. int irq_masks_cur[MAX77686_IRQ_GROUP_NR];
  417. int irq_masks_cache[MAX77686_IRQ_GROUP_NR];
  418. };
  419. enum max77686_types {
  420. TYPE_MAX77686,
  421. TYPE_MAX77802,
  422. };
  423. extern int max77686_irq_init(struct max77686_dev *max77686);
  424. extern void max77686_irq_exit(struct max77686_dev *max77686);
  425. extern int max77686_irq_resume(struct max77686_dev *max77686);
  426. #endif /* __LINUX_MFD_MAX77686_PRIV_H */