tmio.h 4.2 KB

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  1. #ifndef MFD_TMIO_H
  2. #define MFD_TMIO_H
  3. #include <linux/device.h>
  4. #include <linux/fb.h>
  5. #include <linux/io.h>
  6. #include <linux/jiffies.h>
  7. #include <linux/mmc/card.h>
  8. #include <linux/platform_device.h>
  9. #include <linux/pm_runtime.h>
  10. #define tmio_ioread8(addr) readb(addr)
  11. #define tmio_ioread16(addr) readw(addr)
  12. #define tmio_ioread16_rep(r, b, l) readsw(r, b, l)
  13. #define tmio_ioread32(addr) \
  14. (((u32) readw((addr))) | (((u32) readw((addr) + 2)) << 16))
  15. #define tmio_iowrite8(val, addr) writeb((val), (addr))
  16. #define tmio_iowrite16(val, addr) writew((val), (addr))
  17. #define tmio_iowrite16_rep(r, b, l) writesw(r, b, l)
  18. #define tmio_iowrite32(val, addr) \
  19. do { \
  20. writew((val), (addr)); \
  21. writew((val) >> 16, (addr) + 2); \
  22. } while (0)
  23. #define CNF_CMD 0x04
  24. #define CNF_CTL_BASE 0x10
  25. #define CNF_INT_PIN 0x3d
  26. #define CNF_STOP_CLK_CTL 0x40
  27. #define CNF_GCLK_CTL 0x41
  28. #define CNF_SD_CLK_MODE 0x42
  29. #define CNF_PIN_STATUS 0x44
  30. #define CNF_PWR_CTL_1 0x48
  31. #define CNF_PWR_CTL_2 0x49
  32. #define CNF_PWR_CTL_3 0x4a
  33. #define CNF_CARD_DETECT_MODE 0x4c
  34. #define CNF_SD_SLOT 0x50
  35. #define CNF_EXT_GCLK_CTL_1 0xf0
  36. #define CNF_EXT_GCLK_CTL_2 0xf1
  37. #define CNF_EXT_GCLK_CTL_3 0xf9
  38. #define CNF_SD_LED_EN_1 0xfa
  39. #define CNF_SD_LED_EN_2 0xfe
  40. #define SDCREN 0x2 /* Enable access to MMC CTL regs. (flag in COMMAND_REG)*/
  41. #define sd_config_write8(base, shift, reg, val) \
  42. tmio_iowrite8((val), (base) + ((reg) << (shift)))
  43. #define sd_config_write16(base, shift, reg, val) \
  44. tmio_iowrite16((val), (base) + ((reg) << (shift)))
  45. #define sd_config_write32(base, shift, reg, val) \
  46. do { \
  47. tmio_iowrite16((val), (base) + ((reg) << (shift))); \
  48. tmio_iowrite16((val) >> 16, (base) + ((reg + 2) << (shift))); \
  49. } while (0)
  50. /* tmio MMC platform flags */
  51. #define TMIO_MMC_WRPROTECT_DISABLE (1 << 0)
  52. /*
  53. * Some controllers can support a 2-byte block size when the bus width
  54. * is configured in 4-bit mode.
  55. */
  56. #define TMIO_MMC_BLKSZ_2BYTES (1 << 1)
  57. /*
  58. * Some controllers can support SDIO IRQ signalling.
  59. */
  60. #define TMIO_MMC_SDIO_IRQ (1 << 2)
  61. /*
  62. * Some controllers require waiting for the SD bus to become
  63. * idle before writing to some registers.
  64. */
  65. #define TMIO_MMC_HAS_IDLE_WAIT (1 << 4)
  66. /*
  67. * A GPIO is used for card hotplug detection. We need an extra flag for this,
  68. * because 0 is a valid GPIO number too, and requiring users to specify
  69. * cd_gpio < 0 to disable GPIO hotplug would break backwards compatibility.
  70. */
  71. #define TMIO_MMC_USE_GPIO_CD (1 << 5)
  72. /*
  73. * Some controllers doesn't have over 0x100 register.
  74. * it is used to checking accessibility of
  75. * CTL_SD_CARD_CLK_CTL / CTL_CLK_AND_WAIT_CTL
  76. */
  77. #define TMIO_MMC_HAVE_HIGH_REG (1 << 6)
  78. /*
  79. * Some controllers have CMD12 automatically
  80. * issue/non-issue register
  81. */
  82. #define TMIO_MMC_HAVE_CMD12_CTRL (1 << 7)
  83. /*
  84. * Some controllers needs to set 1 on SDIO status reserved bits
  85. */
  86. #define TMIO_MMC_SDIO_STATUS_QUIRK (1 << 8)
  87. /*
  88. * Some controllers allows to set SDx actual clock
  89. */
  90. #define TMIO_MMC_CLK_ACTUAL (1 << 10)
  91. int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
  92. int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
  93. void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state);
  94. void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state);
  95. struct dma_chan;
  96. /*
  97. * data for the MMC controller
  98. */
  99. struct tmio_mmc_data {
  100. void *chan_priv_tx;
  101. void *chan_priv_rx;
  102. unsigned int hclk;
  103. unsigned long capabilities;
  104. unsigned long capabilities2;
  105. unsigned long flags;
  106. u32 ocr_mask; /* available voltages */
  107. unsigned int cd_gpio;
  108. int alignment_shift;
  109. dma_addr_t dma_rx_offset;
  110. void (*set_pwr)(struct platform_device *host, int state);
  111. void (*set_clk_div)(struct platform_device *host, int state);
  112. };
  113. /*
  114. * data for the NAND controller
  115. */
  116. struct tmio_nand_data {
  117. struct nand_bbt_descr *badblock_pattern;
  118. struct mtd_partition *partition;
  119. unsigned int num_partitions;
  120. };
  121. #define FBIO_TMIO_ACC_WRITE 0x7C639300
  122. #define FBIO_TMIO_ACC_SYNC 0x7C639301
  123. struct tmio_fb_data {
  124. int (*lcd_set_power)(struct platform_device *fb_dev,
  125. bool on);
  126. int (*lcd_mode)(struct platform_device *fb_dev,
  127. const struct fb_videomode *mode);
  128. int num_modes;
  129. struct fb_videomode *modes;
  130. /* in mm: size of screen */
  131. int height;
  132. int width;
  133. };
  134. #endif