tps65217.h 8.0 KB

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  1. /*
  2. * linux/mfd/tps65217.h
  3. *
  4. * Functions to access TPS65217 power management chip.
  5. *
  6. * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation version 2.
  11. *
  12. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  13. * kind, whether express or implied; without even the implied warranty
  14. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. */
  17. #ifndef __LINUX_MFD_TPS65217_H
  18. #define __LINUX_MFD_TPS65217_H
  19. #include <linux/i2c.h>
  20. #include <linux/regulator/driver.h>
  21. #include <linux/regulator/machine.h>
  22. /* TPS chip id list */
  23. #define TPS65217 0xF0
  24. /* I2C ID for TPS65217 part */
  25. #define TPS65217_I2C_ID 0x24
  26. /* All register addresses */
  27. #define TPS65217_REG_CHIPID 0X00
  28. #define TPS65217_REG_PPATH 0X01
  29. #define TPS65217_REG_INT 0X02
  30. #define TPS65217_REG_CHGCONFIG0 0X03
  31. #define TPS65217_REG_CHGCONFIG1 0X04
  32. #define TPS65217_REG_CHGCONFIG2 0X05
  33. #define TPS65217_REG_CHGCONFIG3 0X06
  34. #define TPS65217_REG_WLEDCTRL1 0X07
  35. #define TPS65217_REG_WLEDCTRL2 0X08
  36. #define TPS65217_REG_MUXCTRL 0X09
  37. #define TPS65217_REG_STATUS 0X0A
  38. #define TPS65217_REG_PASSWORD 0X0B
  39. #define TPS65217_REG_PGOOD 0X0C
  40. #define TPS65217_REG_DEFPG 0X0D
  41. #define TPS65217_REG_DEFDCDC1 0X0E
  42. #define TPS65217_REG_DEFDCDC2 0X0F
  43. #define TPS65217_REG_DEFDCDC3 0X10
  44. #define TPS65217_REG_DEFSLEW 0X11
  45. #define TPS65217_REG_DEFLDO1 0X12
  46. #define TPS65217_REG_DEFLDO2 0X13
  47. #define TPS65217_REG_DEFLS1 0X14
  48. #define TPS65217_REG_DEFLS2 0X15
  49. #define TPS65217_REG_ENABLE 0X16
  50. #define TPS65217_REG_DEFUVLO 0X18
  51. #define TPS65217_REG_SEQ1 0X19
  52. #define TPS65217_REG_SEQ2 0X1A
  53. #define TPS65217_REG_SEQ3 0X1B
  54. #define TPS65217_REG_SEQ4 0X1C
  55. #define TPS65217_REG_SEQ5 0X1D
  56. #define TPS65217_REG_SEQ6 0X1E
  57. #define TPS65217_REG_MAX TPS65217_REG_SEQ6
  58. /* Register field definitions */
  59. #define TPS65217_CHIPID_CHIP_MASK 0xF0
  60. #define TPS65217_CHIPID_REV_MASK 0x0F
  61. #define TPS65217_PPATH_ACSINK_ENABLE BIT(7)
  62. #define TPS65217_PPATH_USBSINK_ENABLE BIT(6)
  63. #define TPS65217_PPATH_AC_PW_ENABLE BIT(5)
  64. #define TPS65217_PPATH_USB_PW_ENABLE BIT(4)
  65. #define TPS65217_PPATH_AC_CURRENT_MASK 0x0C
  66. #define TPS65217_PPATH_USB_CURRENT_MASK 0x03
  67. #define TPS65217_INT_PBM BIT(6)
  68. #define TPS65217_INT_ACM BIT(5)
  69. #define TPS65217_INT_USBM BIT(4)
  70. #define TPS65217_INT_PBI BIT(2)
  71. #define TPS65217_INT_ACI BIT(1)
  72. #define TPS65217_INT_USBI BIT(0)
  73. #define TPS65217_CHGCONFIG0_TREG BIT(7)
  74. #define TPS65217_CHGCONFIG0_DPPM BIT(6)
  75. #define TPS65217_CHGCONFIG0_TSUSP BIT(5)
  76. #define TPS65217_CHGCONFIG0_TERMI BIT(4)
  77. #define TPS65217_CHGCONFIG0_ACTIVE BIT(3)
  78. #define TPS65217_CHGCONFIG0_CHGTOUT BIT(2)
  79. #define TPS65217_CHGCONFIG0_PCHGTOUT BIT(1)
  80. #define TPS65217_CHGCONFIG0_BATTEMP BIT(0)
  81. #define TPS65217_CHGCONFIG1_TMR_MASK 0xC0
  82. #define TPS65217_CHGCONFIG1_TMR_ENABLE BIT(5)
  83. #define TPS65217_CHGCONFIG1_NTC_TYPE BIT(4)
  84. #define TPS65217_CHGCONFIG1_RESET BIT(3)
  85. #define TPS65217_CHGCONFIG1_TERM BIT(2)
  86. #define TPS65217_CHGCONFIG1_SUSP BIT(1)
  87. #define TPS65217_CHGCONFIG1_CHG_EN BIT(0)
  88. #define TPS65217_CHGCONFIG2_DYNTMR BIT(7)
  89. #define TPS65217_CHGCONFIG2_VPREGHG BIT(6)
  90. #define TPS65217_CHGCONFIG2_VOREG_MASK 0x30
  91. #define TPS65217_CHGCONFIG3_ICHRG_MASK 0xC0
  92. #define TPS65217_CHGCONFIG3_DPPMTH_MASK 0x30
  93. #define TPS65217_CHGCONFIG2_PCHRGT BIT(3)
  94. #define TPS65217_CHGCONFIG2_TERMIF 0x06
  95. #define TPS65217_CHGCONFIG2_TRANGE BIT(0)
  96. #define TPS65217_WLEDCTRL1_ISINK_ENABLE BIT(3)
  97. #define TPS65217_WLEDCTRL1_ISEL BIT(2)
  98. #define TPS65217_WLEDCTRL1_FDIM_MASK 0x03
  99. #define TPS65217_WLEDCTRL2_DUTY_MASK 0x7F
  100. #define TPS65217_MUXCTRL_MUX_MASK 0x07
  101. #define TPS65217_STATUS_OFF BIT(7)
  102. #define TPS65217_STATUS_ACPWR BIT(3)
  103. #define TPS65217_STATUS_USBPWR BIT(2)
  104. #define TPS65217_STATUS_PB BIT(0)
  105. #define TPS65217_PASSWORD_REGS_UNLOCK 0x7D
  106. #define TPS65217_PGOOD_LDO3_PG BIT(6)
  107. #define TPS65217_PGOOD_LDO4_PG BIT(5)
  108. #define TPS65217_PGOOD_DC1_PG BIT(4)
  109. #define TPS65217_PGOOD_DC2_PG BIT(3)
  110. #define TPS65217_PGOOD_DC3_PG BIT(2)
  111. #define TPS65217_PGOOD_LDO1_PG BIT(1)
  112. #define TPS65217_PGOOD_LDO2_PG BIT(0)
  113. #define TPS65217_DEFPG_LDO1PGM BIT(3)
  114. #define TPS65217_DEFPG_LDO2PGM BIT(2)
  115. #define TPS65217_DEFPG_PGDLY_MASK 0x03
  116. #define TPS65217_DEFDCDCX_XADJX BIT(7)
  117. #define TPS65217_DEFDCDCX_DCDC_MASK 0x3F
  118. #define TPS65217_DEFSLEW_GO BIT(7)
  119. #define TPS65217_DEFSLEW_GODSBL BIT(6)
  120. #define TPS65217_DEFSLEW_PFM_EN1 BIT(5)
  121. #define TPS65217_DEFSLEW_PFM_EN2 BIT(4)
  122. #define TPS65217_DEFSLEW_PFM_EN3 BIT(3)
  123. #define TPS65217_DEFSLEW_SLEW_MASK 0x07
  124. #define TPS65217_DEFLDO1_LDO1_MASK 0x0F
  125. #define TPS65217_DEFLDO2_TRACK BIT(6)
  126. #define TPS65217_DEFLDO2_LDO2_MASK 0x3F
  127. #define TPS65217_DEFLDO3_LDO3_EN BIT(5)
  128. #define TPS65217_DEFLDO3_LDO3_MASK 0x1F
  129. #define TPS65217_DEFLDO4_LDO4_EN BIT(5)
  130. #define TPS65217_DEFLDO4_LDO4_MASK 0x1F
  131. #define TPS65217_ENABLE_LS1_EN BIT(6)
  132. #define TPS65217_ENABLE_LS2_EN BIT(5)
  133. #define TPS65217_ENABLE_DC1_EN BIT(4)
  134. #define TPS65217_ENABLE_DC2_EN BIT(3)
  135. #define TPS65217_ENABLE_DC3_EN BIT(2)
  136. #define TPS65217_ENABLE_LDO1_EN BIT(1)
  137. #define TPS65217_ENABLE_LDO2_EN BIT(0)
  138. #define TPS65217_DEFUVLO_UVLOHYS BIT(2)
  139. #define TPS65217_DEFUVLO_UVLO_MASK 0x03
  140. #define TPS65217_SEQ1_DC1_SEQ_MASK 0xF0
  141. #define TPS65217_SEQ1_DC2_SEQ_MASK 0x0F
  142. #define TPS65217_SEQ2_DC3_SEQ_MASK 0xF0
  143. #define TPS65217_SEQ2_LDO1_SEQ_MASK 0x0F
  144. #define TPS65217_SEQ3_LDO2_SEQ_MASK 0xF0
  145. #define TPS65217_SEQ3_LDO3_SEQ_MASK 0x0F
  146. #define TPS65217_SEQ4_LDO4_SEQ_MASK 0xF0
  147. #define TPS65217_SEQ5_DLY1_MASK 0xC0
  148. #define TPS65217_SEQ5_DLY2_MASK 0x30
  149. #define TPS65217_SEQ5_DLY3_MASK 0x0C
  150. #define TPS65217_SEQ5_DLY4_MASK 0x03
  151. #define TPS65217_SEQ6_DLY5_MASK 0xC0
  152. #define TPS65217_SEQ6_DLY6_MASK 0x30
  153. #define TPS65217_SEQ6_SEQUP BIT(2)
  154. #define TPS65217_SEQ6_SEQDWN BIT(1)
  155. #define TPS65217_SEQ6_INSTDWN BIT(0)
  156. #define TPS65217_MAX_REGISTER 0x1E
  157. #define TPS65217_PROTECT_NONE 0
  158. #define TPS65217_PROTECT_L1 1
  159. #define TPS65217_PROTECT_L2 2
  160. enum tps65217_regulator_id {
  161. /* DCDC's */
  162. TPS65217_DCDC_1,
  163. TPS65217_DCDC_2,
  164. TPS65217_DCDC_3,
  165. /* LDOs */
  166. TPS65217_LDO_1,
  167. TPS65217_LDO_2,
  168. TPS65217_LDO_3,
  169. TPS65217_LDO_4,
  170. };
  171. #define TPS65217_MAX_REG_ID TPS65217_LDO_4
  172. /* Number of step-down converters available */
  173. #define TPS65217_NUM_DCDC 3
  174. /* Number of LDO voltage regulators available */
  175. #define TPS65217_NUM_LDO 4
  176. /* Number of total regulators available */
  177. #define TPS65217_NUM_REGULATOR (TPS65217_NUM_DCDC + TPS65217_NUM_LDO)
  178. enum tps65217_bl_isel {
  179. TPS65217_BL_ISET1 = 1,
  180. TPS65217_BL_ISET2,
  181. };
  182. enum tps65217_bl_fdim {
  183. TPS65217_BL_FDIM_100HZ,
  184. TPS65217_BL_FDIM_200HZ,
  185. TPS65217_BL_FDIM_500HZ,
  186. TPS65217_BL_FDIM_1000HZ,
  187. };
  188. struct tps65217_bl_pdata {
  189. enum tps65217_bl_isel isel;
  190. enum tps65217_bl_fdim fdim;
  191. int dft_brightness;
  192. };
  193. /**
  194. * struct tps65217_board - packages regulator init data
  195. * @tps65217_regulator_data: regulator initialization values
  196. *
  197. * Board data may be used to initialize regulator.
  198. */
  199. struct tps65217_board {
  200. struct regulator_init_data *tps65217_init_data[TPS65217_NUM_REGULATOR];
  201. struct device_node *of_node[TPS65217_NUM_REGULATOR];
  202. struct tps65217_bl_pdata *bl_pdata;
  203. };
  204. /**
  205. * struct tps65217 - tps65217 sub-driver chip access routines
  206. *
  207. * Device data may be used to access the TPS65217 chip
  208. */
  209. struct tps65217 {
  210. struct device *dev;
  211. struct tps65217_board *pdata;
  212. unsigned long id;
  213. struct regulator_desc desc[TPS65217_NUM_REGULATOR];
  214. struct regmap *regmap;
  215. };
  216. static inline struct tps65217 *dev_to_tps65217(struct device *dev)
  217. {
  218. return dev_get_drvdata(dev);
  219. }
  220. static inline unsigned long tps65217_chip_id(struct tps65217 *tps65217)
  221. {
  222. return tps65217->id;
  223. }
  224. int tps65217_reg_read(struct tps65217 *tps, unsigned int reg,
  225. unsigned int *val);
  226. int tps65217_reg_write(struct tps65217 *tps, unsigned int reg,
  227. unsigned int val, unsigned int level);
  228. int tps65217_set_bits(struct tps65217 *tps, unsigned int reg,
  229. unsigned int mask, unsigned int val, unsigned int level);
  230. int tps65217_clear_bits(struct tps65217 *tps, unsigned int reg,
  231. unsigned int mask, unsigned int level);
  232. #endif /* __LINUX_MFD_TPS65217_H */