digi00x.h 4.7 KB

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  1. /*
  2. * digi00x.h - a part of driver for Digidesign Digi 002/003 family
  3. *
  4. * Copyright (c) 2014-2015 Takashi Sakamoto
  5. *
  6. * Licensed under the terms of the GNU General Public License, version 2.
  7. */
  8. #ifndef SOUND_DIGI00X_H_INCLUDED
  9. #define SOUND_DIGI00X_H_INCLUDED
  10. #include <linux/compat.h>
  11. #include <linux/device.h>
  12. #include <linux/firewire.h>
  13. #include <linux/module.h>
  14. #include <linux/mod_devicetable.h>
  15. #include <linux/delay.h>
  16. #include <linux/slab.h>
  17. #include <sound/core.h>
  18. #include <sound/initval.h>
  19. #include <sound/info.h>
  20. #include <sound/pcm.h>
  21. #include <sound/pcm_params.h>
  22. #include <sound/firewire.h>
  23. #include <sound/hwdep.h>
  24. #include <sound/rawmidi.h>
  25. #include "../lib.h"
  26. #include "../iso-resources.h"
  27. #include "../amdtp-stream.h"
  28. struct snd_dg00x {
  29. struct snd_card *card;
  30. struct fw_unit *unit;
  31. struct mutex mutex;
  32. spinlock_t lock;
  33. struct amdtp_stream tx_stream;
  34. struct fw_iso_resources tx_resources;
  35. struct amdtp_stream rx_stream;
  36. struct fw_iso_resources rx_resources;
  37. unsigned int substreams_counter;
  38. /* for uapi */
  39. int dev_lock_count;
  40. bool dev_lock_changed;
  41. wait_queue_head_t hwdep_wait;
  42. /* For asynchronous messages. */
  43. struct fw_address_handler async_handler;
  44. u32 msg;
  45. /* For asynchronous MIDI controls. */
  46. struct snd_rawmidi_substream *in_control;
  47. struct snd_fw_async_midi_port out_control;
  48. };
  49. #define DG00X_ADDR_BASE 0xffffe0000000ull
  50. #define DG00X_OFFSET_STREAMING_STATE 0x0000
  51. #define DG00X_OFFSET_STREAMING_SET 0x0004
  52. #define DG00X_OFFSET_MIDI_CTL_ADDR 0x0008
  53. /* For LSB of the address 0x000c */
  54. /* unknown 0x0010 */
  55. #define DG00X_OFFSET_MESSAGE_ADDR 0x0014
  56. /* For LSB of the address 0x0018 */
  57. /* unknown 0x001c */
  58. /* unknown 0x0020 */
  59. /* not used 0x0024--0x00ff */
  60. #define DG00X_OFFSET_ISOC_CHANNELS 0x0100
  61. /* unknown 0x0104 */
  62. /* unknown 0x0108 */
  63. /* unknown 0x010c */
  64. #define DG00X_OFFSET_LOCAL_RATE 0x0110
  65. #define DG00X_OFFSET_EXTERNAL_RATE 0x0114
  66. #define DG00X_OFFSET_CLOCK_SOURCE 0x0118
  67. #define DG00X_OFFSET_OPT_IFACE_MODE 0x011c
  68. /* unknown 0x0120 */
  69. /* Mixer control on/off 0x0124 */
  70. /* unknown 0x0128 */
  71. #define DG00X_OFFSET_DETECT_EXTERNAL 0x012c
  72. /* unknown 0x0138 */
  73. #define DG00X_OFFSET_MMC 0x0400
  74. enum snd_dg00x_rate {
  75. SND_DG00X_RATE_44100 = 0,
  76. SND_DG00X_RATE_48000,
  77. SND_DG00X_RATE_88200,
  78. SND_DG00X_RATE_96000,
  79. SND_DG00X_RATE_COUNT,
  80. };
  81. enum snd_dg00x_clock {
  82. SND_DG00X_CLOCK_INTERNAL = 0,
  83. SND_DG00X_CLOCK_SPDIF,
  84. SND_DG00X_CLOCK_ADAT,
  85. SND_DG00X_CLOCK_WORD,
  86. SND_DG00X_CLOCK_COUNT,
  87. };
  88. enum snd_dg00x_optical_mode {
  89. SND_DG00X_OPT_IFACE_MODE_ADAT = 0,
  90. SND_DG00X_OPT_IFACE_MODE_SPDIF,
  91. SND_DG00X_OPT_IFACE_MODE_COUNT,
  92. };
  93. #define DOT_MIDI_IN_PORTS 1
  94. #define DOT_MIDI_OUT_PORTS 2
  95. int amdtp_dot_init(struct amdtp_stream *s, struct fw_unit *unit,
  96. enum amdtp_stream_direction dir);
  97. int amdtp_dot_set_parameters(struct amdtp_stream *s, unsigned int rate,
  98. unsigned int pcm_channels);
  99. void amdtp_dot_reset(struct amdtp_stream *s);
  100. int amdtp_dot_add_pcm_hw_constraints(struct amdtp_stream *s,
  101. struct snd_pcm_runtime *runtime);
  102. void amdtp_dot_set_pcm_format(struct amdtp_stream *s, snd_pcm_format_t format);
  103. void amdtp_dot_midi_trigger(struct amdtp_stream *s, unsigned int port,
  104. struct snd_rawmidi_substream *midi);
  105. int snd_dg00x_transaction_register(struct snd_dg00x *dg00x);
  106. int snd_dg00x_transaction_reregister(struct snd_dg00x *dg00x);
  107. void snd_dg00x_transaction_unregister(struct snd_dg00x *dg00x);
  108. extern const unsigned int snd_dg00x_stream_rates[SND_DG00X_RATE_COUNT];
  109. extern const unsigned int snd_dg00x_stream_pcm_channels[SND_DG00X_RATE_COUNT];
  110. int snd_dg00x_stream_get_external_rate(struct snd_dg00x *dg00x,
  111. unsigned int *rate);
  112. int snd_dg00x_stream_get_local_rate(struct snd_dg00x *dg00x,
  113. unsigned int *rate);
  114. int snd_dg00x_stream_set_local_rate(struct snd_dg00x *dg00x, unsigned int rate);
  115. int snd_dg00x_stream_get_clock(struct snd_dg00x *dg00x,
  116. enum snd_dg00x_clock *clock);
  117. int snd_dg00x_stream_check_external_clock(struct snd_dg00x *dg00x,
  118. bool *detect);
  119. int snd_dg00x_stream_init_duplex(struct snd_dg00x *dg00x);
  120. int snd_dg00x_stream_start_duplex(struct snd_dg00x *dg00x, unsigned int rate);
  121. void snd_dg00x_stream_stop_duplex(struct snd_dg00x *dg00x);
  122. void snd_dg00x_stream_update_duplex(struct snd_dg00x *dg00x);
  123. void snd_dg00x_stream_destroy_duplex(struct snd_dg00x *dg00x);
  124. void snd_dg00x_stream_lock_changed(struct snd_dg00x *dg00x);
  125. int snd_dg00x_stream_lock_try(struct snd_dg00x *dg00x);
  126. void snd_dg00x_stream_lock_release(struct snd_dg00x *dg00x);
  127. void snd_dg00x_proc_init(struct snd_dg00x *dg00x);
  128. int snd_dg00x_create_pcm_devices(struct snd_dg00x *dg00x);
  129. int snd_dg00x_create_midi_devices(struct snd_dg00x *dg00x);
  130. int snd_dg00x_create_hwdep_device(struct snd_dg00x *dg00x);
  131. #endif