tascam-stream.c 11 KB

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  1. /*
  2. * tascam-stream.c - a part of driver for TASCAM FireWire series
  3. *
  4. * Copyright (c) 2015 Takashi Sakamoto
  5. *
  6. * Licensed under the terms of the GNU General Public License, version 2.
  7. */
  8. #include <linux/delay.h>
  9. #include "tascam.h"
  10. #define CALLBACK_TIMEOUT 500
  11. static int get_clock(struct snd_tscm *tscm, u32 *data)
  12. {
  13. __be32 reg;
  14. int err;
  15. err = snd_fw_transaction(tscm->unit, TCODE_READ_QUADLET_REQUEST,
  16. TSCM_ADDR_BASE + TSCM_OFFSET_CLOCK_STATUS,
  17. &reg, sizeof(reg), 0);
  18. if (err >= 0)
  19. *data = be32_to_cpu(reg);
  20. return err;
  21. }
  22. static int set_clock(struct snd_tscm *tscm, unsigned int rate,
  23. enum snd_tscm_clock clock)
  24. {
  25. u32 data;
  26. __be32 reg;
  27. int err;
  28. err = get_clock(tscm, &data);
  29. if (err < 0)
  30. return err;
  31. data &= 0x0000ffff;
  32. if (rate > 0) {
  33. data &= 0x000000ff;
  34. /* Base rate. */
  35. if ((rate % 44100) == 0) {
  36. data |= 0x00000100;
  37. /* Multiplier. */
  38. if (rate / 44100 == 2)
  39. data |= 0x00008000;
  40. } else if ((rate % 48000) == 0) {
  41. data |= 0x00000200;
  42. /* Multiplier. */
  43. if (rate / 48000 == 2)
  44. data |= 0x00008000;
  45. } else {
  46. return -EAGAIN;
  47. }
  48. }
  49. if (clock != INT_MAX) {
  50. data &= 0x0000ff00;
  51. data |= clock + 1;
  52. }
  53. reg = cpu_to_be32(data);
  54. err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
  55. TSCM_ADDR_BASE + TSCM_OFFSET_CLOCK_STATUS,
  56. &reg, sizeof(reg), 0);
  57. if (err < 0)
  58. return err;
  59. if (data & 0x00008000)
  60. reg = cpu_to_be32(0x0000001a);
  61. else
  62. reg = cpu_to_be32(0x0000000d);
  63. return snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
  64. TSCM_ADDR_BASE + TSCM_OFFSET_MULTIPLEX_MODE,
  65. &reg, sizeof(reg), 0);
  66. }
  67. int snd_tscm_stream_get_rate(struct snd_tscm *tscm, unsigned int *rate)
  68. {
  69. u32 data = 0x0;
  70. unsigned int trials = 0;
  71. int err;
  72. while (data == 0x0 || trials++ < 5) {
  73. err = get_clock(tscm, &data);
  74. if (err < 0)
  75. return err;
  76. data = (data & 0xff000000) >> 24;
  77. }
  78. /* Check base rate. */
  79. if ((data & 0x0f) == 0x01)
  80. *rate = 44100;
  81. else if ((data & 0x0f) == 0x02)
  82. *rate = 48000;
  83. else
  84. return -EAGAIN;
  85. /* Check multiplier. */
  86. if ((data & 0xf0) == 0x80)
  87. *rate *= 2;
  88. else if ((data & 0xf0) != 0x00)
  89. return -EAGAIN;
  90. return err;
  91. }
  92. int snd_tscm_stream_get_clock(struct snd_tscm *tscm, enum snd_tscm_clock *clock)
  93. {
  94. u32 data;
  95. int err;
  96. err = get_clock(tscm, &data);
  97. if (err < 0)
  98. return err;
  99. *clock = ((data & 0x00ff0000) >> 16) - 1;
  100. if (*clock < 0 || *clock > SND_TSCM_CLOCK_ADAT)
  101. return -EIO;
  102. return 0;
  103. }
  104. static int enable_data_channels(struct snd_tscm *tscm)
  105. {
  106. __be32 reg;
  107. u32 data;
  108. unsigned int i;
  109. int err;
  110. data = 0;
  111. for (i = 0; i < tscm->spec->pcm_capture_analog_channels; ++i)
  112. data |= BIT(i);
  113. if (tscm->spec->has_adat)
  114. data |= 0x0000ff00;
  115. if (tscm->spec->has_spdif)
  116. data |= 0x00030000;
  117. reg = cpu_to_be32(data);
  118. err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
  119. TSCM_ADDR_BASE + TSCM_OFFSET_TX_PCM_CHANNELS,
  120. &reg, sizeof(reg), 0);
  121. if (err < 0)
  122. return err;
  123. data = 0;
  124. for (i = 0; i < tscm->spec->pcm_playback_analog_channels; ++i)
  125. data |= BIT(i);
  126. if (tscm->spec->has_adat)
  127. data |= 0x0000ff00;
  128. if (tscm->spec->has_spdif)
  129. data |= 0x00030000;
  130. reg = cpu_to_be32(data);
  131. return snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
  132. TSCM_ADDR_BASE + TSCM_OFFSET_RX_PCM_CHANNELS,
  133. &reg, sizeof(reg), 0);
  134. }
  135. static int set_stream_formats(struct snd_tscm *tscm, unsigned int rate)
  136. {
  137. __be32 reg;
  138. int err;
  139. /* Set an option for unknown purpose. */
  140. reg = cpu_to_be32(0x00200000);
  141. err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
  142. TSCM_ADDR_BASE + TSCM_OFFSET_SET_OPTION,
  143. &reg, sizeof(reg), 0);
  144. if (err < 0)
  145. return err;
  146. err = enable_data_channels(tscm);
  147. if (err < 0)
  148. return err;
  149. return set_clock(tscm, rate, INT_MAX);
  150. }
  151. static void finish_session(struct snd_tscm *tscm)
  152. {
  153. __be32 reg;
  154. reg = 0;
  155. snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
  156. TSCM_ADDR_BASE + TSCM_OFFSET_START_STREAMING,
  157. &reg, sizeof(reg), 0);
  158. reg = 0;
  159. snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
  160. TSCM_ADDR_BASE + TSCM_OFFSET_ISOC_RX_ON,
  161. &reg, sizeof(reg), 0);
  162. }
  163. static int begin_session(struct snd_tscm *tscm)
  164. {
  165. __be32 reg;
  166. int err;
  167. reg = cpu_to_be32(0x00000001);
  168. err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
  169. TSCM_ADDR_BASE + TSCM_OFFSET_START_STREAMING,
  170. &reg, sizeof(reg), 0);
  171. if (err < 0)
  172. return err;
  173. reg = cpu_to_be32(0x00000001);
  174. err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
  175. TSCM_ADDR_BASE + TSCM_OFFSET_ISOC_RX_ON,
  176. &reg, sizeof(reg), 0);
  177. if (err < 0)
  178. return err;
  179. /* Set an option for unknown purpose. */
  180. reg = cpu_to_be32(0x00002000);
  181. err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
  182. TSCM_ADDR_BASE + TSCM_OFFSET_SET_OPTION,
  183. &reg, sizeof(reg), 0);
  184. if (err < 0)
  185. return err;
  186. /* Start multiplexing PCM samples on packets. */
  187. reg = cpu_to_be32(0x00000001);
  188. return snd_fw_transaction(tscm->unit,
  189. TCODE_WRITE_QUADLET_REQUEST,
  190. TSCM_ADDR_BASE + TSCM_OFFSET_ISOC_TX_ON,
  191. &reg, sizeof(reg), 0);
  192. }
  193. static void release_resources(struct snd_tscm *tscm)
  194. {
  195. __be32 reg;
  196. /* Unregister channels. */
  197. reg = cpu_to_be32(0x00000000);
  198. snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
  199. TSCM_ADDR_BASE + TSCM_OFFSET_ISOC_TX_CH,
  200. &reg, sizeof(reg), 0);
  201. reg = cpu_to_be32(0x00000000);
  202. snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
  203. TSCM_ADDR_BASE + TSCM_OFFSET_UNKNOWN,
  204. &reg, sizeof(reg), 0);
  205. reg = cpu_to_be32(0x00000000);
  206. snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
  207. TSCM_ADDR_BASE + TSCM_OFFSET_ISOC_RX_CH,
  208. &reg, sizeof(reg), 0);
  209. /* Release isochronous resources. */
  210. fw_iso_resources_free(&tscm->tx_resources);
  211. fw_iso_resources_free(&tscm->rx_resources);
  212. }
  213. static int keep_resources(struct snd_tscm *tscm, unsigned int rate)
  214. {
  215. __be32 reg;
  216. int err;
  217. /* Keep resources for in-stream. */
  218. err = amdtp_tscm_set_parameters(&tscm->tx_stream, rate);
  219. if (err < 0)
  220. return err;
  221. err = fw_iso_resources_allocate(&tscm->tx_resources,
  222. amdtp_stream_get_max_payload(&tscm->tx_stream),
  223. fw_parent_device(tscm->unit)->max_speed);
  224. if (err < 0)
  225. goto error;
  226. /* Keep resources for out-stream. */
  227. err = amdtp_tscm_set_parameters(&tscm->rx_stream, rate);
  228. if (err < 0)
  229. return err;
  230. err = fw_iso_resources_allocate(&tscm->rx_resources,
  231. amdtp_stream_get_max_payload(&tscm->rx_stream),
  232. fw_parent_device(tscm->unit)->max_speed);
  233. if (err < 0)
  234. return err;
  235. /* Register the isochronous channel for transmitting stream. */
  236. reg = cpu_to_be32(tscm->tx_resources.channel);
  237. err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
  238. TSCM_ADDR_BASE + TSCM_OFFSET_ISOC_TX_CH,
  239. &reg, sizeof(reg), 0);
  240. if (err < 0)
  241. goto error;
  242. /* Unknown */
  243. reg = cpu_to_be32(0x00000002);
  244. err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
  245. TSCM_ADDR_BASE + TSCM_OFFSET_UNKNOWN,
  246. &reg, sizeof(reg), 0);
  247. if (err < 0)
  248. goto error;
  249. /* Register the isochronous channel for receiving stream. */
  250. reg = cpu_to_be32(tscm->rx_resources.channel);
  251. err = snd_fw_transaction(tscm->unit, TCODE_WRITE_QUADLET_REQUEST,
  252. TSCM_ADDR_BASE + TSCM_OFFSET_ISOC_RX_CH,
  253. &reg, sizeof(reg), 0);
  254. if (err < 0)
  255. goto error;
  256. return 0;
  257. error:
  258. release_resources(tscm);
  259. return err;
  260. }
  261. int snd_tscm_stream_init_duplex(struct snd_tscm *tscm)
  262. {
  263. unsigned int pcm_channels;
  264. int err;
  265. /* For out-stream. */
  266. err = fw_iso_resources_init(&tscm->rx_resources, tscm->unit);
  267. if (err < 0)
  268. return err;
  269. pcm_channels = tscm->spec->pcm_playback_analog_channels;
  270. if (tscm->spec->has_adat)
  271. pcm_channels += 8;
  272. if (tscm->spec->has_spdif)
  273. pcm_channels += 2;
  274. err = amdtp_tscm_init(&tscm->rx_stream, tscm->unit, AMDTP_OUT_STREAM,
  275. pcm_channels);
  276. if (err < 0)
  277. return err;
  278. /* For in-stream. */
  279. err = fw_iso_resources_init(&tscm->tx_resources, tscm->unit);
  280. if (err < 0)
  281. return err;
  282. pcm_channels = tscm->spec->pcm_capture_analog_channels;
  283. if (tscm->spec->has_adat)
  284. pcm_channels += 8;
  285. if (tscm->spec->has_spdif)
  286. pcm_channels += 2;
  287. err = amdtp_tscm_init(&tscm->tx_stream, tscm->unit, AMDTP_IN_STREAM,
  288. pcm_channels);
  289. if (err < 0)
  290. amdtp_stream_destroy(&tscm->rx_stream);
  291. return err;
  292. }
  293. /* At bus reset, streaming is stopped and some registers are clear. */
  294. void snd_tscm_stream_update_duplex(struct snd_tscm *tscm)
  295. {
  296. amdtp_stream_pcm_abort(&tscm->tx_stream);
  297. amdtp_stream_stop(&tscm->tx_stream);
  298. amdtp_stream_pcm_abort(&tscm->rx_stream);
  299. amdtp_stream_stop(&tscm->rx_stream);
  300. }
  301. /*
  302. * This function should be called before starting streams or after stopping
  303. * streams.
  304. */
  305. void snd_tscm_stream_destroy_duplex(struct snd_tscm *tscm)
  306. {
  307. amdtp_stream_destroy(&tscm->rx_stream);
  308. amdtp_stream_destroy(&tscm->tx_stream);
  309. fw_iso_resources_destroy(&tscm->rx_resources);
  310. fw_iso_resources_destroy(&tscm->tx_resources);
  311. }
  312. int snd_tscm_stream_start_duplex(struct snd_tscm *tscm, unsigned int rate)
  313. {
  314. unsigned int curr_rate;
  315. int err;
  316. if (tscm->substreams_counter == 0)
  317. return 0;
  318. err = snd_tscm_stream_get_rate(tscm, &curr_rate);
  319. if (err < 0)
  320. return err;
  321. if (curr_rate != rate ||
  322. amdtp_streaming_error(&tscm->tx_stream) ||
  323. amdtp_streaming_error(&tscm->rx_stream)) {
  324. finish_session(tscm);
  325. amdtp_stream_stop(&tscm->tx_stream);
  326. amdtp_stream_stop(&tscm->rx_stream);
  327. release_resources(tscm);
  328. }
  329. if (!amdtp_stream_running(&tscm->tx_stream)) {
  330. amdtp_stream_set_sync(CIP_SYNC_TO_DEVICE,
  331. &tscm->tx_stream, &tscm->rx_stream);
  332. err = keep_resources(tscm, rate);
  333. if (err < 0)
  334. goto error;
  335. err = set_stream_formats(tscm, rate);
  336. if (err < 0)
  337. goto error;
  338. err = begin_session(tscm);
  339. if (err < 0)
  340. goto error;
  341. err = amdtp_stream_start(&tscm->tx_stream,
  342. tscm->tx_resources.channel,
  343. fw_parent_device(tscm->unit)->max_speed);
  344. if (err < 0)
  345. goto error;
  346. if (!amdtp_stream_wait_callback(&tscm->tx_stream,
  347. CALLBACK_TIMEOUT)) {
  348. err = -ETIMEDOUT;
  349. goto error;
  350. }
  351. }
  352. if (!amdtp_stream_running(&tscm->rx_stream)) {
  353. err = amdtp_stream_start(&tscm->rx_stream,
  354. tscm->rx_resources.channel,
  355. fw_parent_device(tscm->unit)->max_speed);
  356. if (err < 0)
  357. goto error;
  358. if (!amdtp_stream_wait_callback(&tscm->rx_stream,
  359. CALLBACK_TIMEOUT)) {
  360. err = -ETIMEDOUT;
  361. goto error;
  362. }
  363. }
  364. return 0;
  365. error:
  366. amdtp_stream_stop(&tscm->tx_stream);
  367. amdtp_stream_stop(&tscm->rx_stream);
  368. finish_session(tscm);
  369. release_resources(tscm);
  370. return err;
  371. }
  372. void snd_tscm_stream_stop_duplex(struct snd_tscm *tscm)
  373. {
  374. if (tscm->substreams_counter > 0)
  375. return;
  376. amdtp_stream_stop(&tscm->tx_stream);
  377. amdtp_stream_stop(&tscm->rx_stream);
  378. finish_session(tscm);
  379. release_resources(tscm);
  380. }
  381. void snd_tscm_stream_lock_changed(struct snd_tscm *tscm)
  382. {
  383. tscm->dev_lock_changed = true;
  384. wake_up(&tscm->hwdep_wait);
  385. }
  386. int snd_tscm_stream_lock_try(struct snd_tscm *tscm)
  387. {
  388. int err;
  389. spin_lock_irq(&tscm->lock);
  390. /* user land lock this */
  391. if (tscm->dev_lock_count < 0) {
  392. err = -EBUSY;
  393. goto end;
  394. }
  395. /* this is the first time */
  396. if (tscm->dev_lock_count++ == 0)
  397. snd_tscm_stream_lock_changed(tscm);
  398. err = 0;
  399. end:
  400. spin_unlock_irq(&tscm->lock);
  401. return err;
  402. }
  403. void snd_tscm_stream_lock_release(struct snd_tscm *tscm)
  404. {
  405. spin_lock_irq(&tscm->lock);
  406. if (WARN_ON(tscm->dev_lock_count <= 0))
  407. goto end;
  408. if (--tscm->dev_lock_count == 0)
  409. snd_tscm_stream_lock_changed(tscm);
  410. end:
  411. spin_unlock_irq(&tscm->lock);
  412. }