dsp_spos_scb_lib.c 48 KB

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  1. /*
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License as published by
  5. * the Free Software Foundation; either version 2 of the License, or
  6. * (at your option) any later version.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. *
  13. * You should have received a copy of the GNU General Public License
  14. * along with this program; if not, write to the Free Software
  15. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  16. *
  17. */
  18. /*
  19. * 2002-07 Benny Sjostrand benny@hostmobility.com
  20. */
  21. #include <linux/io.h>
  22. #include <linux/delay.h>
  23. #include <linux/pm.h>
  24. #include <linux/init.h>
  25. #include <linux/slab.h>
  26. #include <linux/mutex.h>
  27. #include <sound/core.h>
  28. #include <sound/control.h>
  29. #include <sound/info.h>
  30. #include "cs46xx.h"
  31. #include "cs46xx_lib.h"
  32. #include "dsp_spos.h"
  33. struct proc_scb_info {
  34. struct dsp_scb_descriptor * scb_desc;
  35. struct snd_cs46xx *chip;
  36. };
  37. static void remove_symbol (struct snd_cs46xx * chip, struct dsp_symbol_entry * symbol)
  38. {
  39. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  40. int symbol_index = (int)(symbol - ins->symbol_table.symbols);
  41. if (snd_BUG_ON(ins->symbol_table.nsymbols <= 0))
  42. return;
  43. if (snd_BUG_ON(symbol_index < 0 ||
  44. symbol_index >= ins->symbol_table.nsymbols))
  45. return;
  46. ins->symbol_table.symbols[symbol_index].deleted = 1;
  47. if (symbol_index < ins->symbol_table.highest_frag_index) {
  48. ins->symbol_table.highest_frag_index = symbol_index;
  49. }
  50. if (symbol_index == ins->symbol_table.nsymbols - 1)
  51. ins->symbol_table.nsymbols --;
  52. if (ins->symbol_table.highest_frag_index > ins->symbol_table.nsymbols) {
  53. ins->symbol_table.highest_frag_index = ins->symbol_table.nsymbols;
  54. }
  55. }
  56. #ifdef CONFIG_SND_PROC_FS
  57. static void cs46xx_dsp_proc_scb_info_read (struct snd_info_entry *entry,
  58. struct snd_info_buffer *buffer)
  59. {
  60. struct proc_scb_info * scb_info = entry->private_data;
  61. struct dsp_scb_descriptor * scb = scb_info->scb_desc;
  62. struct dsp_spos_instance * ins;
  63. struct snd_cs46xx *chip = scb_info->chip;
  64. int j,col;
  65. void __iomem *dst = chip->region.idx[1].remap_addr + DSP_PARAMETER_BYTE_OFFSET;
  66. ins = chip->dsp_spos_instance;
  67. mutex_lock(&chip->spos_mutex);
  68. snd_iprintf(buffer,"%04x %s:\n",scb->address,scb->scb_name);
  69. for (col = 0,j = 0;j < 0x10; j++,col++) {
  70. if (col == 4) {
  71. snd_iprintf(buffer,"\n");
  72. col = 0;
  73. }
  74. snd_iprintf(buffer,"%08x ",readl(dst + (scb->address + j) * sizeof(u32)));
  75. }
  76. snd_iprintf(buffer,"\n");
  77. if (scb->parent_scb_ptr != NULL) {
  78. snd_iprintf(buffer,"parent [%s:%04x] ",
  79. scb->parent_scb_ptr->scb_name,
  80. scb->parent_scb_ptr->address);
  81. } else snd_iprintf(buffer,"parent [none] ");
  82. snd_iprintf(buffer,"sub_list_ptr [%s:%04x]\nnext_scb_ptr [%s:%04x] task_entry [%s:%04x]\n",
  83. scb->sub_list_ptr->scb_name,
  84. scb->sub_list_ptr->address,
  85. scb->next_scb_ptr->scb_name,
  86. scb->next_scb_ptr->address,
  87. scb->task_entry->symbol_name,
  88. scb->task_entry->address);
  89. snd_iprintf(buffer,"index [%d] ref_count [%d]\n",scb->index,scb->ref_count);
  90. mutex_unlock(&chip->spos_mutex);
  91. }
  92. #endif
  93. static void _dsp_unlink_scb (struct snd_cs46xx *chip, struct dsp_scb_descriptor * scb)
  94. {
  95. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  96. if ( scb->parent_scb_ptr ) {
  97. /* unlink parent SCB */
  98. if (snd_BUG_ON(scb->parent_scb_ptr->sub_list_ptr != scb &&
  99. scb->parent_scb_ptr->next_scb_ptr != scb))
  100. return;
  101. if (scb->parent_scb_ptr->sub_list_ptr == scb) {
  102. if (scb->next_scb_ptr == ins->the_null_scb) {
  103. /* last and only node in parent sublist */
  104. scb->parent_scb_ptr->sub_list_ptr = scb->sub_list_ptr;
  105. if (scb->sub_list_ptr != ins->the_null_scb) {
  106. scb->sub_list_ptr->parent_scb_ptr = scb->parent_scb_ptr;
  107. }
  108. scb->sub_list_ptr = ins->the_null_scb;
  109. } else {
  110. /* first node in parent sublist */
  111. scb->parent_scb_ptr->sub_list_ptr = scb->next_scb_ptr;
  112. if (scb->next_scb_ptr != ins->the_null_scb) {
  113. /* update next node parent ptr. */
  114. scb->next_scb_ptr->parent_scb_ptr = scb->parent_scb_ptr;
  115. }
  116. scb->next_scb_ptr = ins->the_null_scb;
  117. }
  118. } else {
  119. scb->parent_scb_ptr->next_scb_ptr = scb->next_scb_ptr;
  120. if (scb->next_scb_ptr != ins->the_null_scb) {
  121. /* update next node parent ptr. */
  122. scb->next_scb_ptr->parent_scb_ptr = scb->parent_scb_ptr;
  123. }
  124. scb->next_scb_ptr = ins->the_null_scb;
  125. }
  126. /* update parent first entry in DSP RAM */
  127. cs46xx_dsp_spos_update_scb(chip,scb->parent_scb_ptr);
  128. /* then update entry in DSP RAM */
  129. cs46xx_dsp_spos_update_scb(chip,scb);
  130. scb->parent_scb_ptr = NULL;
  131. }
  132. }
  133. static void _dsp_clear_sample_buffer (struct snd_cs46xx *chip, u32 sample_buffer_addr,
  134. int dword_count)
  135. {
  136. void __iomem *dst = chip->region.idx[2].remap_addr + sample_buffer_addr;
  137. int i;
  138. for (i = 0; i < dword_count ; ++i ) {
  139. writel(0, dst);
  140. dst += 4;
  141. }
  142. }
  143. void cs46xx_dsp_remove_scb (struct snd_cs46xx *chip, struct dsp_scb_descriptor * scb)
  144. {
  145. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  146. unsigned long flags;
  147. /* check integrety */
  148. if (snd_BUG_ON(scb->index < 0 ||
  149. scb->index >= ins->nscb ||
  150. (ins->scbs + scb->index) != scb))
  151. return;
  152. #if 0
  153. /* can't remove a SCB with childs before
  154. removing childs first */
  155. if (snd_BUG_ON(scb->sub_list_ptr != ins->the_null_scb ||
  156. scb->next_scb_ptr != ins->the_null_scb))
  157. goto _end;
  158. #endif
  159. spin_lock_irqsave(&chip->reg_lock, flags);
  160. _dsp_unlink_scb (chip,scb);
  161. spin_unlock_irqrestore(&chip->reg_lock, flags);
  162. cs46xx_dsp_proc_free_scb_desc(scb);
  163. if (snd_BUG_ON(!scb->scb_symbol))
  164. return;
  165. remove_symbol (chip,scb->scb_symbol);
  166. ins->scbs[scb->index].deleted = 1;
  167. #ifdef CONFIG_PM_SLEEP
  168. kfree(ins->scbs[scb->index].data);
  169. ins->scbs[scb->index].data = NULL;
  170. #endif
  171. if (scb->index < ins->scb_highest_frag_index)
  172. ins->scb_highest_frag_index = scb->index;
  173. if (scb->index == ins->nscb - 1) {
  174. ins->nscb --;
  175. }
  176. if (ins->scb_highest_frag_index > ins->nscb) {
  177. ins->scb_highest_frag_index = ins->nscb;
  178. }
  179. #if 0
  180. /* !!!! THIS IS A PIECE OF SHIT MADE BY ME !!! */
  181. for(i = scb->index + 1;i < ins->nscb; ++i) {
  182. ins->scbs[i - 1].index = i - 1;
  183. }
  184. #endif
  185. }
  186. #ifdef CONFIG_SND_PROC_FS
  187. void cs46xx_dsp_proc_free_scb_desc (struct dsp_scb_descriptor * scb)
  188. {
  189. if (scb->proc_info) {
  190. struct proc_scb_info * scb_info = scb->proc_info->private_data;
  191. struct snd_cs46xx *chip = scb_info->chip;
  192. dev_dbg(chip->card->dev,
  193. "cs46xx_dsp_proc_free_scb_desc: freeing %s\n",
  194. scb->scb_name);
  195. snd_info_free_entry(scb->proc_info);
  196. scb->proc_info = NULL;
  197. kfree (scb_info);
  198. }
  199. }
  200. void cs46xx_dsp_proc_register_scb_desc (struct snd_cs46xx *chip,
  201. struct dsp_scb_descriptor * scb)
  202. {
  203. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  204. struct snd_info_entry * entry;
  205. struct proc_scb_info * scb_info;
  206. /* register to proc */
  207. if (ins->snd_card != NULL && ins->proc_dsp_dir != NULL &&
  208. scb->proc_info == NULL) {
  209. if ((entry = snd_info_create_card_entry(ins->snd_card, scb->scb_name,
  210. ins->proc_dsp_dir)) != NULL) {
  211. scb_info = kmalloc(sizeof(struct proc_scb_info), GFP_KERNEL);
  212. if (!scb_info) {
  213. snd_info_free_entry(entry);
  214. entry = NULL;
  215. goto out;
  216. }
  217. scb_info->chip = chip;
  218. scb_info->scb_desc = scb;
  219. entry->content = SNDRV_INFO_CONTENT_TEXT;
  220. entry->private_data = scb_info;
  221. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  222. entry->c.text.read = cs46xx_dsp_proc_scb_info_read;
  223. if (snd_info_register(entry) < 0) {
  224. snd_info_free_entry(entry);
  225. kfree (scb_info);
  226. entry = NULL;
  227. }
  228. }
  229. out:
  230. scb->proc_info = entry;
  231. }
  232. }
  233. #endif /* CONFIG_SND_PROC_FS */
  234. static struct dsp_scb_descriptor *
  235. _dsp_create_generic_scb (struct snd_cs46xx *chip, char * name, u32 * scb_data, u32 dest,
  236. struct dsp_symbol_entry * task_entry,
  237. struct dsp_scb_descriptor * parent_scb,
  238. int scb_child_type)
  239. {
  240. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  241. struct dsp_scb_descriptor * scb;
  242. unsigned long flags;
  243. if (snd_BUG_ON(!ins->the_null_scb))
  244. return NULL;
  245. /* fill the data that will be wroten to DSP */
  246. scb_data[SCBsubListPtr] =
  247. (ins->the_null_scb->address << 0x10) | ins->the_null_scb->address;
  248. scb_data[SCBfuncEntryPtr] &= 0xFFFF0000;
  249. scb_data[SCBfuncEntryPtr] |= task_entry->address;
  250. dev_dbg(chip->card->dev, "dsp_spos: creating SCB <%s>\n", name);
  251. scb = cs46xx_dsp_create_scb(chip,name,scb_data,dest);
  252. scb->sub_list_ptr = ins->the_null_scb;
  253. scb->next_scb_ptr = ins->the_null_scb;
  254. scb->parent_scb_ptr = parent_scb;
  255. scb->task_entry = task_entry;
  256. /* update parent SCB */
  257. if (scb->parent_scb_ptr) {
  258. #if 0
  259. dev_dbg(chip->card->dev,
  260. "scb->parent_scb_ptr = %s\n",
  261. scb->parent_scb_ptr->scb_name);
  262. dev_dbg(chip->card->dev,
  263. "scb->parent_scb_ptr->next_scb_ptr = %s\n",
  264. scb->parent_scb_ptr->next_scb_ptr->scb_name);
  265. dev_dbg(chip->card->dev,
  266. "scb->parent_scb_ptr->sub_list_ptr = %s\n",
  267. scb->parent_scb_ptr->sub_list_ptr->scb_name);
  268. #endif
  269. /* link to parent SCB */
  270. if (scb_child_type == SCB_ON_PARENT_NEXT_SCB) {
  271. if (snd_BUG_ON(scb->parent_scb_ptr->next_scb_ptr !=
  272. ins->the_null_scb))
  273. return NULL;
  274. scb->parent_scb_ptr->next_scb_ptr = scb;
  275. } else if (scb_child_type == SCB_ON_PARENT_SUBLIST_SCB) {
  276. if (snd_BUG_ON(scb->parent_scb_ptr->sub_list_ptr !=
  277. ins->the_null_scb))
  278. return NULL;
  279. scb->parent_scb_ptr->sub_list_ptr = scb;
  280. } else {
  281. snd_BUG();
  282. }
  283. spin_lock_irqsave(&chip->reg_lock, flags);
  284. /* update entry in DSP RAM */
  285. cs46xx_dsp_spos_update_scb(chip,scb->parent_scb_ptr);
  286. spin_unlock_irqrestore(&chip->reg_lock, flags);
  287. }
  288. cs46xx_dsp_proc_register_scb_desc (chip,scb);
  289. return scb;
  290. }
  291. static struct dsp_scb_descriptor *
  292. cs46xx_dsp_create_generic_scb (struct snd_cs46xx *chip, char * name, u32 * scb_data,
  293. u32 dest, char * task_entry_name,
  294. struct dsp_scb_descriptor * parent_scb,
  295. int scb_child_type)
  296. {
  297. struct dsp_symbol_entry * task_entry;
  298. task_entry = cs46xx_dsp_lookup_symbol (chip,task_entry_name,
  299. SYMBOL_CODE);
  300. if (task_entry == NULL) {
  301. dev_err(chip->card->dev,
  302. "dsp_spos: symbol %s not found\n", task_entry_name);
  303. return NULL;
  304. }
  305. return _dsp_create_generic_scb (chip,name,scb_data,dest,task_entry,
  306. parent_scb,scb_child_type);
  307. }
  308. struct dsp_scb_descriptor *
  309. cs46xx_dsp_create_timing_master_scb (struct snd_cs46xx *chip)
  310. {
  311. struct dsp_scb_descriptor * scb;
  312. struct dsp_timing_master_scb timing_master_scb = {
  313. { 0,
  314. 0,
  315. 0,
  316. 0
  317. },
  318. { 0,
  319. 0,
  320. 0,
  321. 0,
  322. 0
  323. },
  324. 0,0,
  325. 0,NULL_SCB_ADDR,
  326. 0,0, /* extraSampleAccum:TMreserved */
  327. 0,0, /* codecFIFOptr:codecFIFOsyncd */
  328. 0x0001,0x8000, /* fracSampAccumQm1:TMfrmsLeftInGroup */
  329. 0x0001,0x0000, /* fracSampCorrectionQm1:TMfrmGroupLength */
  330. 0x00060000 /* nSampPerFrmQ15 */
  331. };
  332. scb = cs46xx_dsp_create_generic_scb(chip,"TimingMasterSCBInst",(u32 *)&timing_master_scb,
  333. TIMINGMASTER_SCB_ADDR,
  334. "TIMINGMASTER",NULL,SCB_NO_PARENT);
  335. return scb;
  336. }
  337. struct dsp_scb_descriptor *
  338. cs46xx_dsp_create_codec_out_scb(struct snd_cs46xx * chip, char * codec_name,
  339. u16 channel_disp, u16 fifo_addr, u16 child_scb_addr,
  340. u32 dest, struct dsp_scb_descriptor * parent_scb,
  341. int scb_child_type)
  342. {
  343. struct dsp_scb_descriptor * scb;
  344. struct dsp_codec_output_scb codec_out_scb = {
  345. { 0,
  346. 0,
  347. 0,
  348. 0
  349. },
  350. {
  351. 0,
  352. 0,
  353. 0,
  354. 0,
  355. 0
  356. },
  357. 0,0,
  358. 0,NULL_SCB_ADDR,
  359. 0, /* COstrmRsConfig */
  360. 0, /* COstrmBufPtr */
  361. channel_disp,fifo_addr, /* leftChanBaseIOaddr:rightChanIOdisp */
  362. 0x0000,0x0080, /* (!AC97!) COexpVolChangeRate:COscaleShiftCount */
  363. 0,child_scb_addr /* COreserved - need child scb to work with rom code */
  364. };
  365. scb = cs46xx_dsp_create_generic_scb(chip,codec_name,(u32 *)&codec_out_scb,
  366. dest,"S16_CODECOUTPUTTASK",parent_scb,
  367. scb_child_type);
  368. return scb;
  369. }
  370. struct dsp_scb_descriptor *
  371. cs46xx_dsp_create_codec_in_scb(struct snd_cs46xx * chip, char * codec_name,
  372. u16 channel_disp, u16 fifo_addr, u16 sample_buffer_addr,
  373. u32 dest, struct dsp_scb_descriptor * parent_scb,
  374. int scb_child_type)
  375. {
  376. struct dsp_scb_descriptor * scb;
  377. struct dsp_codec_input_scb codec_input_scb = {
  378. { 0,
  379. 0,
  380. 0,
  381. 0
  382. },
  383. {
  384. 0,
  385. 0,
  386. 0,
  387. 0,
  388. 0
  389. },
  390. #if 0 /* cs4620 */
  391. SyncIOSCB,NULL_SCB_ADDR
  392. #else
  393. 0 , 0,
  394. #endif
  395. 0,0,
  396. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_64, /* strmRsConfig */
  397. sample_buffer_addr << 0x10, /* strmBufPtr; defined as a dword ptr, used as a byte ptr */
  398. channel_disp,fifo_addr, /* (!AC97!) leftChanBaseINaddr=AC97primary
  399. link input slot 3 :rightChanINdisp=""slot 4 */
  400. 0x0000,0x0000, /* (!AC97!) ????:scaleShiftCount; no shift needed
  401. because AC97 is already 20 bits */
  402. 0x80008000 /* ??clw cwcgame.scb has 0 */
  403. };
  404. scb = cs46xx_dsp_create_generic_scb(chip,codec_name,(u32 *)&codec_input_scb,
  405. dest,"S16_CODECINPUTTASK",parent_scb,
  406. scb_child_type);
  407. return scb;
  408. }
  409. static struct dsp_scb_descriptor *
  410. cs46xx_dsp_create_pcm_reader_scb(struct snd_cs46xx * chip, char * scb_name,
  411. u16 sample_buffer_addr, u32 dest,
  412. int virtual_channel, u32 playback_hw_addr,
  413. struct dsp_scb_descriptor * parent_scb,
  414. int scb_child_type)
  415. {
  416. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  417. struct dsp_scb_descriptor * scb;
  418. struct dsp_generic_scb pcm_reader_scb = {
  419. /*
  420. Play DMA Task xfers data from host buffer to SP buffer
  421. init/runtime variables:
  422. PlayAC: Play Audio Data Conversion - SCB loc: 2nd dword, mask: 0x0000F000L
  423. DATA_FMT_16BIT_ST_LTLEND(0x00000000L) from 16-bit stereo, little-endian
  424. DATA_FMT_8_BIT_ST_SIGNED(0x00001000L) from 8-bit stereo, signed
  425. DATA_FMT_16BIT_MN_LTLEND(0x00002000L) from 16-bit mono, little-endian
  426. DATA_FMT_8_BIT_MN_SIGNED(0x00003000L) from 8-bit mono, signed
  427. DATA_FMT_16BIT_ST_BIGEND(0x00004000L) from 16-bit stereo, big-endian
  428. DATA_FMT_16BIT_MN_BIGEND(0x00006000L) from 16-bit mono, big-endian
  429. DATA_FMT_8_BIT_ST_UNSIGNED(0x00009000L) from 8-bit stereo, unsigned
  430. DATA_FMT_8_BIT_MN_UNSIGNED(0x0000b000L) from 8-bit mono, unsigned
  431. ? Other combinations possible from:
  432. DMA_RQ_C2_AUDIO_CONVERT_MASK 0x0000F000L
  433. DMA_RQ_C2_AC_NONE 0x00000000L
  434. DMA_RQ_C2_AC_8_TO_16_BIT 0x00001000L
  435. DMA_RQ_C2_AC_MONO_TO_STEREO 0x00002000L
  436. DMA_RQ_C2_AC_ENDIAN_CONVERT 0x00004000L
  437. DMA_RQ_C2_AC_SIGNED_CONVERT 0x00008000L
  438. HostBuffAddr: Host Buffer Physical Byte Address - SCB loc:3rd dword, Mask: 0xFFFFFFFFL
  439. aligned to dword boundary
  440. */
  441. /* Basic (non scatter/gather) DMA requestor (4 ints) */
  442. { DMA_RQ_C1_SOURCE_ON_HOST + /* source buffer is on the host */
  443. DMA_RQ_C1_SOURCE_MOD1024 + /* source buffer is 1024 dwords (4096 bytes) */
  444. DMA_RQ_C1_DEST_MOD32 + /* dest buffer(PCMreaderBuf) is 32 dwords*/
  445. DMA_RQ_C1_WRITEBACK_SRC_FLAG + /* ?? */
  446. DMA_RQ_C1_WRITEBACK_DEST_FLAG + /* ?? */
  447. 15, /* DwordCount-1: picked 16 for DwordCount because Jim */
  448. /* Barnette said that is what we should use since */
  449. /* we are not running in optimized mode? */
  450. DMA_RQ_C2_AC_NONE +
  451. DMA_RQ_C2_SIGNAL_SOURCE_PINGPONG + /* set play interrupt (bit0) in HISR when source */
  452. /* buffer (on host) crosses half-way point */
  453. virtual_channel, /* Play DMA channel arbitrarily set to 0 */
  454. playback_hw_addr, /* HostBuffAddr (source) */
  455. DMA_RQ_SD_SP_SAMPLE_ADDR + /* destination buffer is in SP Sample Memory */
  456. sample_buffer_addr /* SP Buffer Address (destination) */
  457. },
  458. /* Scatter/gather DMA requestor extension (5 ints) */
  459. {
  460. 0,
  461. 0,
  462. 0,
  463. 0,
  464. 0
  465. },
  466. /* Sublist pointer & next stream control block (SCB) link. */
  467. NULL_SCB_ADDR,NULL_SCB_ADDR,
  468. /* Pointer to this tasks parameter block & stream function pointer */
  469. 0,NULL_SCB_ADDR,
  470. /* rsConfig register for stream buffer (rsDMA reg. is loaded from basicReq.daw */
  471. /* for incoming streams, or basicReq.saw, for outgoing streams) */
  472. RSCONFIG_DMA_ENABLE + /* enable DMA */
  473. (19 << RSCONFIG_MAX_DMA_SIZE_SHIFT) + /* MAX_DMA_SIZE picked to be 19 since SPUD */
  474. /* uses it for some reason */
  475. ((dest >> 4) << RSCONFIG_STREAM_NUM_SHIFT) + /* stream number = SCBaddr/16 */
  476. RSCONFIG_SAMPLE_16STEREO +
  477. RSCONFIG_MODULO_32, /* dest buffer(PCMreaderBuf) is 32 dwords (256 bytes) */
  478. /* Stream sample pointer & MAC-unit mode for this stream */
  479. (sample_buffer_addr << 0x10),
  480. /* Fractional increment per output sample in the input sample buffer */
  481. 0,
  482. {
  483. /* Standard stereo volume control
  484. default muted */
  485. 0xffff,0xffff,
  486. 0xffff,0xffff
  487. }
  488. };
  489. if (ins->null_algorithm == NULL) {
  490. ins->null_algorithm = cs46xx_dsp_lookup_symbol (chip,"NULLALGORITHM",
  491. SYMBOL_CODE);
  492. if (ins->null_algorithm == NULL) {
  493. dev_err(chip->card->dev,
  494. "dsp_spos: symbol NULLALGORITHM not found\n");
  495. return NULL;
  496. }
  497. }
  498. scb = _dsp_create_generic_scb(chip,scb_name,(u32 *)&pcm_reader_scb,
  499. dest,ins->null_algorithm,parent_scb,
  500. scb_child_type);
  501. return scb;
  502. }
  503. #define GOF_PER_SEC 200
  504. struct dsp_scb_descriptor *
  505. cs46xx_dsp_create_src_task_scb(struct snd_cs46xx * chip, char * scb_name,
  506. int rate,
  507. u16 src_buffer_addr,
  508. u16 src_delay_buffer_addr, u32 dest,
  509. struct dsp_scb_descriptor * parent_scb,
  510. int scb_child_type,
  511. int pass_through)
  512. {
  513. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  514. struct dsp_scb_descriptor * scb;
  515. unsigned int tmp1, tmp2;
  516. unsigned int phiIncr;
  517. unsigned int correctionPerGOF, correctionPerSec;
  518. dev_dbg(chip->card->dev, "dsp_spos: setting %s rate to %u\n",
  519. scb_name, rate);
  520. /*
  521. * Compute the values used to drive the actual sample rate conversion.
  522. * The following formulas are being computed, using inline assembly
  523. * since we need to use 64 bit arithmetic to compute the values:
  524. *
  525. * phiIncr = floor((Fs,in * 2^26) / Fs,out)
  526. * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
  527. * GOF_PER_SEC)
  528. * ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M
  529. * GOF_PER_SEC * correctionPerGOF
  530. *
  531. * i.e.
  532. *
  533. * phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out)
  534. * correctionPerGOF:correctionPerSec =
  535. * dividend:remainder(ulOther / GOF_PER_SEC)
  536. */
  537. tmp1 = rate << 16;
  538. phiIncr = tmp1 / 48000;
  539. tmp1 -= phiIncr * 48000;
  540. tmp1 <<= 10;
  541. phiIncr <<= 10;
  542. tmp2 = tmp1 / 48000;
  543. phiIncr += tmp2;
  544. tmp1 -= tmp2 * 48000;
  545. correctionPerGOF = tmp1 / GOF_PER_SEC;
  546. tmp1 -= correctionPerGOF * GOF_PER_SEC;
  547. correctionPerSec = tmp1;
  548. {
  549. struct dsp_src_task_scb src_task_scb = {
  550. 0x0028,0x00c8,
  551. 0x5555,0x0000,
  552. 0x0000,0x0000,
  553. src_buffer_addr,1,
  554. correctionPerGOF,correctionPerSec,
  555. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_32,
  556. 0x0000,src_delay_buffer_addr,
  557. 0x0,
  558. 0x080,(src_delay_buffer_addr + (24 * 4)),
  559. 0,0, /* next_scb, sub_list_ptr */
  560. 0,0, /* entry, this_spb */
  561. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_8,
  562. src_buffer_addr << 0x10,
  563. phiIncr,
  564. {
  565. 0xffff - ins->dac_volume_right,0xffff - ins->dac_volume_left,
  566. 0xffff - ins->dac_volume_right,0xffff - ins->dac_volume_left
  567. }
  568. };
  569. if (ins->s16_up == NULL) {
  570. ins->s16_up = cs46xx_dsp_lookup_symbol (chip,"S16_UPSRC",
  571. SYMBOL_CODE);
  572. if (ins->s16_up == NULL) {
  573. dev_err(chip->card->dev,
  574. "dsp_spos: symbol S16_UPSRC not found\n");
  575. return NULL;
  576. }
  577. }
  578. /* clear buffers */
  579. _dsp_clear_sample_buffer (chip,src_buffer_addr,8);
  580. _dsp_clear_sample_buffer (chip,src_delay_buffer_addr,32);
  581. if (pass_through) {
  582. /* wont work with any other rate than
  583. the native DSP rate */
  584. snd_BUG_ON(rate != 48000);
  585. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&src_task_scb,
  586. dest,"DMAREADER",parent_scb,
  587. scb_child_type);
  588. } else {
  589. scb = _dsp_create_generic_scb(chip,scb_name,(u32 *)&src_task_scb,
  590. dest,ins->s16_up,parent_scb,
  591. scb_child_type);
  592. }
  593. }
  594. return scb;
  595. }
  596. #if 0 /* not used */
  597. struct dsp_scb_descriptor *
  598. cs46xx_dsp_create_filter_scb(struct snd_cs46xx * chip, char * scb_name,
  599. u16 buffer_addr, u32 dest,
  600. struct dsp_scb_descriptor * parent_scb,
  601. int scb_child_type) {
  602. struct dsp_scb_descriptor * scb;
  603. struct dsp_filter_scb filter_scb = {
  604. .a0_right = 0x41a9,
  605. .a0_left = 0x41a9,
  606. .a1_right = 0xb8e4,
  607. .a1_left = 0xb8e4,
  608. .a2_right = 0x3e55,
  609. .a2_left = 0x3e55,
  610. .filter_unused3 = 0x0000,
  611. .filter_unused2 = 0x0000,
  612. .output_buf_ptr = buffer_addr,
  613. .init = 0x000,
  614. .prev_sample_output1 = 0x00000000,
  615. .prev_sample_output2 = 0x00000000,
  616. .prev_sample_input1 = 0x00000000,
  617. .prev_sample_input2 = 0x00000000,
  618. .next_scb_ptr = 0x0000,
  619. .sub_list_ptr = 0x0000,
  620. .entry_point = 0x0000,
  621. .spb_ptr = 0x0000,
  622. .b0_right = 0x0e38,
  623. .b0_left = 0x0e38,
  624. .b1_right = 0x1c71,
  625. .b1_left = 0x1c71,
  626. .b2_right = 0x0e38,
  627. .b2_left = 0x0e38,
  628. };
  629. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&filter_scb,
  630. dest,"FILTERTASK",parent_scb,
  631. scb_child_type);
  632. return scb;
  633. }
  634. #endif /* not used */
  635. struct dsp_scb_descriptor *
  636. cs46xx_dsp_create_mix_only_scb(struct snd_cs46xx * chip, char * scb_name,
  637. u16 mix_buffer_addr, u32 dest,
  638. struct dsp_scb_descriptor * parent_scb,
  639. int scb_child_type)
  640. {
  641. struct dsp_scb_descriptor * scb;
  642. struct dsp_mix_only_scb master_mix_scb = {
  643. /* 0 */ { 0,
  644. /* 1 */ 0,
  645. /* 2 */ mix_buffer_addr,
  646. /* 3 */ 0
  647. /* */ },
  648. {
  649. /* 4 */ 0,
  650. /* 5 */ 0,
  651. /* 6 */ 0,
  652. /* 7 */ 0,
  653. /* 8 */ 0x00000080
  654. },
  655. /* 9 */ 0,0,
  656. /* A */ 0,0,
  657. /* B */ RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_32,
  658. /* C */ (mix_buffer_addr + (16 * 4)) << 0x10,
  659. /* D */ 0,
  660. {
  661. /* E */ 0x8000,0x8000,
  662. /* F */ 0x8000,0x8000
  663. }
  664. };
  665. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&master_mix_scb,
  666. dest,"S16_MIX",parent_scb,
  667. scb_child_type);
  668. return scb;
  669. }
  670. struct dsp_scb_descriptor *
  671. cs46xx_dsp_create_mix_to_ostream_scb(struct snd_cs46xx * chip, char * scb_name,
  672. u16 mix_buffer_addr, u16 writeback_spb, u32 dest,
  673. struct dsp_scb_descriptor * parent_scb,
  674. int scb_child_type)
  675. {
  676. struct dsp_scb_descriptor * scb;
  677. struct dsp_mix2_ostream_scb mix2_ostream_scb = {
  678. /* Basic (non scatter/gather) DMA requestor (4 ints) */
  679. {
  680. DMA_RQ_C1_SOURCE_MOD64 +
  681. DMA_RQ_C1_DEST_ON_HOST +
  682. DMA_RQ_C1_DEST_MOD1024 +
  683. DMA_RQ_C1_WRITEBACK_SRC_FLAG +
  684. DMA_RQ_C1_WRITEBACK_DEST_FLAG +
  685. 15,
  686. DMA_RQ_C2_AC_NONE +
  687. DMA_RQ_C2_SIGNAL_DEST_PINGPONG +
  688. CS46XX_DSP_CAPTURE_CHANNEL,
  689. DMA_RQ_SD_SP_SAMPLE_ADDR +
  690. mix_buffer_addr,
  691. 0x0
  692. },
  693. { 0, 0, 0, 0, 0, },
  694. 0,0,
  695. 0,writeback_spb,
  696. RSCONFIG_DMA_ENABLE +
  697. (19 << RSCONFIG_MAX_DMA_SIZE_SHIFT) +
  698. ((dest >> 4) << RSCONFIG_STREAM_NUM_SHIFT) +
  699. RSCONFIG_DMA_TO_HOST +
  700. RSCONFIG_SAMPLE_16STEREO +
  701. RSCONFIG_MODULO_64,
  702. (mix_buffer_addr + (32 * 4)) << 0x10,
  703. 1,0,
  704. 0x0001,0x0080,
  705. 0xFFFF,0
  706. };
  707. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&mix2_ostream_scb,
  708. dest,"S16_MIX_TO_OSTREAM",parent_scb,
  709. scb_child_type);
  710. return scb;
  711. }
  712. struct dsp_scb_descriptor *
  713. cs46xx_dsp_create_vari_decimate_scb(struct snd_cs46xx * chip,char * scb_name,
  714. u16 vari_buffer_addr0,
  715. u16 vari_buffer_addr1,
  716. u32 dest,
  717. struct dsp_scb_descriptor * parent_scb,
  718. int scb_child_type)
  719. {
  720. struct dsp_scb_descriptor * scb;
  721. struct dsp_vari_decimate_scb vari_decimate_scb = {
  722. 0x0028,0x00c8,
  723. 0x5555,0x0000,
  724. 0x0000,0x0000,
  725. vari_buffer_addr0,vari_buffer_addr1,
  726. 0x0028,0x00c8,
  727. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_256,
  728. 0xFF800000,
  729. 0,
  730. 0x0080,vari_buffer_addr1 + (25 * 4),
  731. 0,0,
  732. 0,0,
  733. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_8,
  734. vari_buffer_addr0 << 0x10,
  735. 0x04000000,
  736. {
  737. 0x8000,0x8000,
  738. 0xFFFF,0xFFFF
  739. }
  740. };
  741. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&vari_decimate_scb,
  742. dest,"VARIDECIMATE",parent_scb,
  743. scb_child_type);
  744. return scb;
  745. }
  746. static struct dsp_scb_descriptor *
  747. cs46xx_dsp_create_pcm_serial_input_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
  748. struct dsp_scb_descriptor * input_scb,
  749. struct dsp_scb_descriptor * parent_scb,
  750. int scb_child_type)
  751. {
  752. struct dsp_scb_descriptor * scb;
  753. struct dsp_pcm_serial_input_scb pcm_serial_input_scb = {
  754. { 0,
  755. 0,
  756. 0,
  757. 0
  758. },
  759. {
  760. 0,
  761. 0,
  762. 0,
  763. 0,
  764. 0
  765. },
  766. 0,0,
  767. 0,0,
  768. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_16,
  769. 0,
  770. /* 0xD */ 0,input_scb->address,
  771. {
  772. /* 0xE */ 0x8000,0x8000,
  773. /* 0xF */ 0x8000,0x8000
  774. }
  775. };
  776. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&pcm_serial_input_scb,
  777. dest,"PCMSERIALINPUTTASK",parent_scb,
  778. scb_child_type);
  779. return scb;
  780. }
  781. static struct dsp_scb_descriptor *
  782. cs46xx_dsp_create_asynch_fg_tx_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
  783. u16 hfg_scb_address,
  784. u16 asynch_buffer_address,
  785. struct dsp_scb_descriptor * parent_scb,
  786. int scb_child_type)
  787. {
  788. struct dsp_scb_descriptor * scb;
  789. struct dsp_asynch_fg_tx_scb asynch_fg_tx_scb = {
  790. 0xfc00,0x03ff, /* Prototype sample buffer size of 256 dwords */
  791. 0x0058,0x0028, /* Min Delta 7 dwords == 28 bytes */
  792. /* : Max delta 25 dwords == 100 bytes */
  793. 0,hfg_scb_address, /* Point to HFG task SCB */
  794. 0,0, /* Initialize current Delta and Consumer ptr adjustment count */
  795. 0, /* Initialize accumulated Phi to 0 */
  796. 0,0x2aab, /* Const 1/3 */
  797. {
  798. 0, /* Define the unused elements */
  799. 0,
  800. 0
  801. },
  802. 0,0,
  803. 0,dest + AFGTxAccumPhi,
  804. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_256, /* Stereo, 256 dword */
  805. (asynch_buffer_address) << 0x10, /* This should be automagically synchronized
  806. to the producer pointer */
  807. /* There is no correct initial value, it will depend upon the detected
  808. rate etc */
  809. 0x18000000, /* Phi increment for approx 32k operation */
  810. 0x8000,0x8000, /* Volume controls are unused at this time */
  811. 0x8000,0x8000
  812. };
  813. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&asynch_fg_tx_scb,
  814. dest,"ASYNCHFGTXCODE",parent_scb,
  815. scb_child_type);
  816. return scb;
  817. }
  818. struct dsp_scb_descriptor *
  819. cs46xx_dsp_create_asynch_fg_rx_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
  820. u16 hfg_scb_address,
  821. u16 asynch_buffer_address,
  822. struct dsp_scb_descriptor * parent_scb,
  823. int scb_child_type)
  824. {
  825. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  826. struct dsp_scb_descriptor * scb;
  827. struct dsp_asynch_fg_rx_scb asynch_fg_rx_scb = {
  828. 0xfe00,0x01ff, /* Prototype sample buffer size of 128 dwords */
  829. 0x0064,0x001c, /* Min Delta 7 dwords == 28 bytes */
  830. /* : Max delta 25 dwords == 100 bytes */
  831. 0,hfg_scb_address, /* Point to HFG task SCB */
  832. 0,0, /* Initialize current Delta and Consumer ptr adjustment count */
  833. {
  834. 0, /* Define the unused elements */
  835. 0,
  836. 0,
  837. 0,
  838. 0
  839. },
  840. 0,0,
  841. 0,dest,
  842. RSCONFIG_MODULO_128 |
  843. RSCONFIG_SAMPLE_16STEREO, /* Stereo, 128 dword */
  844. ( (asynch_buffer_address + (16 * 4)) << 0x10), /* This should be automagically
  845. synchrinized to the producer pointer */
  846. /* There is no correct initial value, it will depend upon the detected
  847. rate etc */
  848. 0x18000000,
  849. /* Set IEC958 input volume */
  850. 0xffff - ins->spdif_input_volume_right,0xffff - ins->spdif_input_volume_left,
  851. 0xffff - ins->spdif_input_volume_right,0xffff - ins->spdif_input_volume_left,
  852. };
  853. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&asynch_fg_rx_scb,
  854. dest,"ASYNCHFGRXCODE",parent_scb,
  855. scb_child_type);
  856. return scb;
  857. }
  858. #if 0 /* not used */
  859. struct dsp_scb_descriptor *
  860. cs46xx_dsp_create_output_snoop_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
  861. u16 snoop_buffer_address,
  862. struct dsp_scb_descriptor * snoop_scb,
  863. struct dsp_scb_descriptor * parent_scb,
  864. int scb_child_type)
  865. {
  866. struct dsp_scb_descriptor * scb;
  867. struct dsp_output_snoop_scb output_snoop_scb = {
  868. { 0, /* not used. Zero */
  869. 0,
  870. 0,
  871. 0,
  872. },
  873. {
  874. 0, /* not used. Zero */
  875. 0,
  876. 0,
  877. 0,
  878. 0
  879. },
  880. 0,0,
  881. 0,0,
  882. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_64,
  883. snoop_buffer_address << 0x10,
  884. 0,0,
  885. 0,
  886. 0,snoop_scb->address
  887. };
  888. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&output_snoop_scb,
  889. dest,"OUTPUTSNOOP",parent_scb,
  890. scb_child_type);
  891. return scb;
  892. }
  893. #endif /* not used */
  894. struct dsp_scb_descriptor *
  895. cs46xx_dsp_create_spio_write_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
  896. struct dsp_scb_descriptor * parent_scb,
  897. int scb_child_type)
  898. {
  899. struct dsp_scb_descriptor * scb;
  900. struct dsp_spio_write_scb spio_write_scb = {
  901. 0,0, /* SPIOWAddress2:SPIOWAddress1; */
  902. 0, /* SPIOWData1; */
  903. 0, /* SPIOWData2; */
  904. 0,0, /* SPIOWAddress4:SPIOWAddress3; */
  905. 0, /* SPIOWData3; */
  906. 0, /* SPIOWData4; */
  907. 0,0, /* SPIOWDataPtr:Unused1; */
  908. { 0,0 }, /* Unused2[2]; */
  909. 0,0, /* SPIOWChildPtr:SPIOWSiblingPtr; */
  910. 0,0, /* SPIOWThisPtr:SPIOWEntryPoint; */
  911. {
  912. 0,
  913. 0,
  914. 0,
  915. 0,
  916. 0 /* Unused3[5]; */
  917. }
  918. };
  919. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&spio_write_scb,
  920. dest,"SPIOWRITE",parent_scb,
  921. scb_child_type);
  922. return scb;
  923. }
  924. struct dsp_scb_descriptor *
  925. cs46xx_dsp_create_magic_snoop_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
  926. u16 snoop_buffer_address,
  927. struct dsp_scb_descriptor * snoop_scb,
  928. struct dsp_scb_descriptor * parent_scb,
  929. int scb_child_type)
  930. {
  931. struct dsp_scb_descriptor * scb;
  932. struct dsp_magic_snoop_task magic_snoop_scb = {
  933. /* 0 */ 0, /* i0 */
  934. /* 1 */ 0, /* i1 */
  935. /* 2 */ snoop_buffer_address << 0x10,
  936. /* 3 */ 0,snoop_scb->address,
  937. /* 4 */ 0, /* i3 */
  938. /* 5 */ 0, /* i4 */
  939. /* 6 */ 0, /* i5 */
  940. /* 7 */ 0, /* i6 */
  941. /* 8 */ 0, /* i7 */
  942. /* 9 */ 0,0, /* next_scb, sub_list_ptr */
  943. /* A */ 0,0, /* entry_point, this_ptr */
  944. /* B */ RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_64,
  945. /* C */ snoop_buffer_address << 0x10,
  946. /* D */ 0,
  947. /* E */ { 0x8000,0x8000,
  948. /* F */ 0xffff,0xffff
  949. }
  950. };
  951. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&magic_snoop_scb,
  952. dest,"MAGICSNOOPTASK",parent_scb,
  953. scb_child_type);
  954. return scb;
  955. }
  956. static struct dsp_scb_descriptor *
  957. find_next_free_scb (struct snd_cs46xx * chip, struct dsp_scb_descriptor * from)
  958. {
  959. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  960. struct dsp_scb_descriptor * scb = from;
  961. while (scb->next_scb_ptr != ins->the_null_scb) {
  962. if (snd_BUG_ON(!scb->next_scb_ptr))
  963. return NULL;
  964. scb = scb->next_scb_ptr;
  965. }
  966. return scb;
  967. }
  968. static u32 pcm_reader_buffer_addr[DSP_MAX_PCM_CHANNELS] = {
  969. 0x0600, /* 1 */
  970. 0x1500, /* 2 */
  971. 0x1580, /* 3 */
  972. 0x1600, /* 4 */
  973. 0x1680, /* 5 */
  974. 0x1700, /* 6 */
  975. 0x1780, /* 7 */
  976. 0x1800, /* 8 */
  977. 0x1880, /* 9 */
  978. 0x1900, /* 10 */
  979. 0x1980, /* 11 */
  980. 0x1A00, /* 12 */
  981. 0x1A80, /* 13 */
  982. 0x1B00, /* 14 */
  983. 0x1B80, /* 15 */
  984. 0x1C00, /* 16 */
  985. 0x1C80, /* 17 */
  986. 0x1D00, /* 18 */
  987. 0x1D80, /* 19 */
  988. 0x1E00, /* 20 */
  989. 0x1E80, /* 21 */
  990. 0x1F00, /* 22 */
  991. 0x1F80, /* 23 */
  992. 0x2000, /* 24 */
  993. 0x2080, /* 25 */
  994. 0x2100, /* 26 */
  995. 0x2180, /* 27 */
  996. 0x2200, /* 28 */
  997. 0x2280, /* 29 */
  998. 0x2300, /* 30 */
  999. 0x2380, /* 31 */
  1000. 0x2400, /* 32 */
  1001. };
  1002. static u32 src_output_buffer_addr[DSP_MAX_SRC_NR] = {
  1003. 0x2B80,
  1004. 0x2BA0,
  1005. 0x2BC0,
  1006. 0x2BE0,
  1007. 0x2D00,
  1008. 0x2D20,
  1009. 0x2D40,
  1010. 0x2D60,
  1011. 0x2D80,
  1012. 0x2DA0,
  1013. 0x2DC0,
  1014. 0x2DE0,
  1015. 0x2E00,
  1016. 0x2E20
  1017. };
  1018. static u32 src_delay_buffer_addr[DSP_MAX_SRC_NR] = {
  1019. 0x2480,
  1020. 0x2500,
  1021. 0x2580,
  1022. 0x2600,
  1023. 0x2680,
  1024. 0x2700,
  1025. 0x2780,
  1026. 0x2800,
  1027. 0x2880,
  1028. 0x2900,
  1029. 0x2980,
  1030. 0x2A00,
  1031. 0x2A80,
  1032. 0x2B00
  1033. };
  1034. struct dsp_pcm_channel_descriptor *
  1035. cs46xx_dsp_create_pcm_channel (struct snd_cs46xx * chip,
  1036. u32 sample_rate, void * private_data,
  1037. u32 hw_dma_addr,
  1038. int pcm_channel_id)
  1039. {
  1040. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1041. struct dsp_scb_descriptor * src_scb = NULL, * pcm_scb, * mixer_scb = NULL;
  1042. struct dsp_scb_descriptor * src_parent_scb = NULL;
  1043. /* struct dsp_scb_descriptor * pcm_parent_scb; */
  1044. char scb_name[DSP_MAX_SCB_NAME];
  1045. int i, pcm_index = -1, insert_point, src_index = -1, pass_through = 0;
  1046. unsigned long flags;
  1047. switch (pcm_channel_id) {
  1048. case DSP_PCM_MAIN_CHANNEL:
  1049. mixer_scb = ins->master_mix_scb;
  1050. break;
  1051. case DSP_PCM_REAR_CHANNEL:
  1052. mixer_scb = ins->rear_mix_scb;
  1053. break;
  1054. case DSP_PCM_CENTER_LFE_CHANNEL:
  1055. mixer_scb = ins->center_lfe_mix_scb;
  1056. break;
  1057. case DSP_PCM_S71_CHANNEL:
  1058. /* TODO */
  1059. snd_BUG();
  1060. break;
  1061. case DSP_IEC958_CHANNEL:
  1062. if (snd_BUG_ON(!ins->asynch_tx_scb))
  1063. return NULL;
  1064. mixer_scb = ins->asynch_tx_scb;
  1065. /* if sample rate is set to 48khz we pass
  1066. the Sample Rate Converted (which could
  1067. alter the raw data stream ...) */
  1068. if (sample_rate == 48000) {
  1069. dev_dbg(chip->card->dev, "IEC958 pass through\n");
  1070. /* Hack to bypass creating a new SRC */
  1071. pass_through = 1;
  1072. }
  1073. break;
  1074. default:
  1075. snd_BUG();
  1076. return NULL;
  1077. }
  1078. /* default sample rate is 44100 */
  1079. if (!sample_rate) sample_rate = 44100;
  1080. /* search for a already created SRC SCB with the same sample rate */
  1081. for (i = 0; i < DSP_MAX_PCM_CHANNELS &&
  1082. (pcm_index == -1 || src_scb == NULL); ++i) {
  1083. /* virtual channel reserved
  1084. for capture */
  1085. if (i == CS46XX_DSP_CAPTURE_CHANNEL) continue;
  1086. if (ins->pcm_channels[i].active) {
  1087. if (!src_scb &&
  1088. ins->pcm_channels[i].sample_rate == sample_rate &&
  1089. ins->pcm_channels[i].mixer_scb == mixer_scb) {
  1090. src_scb = ins->pcm_channels[i].src_scb;
  1091. ins->pcm_channels[i].src_scb->ref_count ++;
  1092. src_index = ins->pcm_channels[i].src_slot;
  1093. }
  1094. } else if (pcm_index == -1) {
  1095. pcm_index = i;
  1096. }
  1097. }
  1098. if (pcm_index == -1) {
  1099. dev_err(chip->card->dev, "dsp_spos: no free PCM channel\n");
  1100. return NULL;
  1101. }
  1102. if (src_scb == NULL) {
  1103. if (ins->nsrc_scb >= DSP_MAX_SRC_NR) {
  1104. dev_err(chip->card->dev,
  1105. "dsp_spos: to many SRC instances\n!");
  1106. return NULL;
  1107. }
  1108. /* find a free slot */
  1109. for (i = 0; i < DSP_MAX_SRC_NR; ++i) {
  1110. if (ins->src_scb_slots[i] == 0) {
  1111. src_index = i;
  1112. ins->src_scb_slots[i] = 1;
  1113. break;
  1114. }
  1115. }
  1116. if (snd_BUG_ON(src_index == -1))
  1117. return NULL;
  1118. /* we need to create a new SRC SCB */
  1119. if (mixer_scb->sub_list_ptr == ins->the_null_scb) {
  1120. src_parent_scb = mixer_scb;
  1121. insert_point = SCB_ON_PARENT_SUBLIST_SCB;
  1122. } else {
  1123. src_parent_scb = find_next_free_scb(chip,mixer_scb->sub_list_ptr);
  1124. insert_point = SCB_ON_PARENT_NEXT_SCB;
  1125. }
  1126. snprintf (scb_name,DSP_MAX_SCB_NAME,"SrcTask_SCB%d",src_index);
  1127. dev_dbg(chip->card->dev,
  1128. "dsp_spos: creating SRC \"%s\"\n", scb_name);
  1129. src_scb = cs46xx_dsp_create_src_task_scb(chip,scb_name,
  1130. sample_rate,
  1131. src_output_buffer_addr[src_index],
  1132. src_delay_buffer_addr[src_index],
  1133. /* 0x400 - 0x600 source SCBs */
  1134. 0x400 + (src_index * 0x10) ,
  1135. src_parent_scb,
  1136. insert_point,
  1137. pass_through);
  1138. if (!src_scb) {
  1139. dev_err(chip->card->dev,
  1140. "dsp_spos: failed to create SRCtaskSCB\n");
  1141. return NULL;
  1142. }
  1143. /* cs46xx_dsp_set_src_sample_rate(chip,src_scb,sample_rate); */
  1144. ins->nsrc_scb ++;
  1145. }
  1146. snprintf (scb_name,DSP_MAX_SCB_NAME,"PCMReader_SCB%d",pcm_index);
  1147. dev_dbg(chip->card->dev, "dsp_spos: creating PCM \"%s\" (%d)\n",
  1148. scb_name, pcm_channel_id);
  1149. pcm_scb = cs46xx_dsp_create_pcm_reader_scb(chip,scb_name,
  1150. pcm_reader_buffer_addr[pcm_index],
  1151. /* 0x200 - 400 PCMreader SCBs */
  1152. (pcm_index * 0x10) + 0x200,
  1153. pcm_index, /* virtual channel 0-31 */
  1154. hw_dma_addr, /* pcm hw addr */
  1155. NULL, /* parent SCB ptr */
  1156. 0 /* insert point */
  1157. );
  1158. if (!pcm_scb) {
  1159. dev_err(chip->card->dev,
  1160. "dsp_spos: failed to create PCMreaderSCB\n");
  1161. return NULL;
  1162. }
  1163. spin_lock_irqsave(&chip->reg_lock, flags);
  1164. ins->pcm_channels[pcm_index].sample_rate = sample_rate;
  1165. ins->pcm_channels[pcm_index].pcm_reader_scb = pcm_scb;
  1166. ins->pcm_channels[pcm_index].src_scb = src_scb;
  1167. ins->pcm_channels[pcm_index].unlinked = 1;
  1168. ins->pcm_channels[pcm_index].private_data = private_data;
  1169. ins->pcm_channels[pcm_index].src_slot = src_index;
  1170. ins->pcm_channels[pcm_index].active = 1;
  1171. ins->pcm_channels[pcm_index].pcm_slot = pcm_index;
  1172. ins->pcm_channels[pcm_index].mixer_scb = mixer_scb;
  1173. ins->npcm_channels ++;
  1174. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1175. return (ins->pcm_channels + pcm_index);
  1176. }
  1177. int cs46xx_dsp_pcm_channel_set_period (struct snd_cs46xx * chip,
  1178. struct dsp_pcm_channel_descriptor * pcm_channel,
  1179. int period_size)
  1180. {
  1181. u32 temp = snd_cs46xx_peek (chip,pcm_channel->pcm_reader_scb->address << 2);
  1182. temp &= ~DMA_RQ_C1_SOURCE_SIZE_MASK;
  1183. switch (period_size) {
  1184. case 2048:
  1185. temp |= DMA_RQ_C1_SOURCE_MOD1024;
  1186. break;
  1187. case 1024:
  1188. temp |= DMA_RQ_C1_SOURCE_MOD512;
  1189. break;
  1190. case 512:
  1191. temp |= DMA_RQ_C1_SOURCE_MOD256;
  1192. break;
  1193. case 256:
  1194. temp |= DMA_RQ_C1_SOURCE_MOD128;
  1195. break;
  1196. case 128:
  1197. temp |= DMA_RQ_C1_SOURCE_MOD64;
  1198. break;
  1199. case 64:
  1200. temp |= DMA_RQ_C1_SOURCE_MOD32;
  1201. break;
  1202. case 32:
  1203. temp |= DMA_RQ_C1_SOURCE_MOD16;
  1204. break;
  1205. default:
  1206. dev_dbg(chip->card->dev,
  1207. "period size (%d) not supported by HW\n", period_size);
  1208. return -EINVAL;
  1209. }
  1210. snd_cs46xx_poke (chip,pcm_channel->pcm_reader_scb->address << 2,temp);
  1211. return 0;
  1212. }
  1213. int cs46xx_dsp_pcm_ostream_set_period (struct snd_cs46xx * chip,
  1214. int period_size)
  1215. {
  1216. u32 temp = snd_cs46xx_peek (chip,WRITEBACK_SCB_ADDR << 2);
  1217. temp &= ~DMA_RQ_C1_DEST_SIZE_MASK;
  1218. switch (period_size) {
  1219. case 2048:
  1220. temp |= DMA_RQ_C1_DEST_MOD1024;
  1221. break;
  1222. case 1024:
  1223. temp |= DMA_RQ_C1_DEST_MOD512;
  1224. break;
  1225. case 512:
  1226. temp |= DMA_RQ_C1_DEST_MOD256;
  1227. break;
  1228. case 256:
  1229. temp |= DMA_RQ_C1_DEST_MOD128;
  1230. break;
  1231. case 128:
  1232. temp |= DMA_RQ_C1_DEST_MOD64;
  1233. break;
  1234. case 64:
  1235. temp |= DMA_RQ_C1_DEST_MOD32;
  1236. break;
  1237. case 32:
  1238. temp |= DMA_RQ_C1_DEST_MOD16;
  1239. break;
  1240. default:
  1241. dev_dbg(chip->card->dev,
  1242. "period size (%d) not supported by HW\n", period_size);
  1243. return -EINVAL;
  1244. }
  1245. snd_cs46xx_poke (chip,WRITEBACK_SCB_ADDR << 2,temp);
  1246. return 0;
  1247. }
  1248. void cs46xx_dsp_destroy_pcm_channel (struct snd_cs46xx * chip,
  1249. struct dsp_pcm_channel_descriptor * pcm_channel)
  1250. {
  1251. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1252. unsigned long flags;
  1253. if (snd_BUG_ON(!pcm_channel->active ||
  1254. ins->npcm_channels <= 0 ||
  1255. pcm_channel->src_scb->ref_count <= 0))
  1256. return;
  1257. spin_lock_irqsave(&chip->reg_lock, flags);
  1258. pcm_channel->unlinked = 1;
  1259. pcm_channel->active = 0;
  1260. pcm_channel->private_data = NULL;
  1261. pcm_channel->src_scb->ref_count --;
  1262. ins->npcm_channels --;
  1263. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1264. cs46xx_dsp_remove_scb(chip,pcm_channel->pcm_reader_scb);
  1265. if (!pcm_channel->src_scb->ref_count) {
  1266. cs46xx_dsp_remove_scb(chip,pcm_channel->src_scb);
  1267. if (snd_BUG_ON(pcm_channel->src_slot < 0 ||
  1268. pcm_channel->src_slot >= DSP_MAX_SRC_NR))
  1269. return;
  1270. ins->src_scb_slots[pcm_channel->src_slot] = 0;
  1271. ins->nsrc_scb --;
  1272. }
  1273. }
  1274. int cs46xx_dsp_pcm_unlink (struct snd_cs46xx * chip,
  1275. struct dsp_pcm_channel_descriptor * pcm_channel)
  1276. {
  1277. unsigned long flags;
  1278. if (snd_BUG_ON(!pcm_channel->active ||
  1279. chip->dsp_spos_instance->npcm_channels <= 0))
  1280. return -EIO;
  1281. spin_lock_irqsave(&chip->reg_lock, flags);
  1282. if (pcm_channel->unlinked) {
  1283. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1284. return -EIO;
  1285. }
  1286. pcm_channel->unlinked = 1;
  1287. _dsp_unlink_scb (chip,pcm_channel->pcm_reader_scb);
  1288. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1289. return 0;
  1290. }
  1291. int cs46xx_dsp_pcm_link (struct snd_cs46xx * chip,
  1292. struct dsp_pcm_channel_descriptor * pcm_channel)
  1293. {
  1294. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1295. struct dsp_scb_descriptor * parent_scb;
  1296. struct dsp_scb_descriptor * src_scb = pcm_channel->src_scb;
  1297. unsigned long flags;
  1298. spin_lock_irqsave(&chip->reg_lock, flags);
  1299. if (pcm_channel->unlinked == 0) {
  1300. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1301. return -EIO;
  1302. }
  1303. parent_scb = src_scb;
  1304. if (src_scb->sub_list_ptr != ins->the_null_scb) {
  1305. src_scb->sub_list_ptr->parent_scb_ptr = pcm_channel->pcm_reader_scb;
  1306. pcm_channel->pcm_reader_scb->next_scb_ptr = src_scb->sub_list_ptr;
  1307. }
  1308. src_scb->sub_list_ptr = pcm_channel->pcm_reader_scb;
  1309. snd_BUG_ON(pcm_channel->pcm_reader_scb->parent_scb_ptr);
  1310. pcm_channel->pcm_reader_scb->parent_scb_ptr = parent_scb;
  1311. /* update SCB entry in DSP RAM */
  1312. cs46xx_dsp_spos_update_scb(chip,pcm_channel->pcm_reader_scb);
  1313. /* update parent SCB entry */
  1314. cs46xx_dsp_spos_update_scb(chip,parent_scb);
  1315. pcm_channel->unlinked = 0;
  1316. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1317. return 0;
  1318. }
  1319. struct dsp_scb_descriptor *
  1320. cs46xx_add_record_source (struct snd_cs46xx *chip, struct dsp_scb_descriptor * source,
  1321. u16 addr, char * scb_name)
  1322. {
  1323. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1324. struct dsp_scb_descriptor * parent;
  1325. struct dsp_scb_descriptor * pcm_input;
  1326. int insert_point;
  1327. if (snd_BUG_ON(!ins->record_mixer_scb))
  1328. return NULL;
  1329. if (ins->record_mixer_scb->sub_list_ptr != ins->the_null_scb) {
  1330. parent = find_next_free_scb (chip,ins->record_mixer_scb->sub_list_ptr);
  1331. insert_point = SCB_ON_PARENT_NEXT_SCB;
  1332. } else {
  1333. parent = ins->record_mixer_scb;
  1334. insert_point = SCB_ON_PARENT_SUBLIST_SCB;
  1335. }
  1336. pcm_input = cs46xx_dsp_create_pcm_serial_input_scb(chip,scb_name,addr,
  1337. source, parent,
  1338. insert_point);
  1339. return pcm_input;
  1340. }
  1341. int cs46xx_src_unlink(struct snd_cs46xx *chip, struct dsp_scb_descriptor * src)
  1342. {
  1343. unsigned long flags;
  1344. if (snd_BUG_ON(!src->parent_scb_ptr))
  1345. return -EINVAL;
  1346. /* mute SCB */
  1347. cs46xx_dsp_scb_set_volume (chip,src,0,0);
  1348. spin_lock_irqsave(&chip->reg_lock, flags);
  1349. _dsp_unlink_scb (chip,src);
  1350. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1351. return 0;
  1352. }
  1353. int cs46xx_src_link(struct snd_cs46xx *chip, struct dsp_scb_descriptor * src)
  1354. {
  1355. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1356. struct dsp_scb_descriptor * parent_scb;
  1357. if (snd_BUG_ON(src->parent_scb_ptr))
  1358. return -EINVAL;
  1359. if (snd_BUG_ON(!ins->master_mix_scb))
  1360. return -EINVAL;
  1361. if (ins->master_mix_scb->sub_list_ptr != ins->the_null_scb) {
  1362. parent_scb = find_next_free_scb (chip,ins->master_mix_scb->sub_list_ptr);
  1363. parent_scb->next_scb_ptr = src;
  1364. } else {
  1365. parent_scb = ins->master_mix_scb;
  1366. parent_scb->sub_list_ptr = src;
  1367. }
  1368. src->parent_scb_ptr = parent_scb;
  1369. /* update entry in DSP RAM */
  1370. cs46xx_dsp_spos_update_scb(chip,parent_scb);
  1371. return 0;
  1372. }
  1373. int cs46xx_dsp_enable_spdif_out (struct snd_cs46xx *chip)
  1374. {
  1375. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1376. if ( ! (ins->spdif_status_out & DSP_SPDIF_STATUS_HW_ENABLED) ) {
  1377. cs46xx_dsp_enable_spdif_hw (chip);
  1378. }
  1379. /* dont touch anything if SPDIF is open */
  1380. if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) {
  1381. /* when cs46xx_iec958_post_close(...) is called it
  1382. will call this function if necessary depending on
  1383. this bit */
  1384. ins->spdif_status_out |= DSP_SPDIF_STATUS_OUTPUT_ENABLED;
  1385. return -EBUSY;
  1386. }
  1387. if (snd_BUG_ON(ins->asynch_tx_scb))
  1388. return -EINVAL;
  1389. if (snd_BUG_ON(ins->master_mix_scb->next_scb_ptr !=
  1390. ins->the_null_scb))
  1391. return -EINVAL;
  1392. /* reset output snooper sample buffer pointer */
  1393. snd_cs46xx_poke (chip, (ins->ref_snoop_scb->address + 2) << 2,
  1394. (OUTPUT_SNOOP_BUFFER + 0x10) << 0x10 );
  1395. /* The asynch. transfer task */
  1396. ins->asynch_tx_scb = cs46xx_dsp_create_asynch_fg_tx_scb(chip,"AsynchFGTxSCB",ASYNCTX_SCB_ADDR,
  1397. SPDIFO_SCB_INST,
  1398. SPDIFO_IP_OUTPUT_BUFFER1,
  1399. ins->master_mix_scb,
  1400. SCB_ON_PARENT_NEXT_SCB);
  1401. if (!ins->asynch_tx_scb) return -ENOMEM;
  1402. ins->spdif_pcm_input_scb = cs46xx_dsp_create_pcm_serial_input_scb(chip,"PCMSerialInput_II",
  1403. PCMSERIALINII_SCB_ADDR,
  1404. ins->ref_snoop_scb,
  1405. ins->asynch_tx_scb,
  1406. SCB_ON_PARENT_SUBLIST_SCB);
  1407. if (!ins->spdif_pcm_input_scb) return -ENOMEM;
  1408. /* monitor state */
  1409. ins->spdif_status_out |= DSP_SPDIF_STATUS_OUTPUT_ENABLED;
  1410. return 0;
  1411. }
  1412. int cs46xx_dsp_disable_spdif_out (struct snd_cs46xx *chip)
  1413. {
  1414. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1415. /* dont touch anything if SPDIF is open */
  1416. if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) {
  1417. ins->spdif_status_out &= ~DSP_SPDIF_STATUS_OUTPUT_ENABLED;
  1418. return -EBUSY;
  1419. }
  1420. /* check integrety */
  1421. if (snd_BUG_ON(!ins->asynch_tx_scb))
  1422. return -EINVAL;
  1423. if (snd_BUG_ON(!ins->spdif_pcm_input_scb))
  1424. return -EINVAL;
  1425. if (snd_BUG_ON(ins->master_mix_scb->next_scb_ptr != ins->asynch_tx_scb))
  1426. return -EINVAL;
  1427. if (snd_BUG_ON(ins->asynch_tx_scb->parent_scb_ptr !=
  1428. ins->master_mix_scb))
  1429. return -EINVAL;
  1430. cs46xx_dsp_remove_scb (chip,ins->spdif_pcm_input_scb);
  1431. cs46xx_dsp_remove_scb (chip,ins->asynch_tx_scb);
  1432. ins->spdif_pcm_input_scb = NULL;
  1433. ins->asynch_tx_scb = NULL;
  1434. /* clear buffer to prevent any undesired noise */
  1435. _dsp_clear_sample_buffer(chip,SPDIFO_IP_OUTPUT_BUFFER1,256);
  1436. /* monitor state */
  1437. ins->spdif_status_out &= ~DSP_SPDIF_STATUS_OUTPUT_ENABLED;
  1438. return 0;
  1439. }
  1440. int cs46xx_iec958_pre_open (struct snd_cs46xx *chip)
  1441. {
  1442. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1443. if ( ins->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED ) {
  1444. /* remove AsynchFGTxSCB and and PCMSerialInput_II */
  1445. cs46xx_dsp_disable_spdif_out (chip);
  1446. /* save state */
  1447. ins->spdif_status_out |= DSP_SPDIF_STATUS_OUTPUT_ENABLED;
  1448. }
  1449. /* if not enabled already */
  1450. if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_HW_ENABLED) ) {
  1451. cs46xx_dsp_enable_spdif_hw (chip);
  1452. }
  1453. /* Create the asynch. transfer task for playback */
  1454. ins->asynch_tx_scb = cs46xx_dsp_create_asynch_fg_tx_scb(chip,"AsynchFGTxSCB",ASYNCTX_SCB_ADDR,
  1455. SPDIFO_SCB_INST,
  1456. SPDIFO_IP_OUTPUT_BUFFER1,
  1457. ins->master_mix_scb,
  1458. SCB_ON_PARENT_NEXT_SCB);
  1459. /* set spdif channel status value for streaming */
  1460. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, ins->spdif_csuv_stream);
  1461. ins->spdif_status_out |= DSP_SPDIF_STATUS_PLAYBACK_OPEN;
  1462. return 0;
  1463. }
  1464. int cs46xx_iec958_post_close (struct snd_cs46xx *chip)
  1465. {
  1466. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1467. if (snd_BUG_ON(!ins->asynch_tx_scb))
  1468. return -EINVAL;
  1469. ins->spdif_status_out &= ~DSP_SPDIF_STATUS_PLAYBACK_OPEN;
  1470. /* restore settings */
  1471. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, ins->spdif_csuv_default);
  1472. /* deallocate stuff */
  1473. if (ins->spdif_pcm_input_scb != NULL) {
  1474. cs46xx_dsp_remove_scb (chip,ins->spdif_pcm_input_scb);
  1475. ins->spdif_pcm_input_scb = NULL;
  1476. }
  1477. cs46xx_dsp_remove_scb (chip,ins->asynch_tx_scb);
  1478. ins->asynch_tx_scb = NULL;
  1479. /* clear buffer to prevent any undesired noise */
  1480. _dsp_clear_sample_buffer(chip,SPDIFO_IP_OUTPUT_BUFFER1,256);
  1481. /* restore state */
  1482. if ( ins->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED ) {
  1483. cs46xx_dsp_enable_spdif_out (chip);
  1484. }
  1485. return 0;
  1486. }