emufx.c 99 KB

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  1. /*
  2. * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
  3. * Creative Labs, Inc.
  4. * Routines for effect processor FX8010
  5. *
  6. * Copyright (c) by James Courtier-Dutton <James@superbug.co.uk>
  7. * Added EMU 1010 support.
  8. *
  9. * BUGS:
  10. * --
  11. *
  12. * TODO:
  13. * --
  14. *
  15. * This program is free software; you can redistribute it and/or modify
  16. * it under the terms of the GNU General Public License as published by
  17. * the Free Software Foundation; either version 2 of the License, or
  18. * (at your option) any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, write to the Free Software
  27. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  28. *
  29. */
  30. #include <linux/pci.h>
  31. #include <linux/capability.h>
  32. #include <linux/delay.h>
  33. #include <linux/slab.h>
  34. #include <linux/vmalloc.h>
  35. #include <linux/init.h>
  36. #include <linux/mutex.h>
  37. #include <linux/moduleparam.h>
  38. #include <linux/nospec.h>
  39. #include <sound/core.h>
  40. #include <sound/tlv.h>
  41. #include <sound/emu10k1.h>
  42. #if 0 /* for testing purposes - digital out -> capture */
  43. #define EMU10K1_CAPTURE_DIGITAL_OUT
  44. #endif
  45. #if 0 /* for testing purposes - set S/PDIF to AC3 output */
  46. #define EMU10K1_SET_AC3_IEC958
  47. #endif
  48. #if 0 /* for testing purposes - feed the front signal to Center/LFE outputs */
  49. #define EMU10K1_CENTER_LFE_FROM_FRONT
  50. #endif
  51. static bool high_res_gpr_volume;
  52. module_param(high_res_gpr_volume, bool, 0444);
  53. MODULE_PARM_DESC(high_res_gpr_volume, "GPR mixer controls use 31-bit range.");
  54. /*
  55. * Tables
  56. */
  57. static char *fxbuses[16] = {
  58. /* 0x00 */ "PCM Left",
  59. /* 0x01 */ "PCM Right",
  60. /* 0x02 */ "PCM Surround Left",
  61. /* 0x03 */ "PCM Surround Right",
  62. /* 0x04 */ "MIDI Left",
  63. /* 0x05 */ "MIDI Right",
  64. /* 0x06 */ "Center",
  65. /* 0x07 */ "LFE",
  66. /* 0x08 */ NULL,
  67. /* 0x09 */ NULL,
  68. /* 0x0a */ NULL,
  69. /* 0x0b */ NULL,
  70. /* 0x0c */ "MIDI Reverb",
  71. /* 0x0d */ "MIDI Chorus",
  72. /* 0x0e */ NULL,
  73. /* 0x0f */ NULL
  74. };
  75. static char *creative_ins[16] = {
  76. /* 0x00 */ "AC97 Left",
  77. /* 0x01 */ "AC97 Right",
  78. /* 0x02 */ "TTL IEC958 Left",
  79. /* 0x03 */ "TTL IEC958 Right",
  80. /* 0x04 */ "Zoom Video Left",
  81. /* 0x05 */ "Zoom Video Right",
  82. /* 0x06 */ "Optical IEC958 Left",
  83. /* 0x07 */ "Optical IEC958 Right",
  84. /* 0x08 */ "Line/Mic 1 Left",
  85. /* 0x09 */ "Line/Mic 1 Right",
  86. /* 0x0a */ "Coaxial IEC958 Left",
  87. /* 0x0b */ "Coaxial IEC958 Right",
  88. /* 0x0c */ "Line/Mic 2 Left",
  89. /* 0x0d */ "Line/Mic 2 Right",
  90. /* 0x0e */ NULL,
  91. /* 0x0f */ NULL
  92. };
  93. static char *audigy_ins[16] = {
  94. /* 0x00 */ "AC97 Left",
  95. /* 0x01 */ "AC97 Right",
  96. /* 0x02 */ "Audigy CD Left",
  97. /* 0x03 */ "Audigy CD Right",
  98. /* 0x04 */ "Optical IEC958 Left",
  99. /* 0x05 */ "Optical IEC958 Right",
  100. /* 0x06 */ NULL,
  101. /* 0x07 */ NULL,
  102. /* 0x08 */ "Line/Mic 2 Left",
  103. /* 0x09 */ "Line/Mic 2 Right",
  104. /* 0x0a */ "SPDIF Left",
  105. /* 0x0b */ "SPDIF Right",
  106. /* 0x0c */ "Aux2 Left",
  107. /* 0x0d */ "Aux2 Right",
  108. /* 0x0e */ NULL,
  109. /* 0x0f */ NULL
  110. };
  111. static char *creative_outs[32] = {
  112. /* 0x00 */ "AC97 Left",
  113. /* 0x01 */ "AC97 Right",
  114. /* 0x02 */ "Optical IEC958 Left",
  115. /* 0x03 */ "Optical IEC958 Right",
  116. /* 0x04 */ "Center",
  117. /* 0x05 */ "LFE",
  118. /* 0x06 */ "Headphone Left",
  119. /* 0x07 */ "Headphone Right",
  120. /* 0x08 */ "Surround Left",
  121. /* 0x09 */ "Surround Right",
  122. /* 0x0a */ "PCM Capture Left",
  123. /* 0x0b */ "PCM Capture Right",
  124. /* 0x0c */ "MIC Capture",
  125. /* 0x0d */ "AC97 Surround Left",
  126. /* 0x0e */ "AC97 Surround Right",
  127. /* 0x0f */ NULL,
  128. /* 0x10 */ NULL,
  129. /* 0x11 */ "Analog Center",
  130. /* 0x12 */ "Analog LFE",
  131. /* 0x13 */ NULL,
  132. /* 0x14 */ NULL,
  133. /* 0x15 */ NULL,
  134. /* 0x16 */ NULL,
  135. /* 0x17 */ NULL,
  136. /* 0x18 */ NULL,
  137. /* 0x19 */ NULL,
  138. /* 0x1a */ NULL,
  139. /* 0x1b */ NULL,
  140. /* 0x1c */ NULL,
  141. /* 0x1d */ NULL,
  142. /* 0x1e */ NULL,
  143. /* 0x1f */ NULL,
  144. };
  145. static char *audigy_outs[32] = {
  146. /* 0x00 */ "Digital Front Left",
  147. /* 0x01 */ "Digital Front Right",
  148. /* 0x02 */ "Digital Center",
  149. /* 0x03 */ "Digital LEF",
  150. /* 0x04 */ "Headphone Left",
  151. /* 0x05 */ "Headphone Right",
  152. /* 0x06 */ "Digital Rear Left",
  153. /* 0x07 */ "Digital Rear Right",
  154. /* 0x08 */ "Front Left",
  155. /* 0x09 */ "Front Right",
  156. /* 0x0a */ "Center",
  157. /* 0x0b */ "LFE",
  158. /* 0x0c */ NULL,
  159. /* 0x0d */ NULL,
  160. /* 0x0e */ "Rear Left",
  161. /* 0x0f */ "Rear Right",
  162. /* 0x10 */ "AC97 Front Left",
  163. /* 0x11 */ "AC97 Front Right",
  164. /* 0x12 */ "ADC Caputre Left",
  165. /* 0x13 */ "ADC Capture Right",
  166. /* 0x14 */ NULL,
  167. /* 0x15 */ NULL,
  168. /* 0x16 */ NULL,
  169. /* 0x17 */ NULL,
  170. /* 0x18 */ NULL,
  171. /* 0x19 */ NULL,
  172. /* 0x1a */ NULL,
  173. /* 0x1b */ NULL,
  174. /* 0x1c */ NULL,
  175. /* 0x1d */ NULL,
  176. /* 0x1e */ NULL,
  177. /* 0x1f */ NULL,
  178. };
  179. static const u32 bass_table[41][5] = {
  180. { 0x3e4f844f, 0x84ed4cc3, 0x3cc69927, 0x7b03553a, 0xc4da8486 },
  181. { 0x3e69a17a, 0x84c280fb, 0x3cd77cd4, 0x7b2f2a6f, 0xc4b08d1d },
  182. { 0x3e82ff42, 0x849991d5, 0x3ce7466b, 0x7b5917c6, 0xc48863ee },
  183. { 0x3e9bab3c, 0x847267f0, 0x3cf5ffe8, 0x7b813560, 0xc461f22c },
  184. { 0x3eb3b275, 0x844ced29, 0x3d03b295, 0x7ba79a1c, 0xc43d223b },
  185. { 0x3ecb2174, 0x84290c8b, 0x3d106714, 0x7bcc5ba3, 0xc419dfa5 },
  186. { 0x3ee2044b, 0x8406b244, 0x3d1c2561, 0x7bef8e77, 0xc3f8170f },
  187. { 0x3ef86698, 0x83e5cb96, 0x3d26f4d8, 0x7c114600, 0xc3d7b625 },
  188. { 0x3f0e5390, 0x83c646c9, 0x3d30dc39, 0x7c319498, 0xc3b8ab97 },
  189. { 0x3f23d60b, 0x83a81321, 0x3d39e1af, 0x7c508b9c, 0xc39ae704 },
  190. { 0x3f38f884, 0x838b20d2, 0x3d420ad2, 0x7c6e3b75, 0xc37e58f1 },
  191. { 0x3f4dc52c, 0x836f60ef, 0x3d495cab, 0x7c8ab3a6, 0xc362f2be },
  192. { 0x3f6245e8, 0x8354c565, 0x3d4fdbb8, 0x7ca602d6, 0xc348a69b },
  193. { 0x3f76845f, 0x833b40ec, 0x3d558bf0, 0x7cc036df, 0xc32f677c },
  194. { 0x3f8a8a03, 0x8322c6fb, 0x3d5a70c4, 0x7cd95cd7, 0xc317290b },
  195. { 0x3f9e6014, 0x830b4bc3, 0x3d5e8d25, 0x7cf1811a, 0xc2ffdfa5 },
  196. { 0x3fb20fae, 0x82f4c420, 0x3d61e37f, 0x7d08af56, 0xc2e9804a },
  197. { 0x3fc5a1cc, 0x82df2592, 0x3d6475c3, 0x7d1ef294, 0xc2d40096 },
  198. { 0x3fd91f55, 0x82ca6632, 0x3d664564, 0x7d345541, 0xc2bf56b9 },
  199. { 0x3fec9120, 0x82b67cac, 0x3d675356, 0x7d48e138, 0xc2ab796e },
  200. { 0x40000000, 0x82a36037, 0x3d67a012, 0x7d5c9fc9, 0xc2985fee },
  201. { 0x401374c7, 0x8291088a, 0x3d672b93, 0x7d6f99c3, 0xc28601f2 },
  202. { 0x4026f857, 0x827f6dd7, 0x3d65f559, 0x7d81d77c, 0xc27457a3 },
  203. { 0x403a939f, 0x826e88c5, 0x3d63fc63, 0x7d9360d4, 0xc2635996 },
  204. { 0x404e4faf, 0x825e5266, 0x3d613f32, 0x7da43d42, 0xc25300c6 },
  205. { 0x406235ba, 0x824ec434, 0x3d5dbbc3, 0x7db473d7, 0xc243468e },
  206. { 0x40764f1f, 0x823fd80c, 0x3d596f8f, 0x7dc40b44, 0xc23424a2 },
  207. { 0x408aa576, 0x82318824, 0x3d545787, 0x7dd309e2, 0xc2259509 },
  208. { 0x409f4296, 0x8223cf0b, 0x3d4e7012, 0x7de175b5, 0xc2179218 },
  209. { 0x40b430a0, 0x8216a7a1, 0x3d47b505, 0x7def5475, 0xc20a1670 },
  210. { 0x40c97a0a, 0x820a0d12, 0x3d4021a1, 0x7dfcab8d, 0xc1fd1cf5 },
  211. { 0x40df29a6, 0x81fdfad6, 0x3d37b08d, 0x7e098028, 0xc1f0a0ca },
  212. { 0x40f54ab1, 0x81f26ca9, 0x3d2e5bd1, 0x7e15d72b, 0xc1e49d52 },
  213. { 0x410be8da, 0x81e75e89, 0x3d241cce, 0x7e21b544, 0xc1d90e24 },
  214. { 0x41231051, 0x81dcccb3, 0x3d18ec37, 0x7e2d1ee6, 0xc1cdef10 },
  215. { 0x413acdd0, 0x81d2b39e, 0x3d0cc20a, 0x7e38184e, 0xc1c33c13 },
  216. { 0x41532ea7, 0x81c90ffb, 0x3cff9585, 0x7e42a58b, 0xc1b8f15a },
  217. { 0x416c40cd, 0x81bfdeb2, 0x3cf15d21, 0x7e4cca7c, 0xc1af0b3f },
  218. { 0x418612ea, 0x81b71cdc, 0x3ce20e85, 0x7e568ad3, 0xc1a58640 },
  219. { 0x41a0b465, 0x81aec7c5, 0x3cd19e7c, 0x7e5fea1e, 0xc19c5f03 },
  220. { 0x41bc3573, 0x81a6dcea, 0x3cc000e9, 0x7e68ebc2, 0xc1939250 }
  221. };
  222. static const u32 treble_table[41][5] = {
  223. { 0x0125cba9, 0xfed5debd, 0x00599b6c, 0x0d2506da, 0xfa85b354 },
  224. { 0x0142f67e, 0xfeb03163, 0x0066cd0f, 0x0d14c69d, 0xfa914473 },
  225. { 0x016328bd, 0xfe860158, 0x0075b7f2, 0x0d03eb27, 0xfa9d32d2 },
  226. { 0x0186b438, 0xfe56c982, 0x00869234, 0x0cf27048, 0xfaa97fca },
  227. { 0x01adf358, 0xfe21f5fe, 0x00999842, 0x0ce051c2, 0xfab62ca5 },
  228. { 0x01d949fa, 0xfde6e287, 0x00af0d8d, 0x0ccd8b4a, 0xfac33aa7 },
  229. { 0x02092669, 0xfda4d8bf, 0x00c73d4c, 0x0cba1884, 0xfad0ab07 },
  230. { 0x023e0268, 0xfd5b0e4a, 0x00e27b54, 0x0ca5f509, 0xfade7ef2 },
  231. { 0x0278645c, 0xfd08a2b0, 0x01012509, 0x0c911c63, 0xfaecb788 },
  232. { 0x02b8e091, 0xfcac9d1a, 0x0123a262, 0x0c7b8a14, 0xfafb55df },
  233. { 0x03001a9a, 0xfc45e9ce, 0x014a6709, 0x0c65398f, 0xfb0a5aff },
  234. { 0x034ec6d7, 0xfbd3576b, 0x0175f397, 0x0c4e2643, 0xfb19c7e4 },
  235. { 0x03a5ac15, 0xfb5393ee, 0x01a6d6ed, 0x0c364b94, 0xfb299d7c },
  236. { 0x0405a562, 0xfac52968, 0x01ddafae, 0x0c1da4e2, 0xfb39dca5 },
  237. { 0x046fa3fe, 0xfa267a66, 0x021b2ddd, 0x0c042d8d, 0xfb4a8631 },
  238. { 0x04e4b17f, 0xf975be0f, 0x0260149f, 0x0be9e0f2, 0xfb5b9ae0 },
  239. { 0x0565f220, 0xf8b0fbe5, 0x02ad3c29, 0x0bceba73, 0xfb6d1b60 },
  240. { 0x05f4a745, 0xf7d60722, 0x030393d4, 0x0bb2b578, 0xfb7f084d },
  241. { 0x06923236, 0xf6e279bd, 0x03642465, 0x0b95cd75, 0xfb916233 },
  242. { 0x07401713, 0xf5d3aef9, 0x03d01283, 0x0b77fded, 0xfba42984 },
  243. { 0x08000000, 0xf4a6bd88, 0x0448a161, 0x0b594278, 0xfbb75e9f },
  244. { 0x08d3c097, 0xf3587131, 0x04cf35a4, 0x0b3996c9, 0xfbcb01cb },
  245. { 0x09bd59a2, 0xf1e543f9, 0x05655880, 0x0b18f6b2, 0xfbdf1333 },
  246. { 0x0abefd0f, 0xf04956ca, 0x060cbb12, 0x0af75e2c, 0xfbf392e8 },
  247. { 0x0bdb123e, 0xee806984, 0x06c739fe, 0x0ad4c962, 0xfc0880dd },
  248. { 0x0d143a94, 0xec85d287, 0x0796e150, 0x0ab134b0, 0xfc1ddce5 },
  249. { 0x0e6d5664, 0xea547598, 0x087df0a0, 0x0a8c9cb6, 0xfc33a6ad },
  250. { 0x0fe98a2a, 0xe7e6ba35, 0x097edf83, 0x0a66fe5b, 0xfc49ddc2 },
  251. { 0x118c4421, 0xe536813a, 0x0a9c6248, 0x0a4056d7, 0xfc608185 },
  252. { 0x1359422e, 0xe23d19eb, 0x0bd96efb, 0x0a18a3bf, 0xfc77912c },
  253. { 0x1554982b, 0xdef33645, 0x0d3942bd, 0x09efe312, 0xfc8f0bc1 },
  254. { 0x1782b68a, 0xdb50deb1, 0x0ebf676d, 0x09c6133f, 0xfca6f019 },
  255. { 0x19e8715d, 0xd74d64fd, 0x106fb999, 0x099b3337, 0xfcbf3cd6 },
  256. { 0x1c8b07b8, 0xd2df56ab, 0x124e6ec8, 0x096f4274, 0xfcd7f060 },
  257. { 0x1f702b6d, 0xcdfc6e92, 0x14601c10, 0x0942410b, 0xfcf108e5 },
  258. { 0x229e0933, 0xc89985cd, 0x16a9bcfa, 0x09142fb5, 0xfd0a8451 },
  259. { 0x261b5118, 0xc2aa8409, 0x1930bab6, 0x08e50fdc, 0xfd24604d },
  260. { 0x29ef3f5d, 0xbc224f28, 0x1bfaf396, 0x08b4e3aa, 0xfd3e9a3b },
  261. { 0x2e21a59b, 0xb4f2ba46, 0x1f0ec2d6, 0x0883ae15, 0xfd592f33 },
  262. { 0x32baf44b, 0xad0c7429, 0x227308a3, 0x085172eb, 0xfd741bfd },
  263. { 0x37c4448b, 0xa45ef51d, 0x262f3267, 0x081e36dc, 0xfd8f5d14 }
  264. };
  265. /* dB gain = (float) 20 * log10( float(db_table_value) / 0x8000000 ) */
  266. static const u32 db_table[101] = {
  267. 0x00000000, 0x01571f82, 0x01674b41, 0x01783a1b, 0x0189f540,
  268. 0x019c8651, 0x01aff763, 0x01c45306, 0x01d9a446, 0x01eff6b8,
  269. 0x0207567a, 0x021fd03d, 0x0239714c, 0x02544792, 0x027061a1,
  270. 0x028dcebb, 0x02ac9edc, 0x02cce2bf, 0x02eeabe8, 0x03120cb0,
  271. 0x0337184e, 0x035de2df, 0x03868173, 0x03b10a18, 0x03dd93e9,
  272. 0x040c3713, 0x043d0cea, 0x04702ff3, 0x04a5bbf2, 0x04ddcdfb,
  273. 0x0518847f, 0x0555ff62, 0x05966005, 0x05d9c95d, 0x06206005,
  274. 0x066a4a52, 0x06b7b067, 0x0708bc4c, 0x075d9a01, 0x07b6779d,
  275. 0x08138561, 0x0874f5d5, 0x08dafde1, 0x0945d4ed, 0x09b5b4fd,
  276. 0x0a2adad1, 0x0aa58605, 0x0b25f936, 0x0bac7a24, 0x0c3951d8,
  277. 0x0ccccccc, 0x0d673b17, 0x0e08f093, 0x0eb24510, 0x0f639481,
  278. 0x101d3f2d, 0x10dfa9e6, 0x11ab3e3f, 0x12806ac3, 0x135fa333,
  279. 0x144960c5, 0x153e2266, 0x163e6cfe, 0x174acbb7, 0x1863d04d,
  280. 0x198a1357, 0x1abe349f, 0x1c00db77, 0x1d52b712, 0x1eb47ee6,
  281. 0x2026f30f, 0x21aadcb6, 0x23410e7e, 0x24ea64f9, 0x26a7c71d,
  282. 0x287a26c4, 0x2a62812c, 0x2c61df84, 0x2e795779, 0x30aa0bcf,
  283. 0x32f52cfe, 0x355bf9d8, 0x37dfc033, 0x3a81dda4, 0x3d43c038,
  284. 0x4026e73c, 0x432ce40f, 0x46575af8, 0x49a8040f, 0x4d20ac2a,
  285. 0x50c335d3, 0x54919a57, 0x588dead1, 0x5cba514a, 0x611911ea,
  286. 0x65ac8c2f, 0x6a773c39, 0x6f7bbc23, 0x74bcc56c, 0x7a3d3272,
  287. 0x7fffffff,
  288. };
  289. /* EMU10k1/EMU10k2 DSP control db gain */
  290. static const DECLARE_TLV_DB_SCALE(snd_emu10k1_db_scale1, -4000, 40, 1);
  291. static const DECLARE_TLV_DB_LINEAR(snd_emu10k1_db_linear, TLV_DB_GAIN_MUTE, 0);
  292. /* EMU10K1 bass/treble db gain */
  293. static const DECLARE_TLV_DB_SCALE(snd_emu10k1_bass_treble_db_scale, -1200, 60, 0);
  294. static const u32 onoff_table[2] = {
  295. 0x00000000, 0x00000001
  296. };
  297. /*
  298. */
  299. static inline mm_segment_t snd_enter_user(void)
  300. {
  301. mm_segment_t fs = get_fs();
  302. set_fs(get_ds());
  303. return fs;
  304. }
  305. static inline void snd_leave_user(mm_segment_t fs)
  306. {
  307. set_fs(fs);
  308. }
  309. /*
  310. * controls
  311. */
  312. static int snd_emu10k1_gpr_ctl_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  313. {
  314. struct snd_emu10k1_fx8010_ctl *ctl =
  315. (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
  316. if (ctl->min == 0 && ctl->max == 1)
  317. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  318. else
  319. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  320. uinfo->count = ctl->vcount;
  321. uinfo->value.integer.min = ctl->min;
  322. uinfo->value.integer.max = ctl->max;
  323. return 0;
  324. }
  325. static int snd_emu10k1_gpr_ctl_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  326. {
  327. struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
  328. struct snd_emu10k1_fx8010_ctl *ctl =
  329. (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
  330. unsigned long flags;
  331. unsigned int i;
  332. spin_lock_irqsave(&emu->reg_lock, flags);
  333. for (i = 0; i < ctl->vcount; i++)
  334. ucontrol->value.integer.value[i] = ctl->value[i];
  335. spin_unlock_irqrestore(&emu->reg_lock, flags);
  336. return 0;
  337. }
  338. static int snd_emu10k1_gpr_ctl_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  339. {
  340. struct snd_emu10k1 *emu = snd_kcontrol_chip(kcontrol);
  341. struct snd_emu10k1_fx8010_ctl *ctl =
  342. (struct snd_emu10k1_fx8010_ctl *) kcontrol->private_value;
  343. unsigned long flags;
  344. unsigned int nval, val;
  345. unsigned int i, j;
  346. int change = 0;
  347. spin_lock_irqsave(&emu->reg_lock, flags);
  348. for (i = 0; i < ctl->vcount; i++) {
  349. nval = ucontrol->value.integer.value[i];
  350. if (nval < ctl->min)
  351. nval = ctl->min;
  352. if (nval > ctl->max)
  353. nval = ctl->max;
  354. if (nval != ctl->value[i])
  355. change = 1;
  356. val = ctl->value[i] = nval;
  357. switch (ctl->translation) {
  358. case EMU10K1_GPR_TRANSLATION_NONE:
  359. snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, val);
  360. break;
  361. case EMU10K1_GPR_TRANSLATION_TABLE100:
  362. snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, db_table[val]);
  363. break;
  364. case EMU10K1_GPR_TRANSLATION_BASS:
  365. if ((ctl->count % 5) != 0 || (ctl->count / 5) != ctl->vcount) {
  366. change = -EIO;
  367. goto __error;
  368. }
  369. for (j = 0; j < 5; j++)
  370. snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[j * ctl->vcount + i], 0, bass_table[val][j]);
  371. break;
  372. case EMU10K1_GPR_TRANSLATION_TREBLE:
  373. if ((ctl->count % 5) != 0 || (ctl->count / 5) != ctl->vcount) {
  374. change = -EIO;
  375. goto __error;
  376. }
  377. for (j = 0; j < 5; j++)
  378. snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[j * ctl->vcount + i], 0, treble_table[val][j]);
  379. break;
  380. case EMU10K1_GPR_TRANSLATION_ONOFF:
  381. snd_emu10k1_ptr_write(emu, emu->gpr_base + ctl->gpr[i], 0, onoff_table[val]);
  382. break;
  383. }
  384. }
  385. __error:
  386. spin_unlock_irqrestore(&emu->reg_lock, flags);
  387. return change;
  388. }
  389. /*
  390. * Interrupt handler
  391. */
  392. static void snd_emu10k1_fx8010_interrupt(struct snd_emu10k1 *emu)
  393. {
  394. struct snd_emu10k1_fx8010_irq *irq, *nirq;
  395. irq = emu->fx8010.irq_handlers;
  396. while (irq) {
  397. nirq = irq->next; /* irq ptr can be removed from list */
  398. if (snd_emu10k1_ptr_read(emu, emu->gpr_base + irq->gpr_running, 0) & 0xffff0000) {
  399. if (irq->handler)
  400. irq->handler(emu, irq->private_data);
  401. snd_emu10k1_ptr_write(emu, emu->gpr_base + irq->gpr_running, 0, 1);
  402. }
  403. irq = nirq;
  404. }
  405. }
  406. int snd_emu10k1_fx8010_register_irq_handler(struct snd_emu10k1 *emu,
  407. snd_fx8010_irq_handler_t *handler,
  408. unsigned char gpr_running,
  409. void *private_data,
  410. struct snd_emu10k1_fx8010_irq **r_irq)
  411. {
  412. struct snd_emu10k1_fx8010_irq *irq;
  413. unsigned long flags;
  414. irq = kmalloc(sizeof(*irq), GFP_ATOMIC);
  415. if (irq == NULL)
  416. return -ENOMEM;
  417. irq->handler = handler;
  418. irq->gpr_running = gpr_running;
  419. irq->private_data = private_data;
  420. irq->next = NULL;
  421. spin_lock_irqsave(&emu->fx8010.irq_lock, flags);
  422. if (emu->fx8010.irq_handlers == NULL) {
  423. emu->fx8010.irq_handlers = irq;
  424. emu->dsp_interrupt = snd_emu10k1_fx8010_interrupt;
  425. snd_emu10k1_intr_enable(emu, INTE_FXDSPENABLE);
  426. } else {
  427. irq->next = emu->fx8010.irq_handlers;
  428. emu->fx8010.irq_handlers = irq;
  429. }
  430. spin_unlock_irqrestore(&emu->fx8010.irq_lock, flags);
  431. if (r_irq)
  432. *r_irq = irq;
  433. return 0;
  434. }
  435. int snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 *emu,
  436. struct snd_emu10k1_fx8010_irq *irq)
  437. {
  438. struct snd_emu10k1_fx8010_irq *tmp;
  439. unsigned long flags;
  440. spin_lock_irqsave(&emu->fx8010.irq_lock, flags);
  441. if ((tmp = emu->fx8010.irq_handlers) == irq) {
  442. emu->fx8010.irq_handlers = tmp->next;
  443. if (emu->fx8010.irq_handlers == NULL) {
  444. snd_emu10k1_intr_disable(emu, INTE_FXDSPENABLE);
  445. emu->dsp_interrupt = NULL;
  446. }
  447. } else {
  448. while (tmp && tmp->next != irq)
  449. tmp = tmp->next;
  450. if (tmp)
  451. tmp->next = tmp->next->next;
  452. }
  453. spin_unlock_irqrestore(&emu->fx8010.irq_lock, flags);
  454. kfree(irq);
  455. return 0;
  456. }
  457. /*************************************************************************
  458. * EMU10K1 effect manager
  459. *************************************************************************/
  460. static void snd_emu10k1_write_op(struct snd_emu10k1_fx8010_code *icode,
  461. unsigned int *ptr,
  462. u32 op, u32 r, u32 a, u32 x, u32 y)
  463. {
  464. u_int32_t *code;
  465. if (snd_BUG_ON(*ptr >= 512))
  466. return;
  467. code = (u_int32_t __force *)icode->code + (*ptr) * 2;
  468. set_bit(*ptr, icode->code_valid);
  469. code[0] = ((x & 0x3ff) << 10) | (y & 0x3ff);
  470. code[1] = ((op & 0x0f) << 20) | ((r & 0x3ff) << 10) | (a & 0x3ff);
  471. (*ptr)++;
  472. }
  473. #define OP(icode, ptr, op, r, a, x, y) \
  474. snd_emu10k1_write_op(icode, ptr, op, r, a, x, y)
  475. static void snd_emu10k1_audigy_write_op(struct snd_emu10k1_fx8010_code *icode,
  476. unsigned int *ptr,
  477. u32 op, u32 r, u32 a, u32 x, u32 y)
  478. {
  479. u_int32_t *code;
  480. if (snd_BUG_ON(*ptr >= 1024))
  481. return;
  482. code = (u_int32_t __force *)icode->code + (*ptr) * 2;
  483. set_bit(*ptr, icode->code_valid);
  484. code[0] = ((x & 0x7ff) << 12) | (y & 0x7ff);
  485. code[1] = ((op & 0x0f) << 24) | ((r & 0x7ff) << 12) | (a & 0x7ff);
  486. (*ptr)++;
  487. }
  488. #define A_OP(icode, ptr, op, r, a, x, y) \
  489. snd_emu10k1_audigy_write_op(icode, ptr, op, r, a, x, y)
  490. static void snd_emu10k1_efx_write(struct snd_emu10k1 *emu, unsigned int pc, unsigned int data)
  491. {
  492. pc += emu->audigy ? A_MICROCODEBASE : MICROCODEBASE;
  493. snd_emu10k1_ptr_write(emu, pc, 0, data);
  494. }
  495. unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc)
  496. {
  497. pc += emu->audigy ? A_MICROCODEBASE : MICROCODEBASE;
  498. return snd_emu10k1_ptr_read(emu, pc, 0);
  499. }
  500. static int snd_emu10k1_gpr_poke(struct snd_emu10k1 *emu,
  501. struct snd_emu10k1_fx8010_code *icode)
  502. {
  503. int gpr;
  504. u32 val;
  505. for (gpr = 0; gpr < (emu->audigy ? 0x200 : 0x100); gpr++) {
  506. if (!test_bit(gpr, icode->gpr_valid))
  507. continue;
  508. if (get_user(val, &icode->gpr_map[gpr]))
  509. return -EFAULT;
  510. snd_emu10k1_ptr_write(emu, emu->gpr_base + gpr, 0, val);
  511. }
  512. return 0;
  513. }
  514. static int snd_emu10k1_gpr_peek(struct snd_emu10k1 *emu,
  515. struct snd_emu10k1_fx8010_code *icode)
  516. {
  517. int gpr;
  518. u32 val;
  519. for (gpr = 0; gpr < (emu->audigy ? 0x200 : 0x100); gpr++) {
  520. set_bit(gpr, icode->gpr_valid);
  521. val = snd_emu10k1_ptr_read(emu, emu->gpr_base + gpr, 0);
  522. if (put_user(val, &icode->gpr_map[gpr]))
  523. return -EFAULT;
  524. }
  525. return 0;
  526. }
  527. static int snd_emu10k1_tram_poke(struct snd_emu10k1 *emu,
  528. struct snd_emu10k1_fx8010_code *icode)
  529. {
  530. int tram;
  531. u32 addr, val;
  532. for (tram = 0; tram < (emu->audigy ? 0x100 : 0xa0); tram++) {
  533. if (!test_bit(tram, icode->tram_valid))
  534. continue;
  535. if (get_user(val, &icode->tram_data_map[tram]) ||
  536. get_user(addr, &icode->tram_addr_map[tram]))
  537. return -EFAULT;
  538. snd_emu10k1_ptr_write(emu, TANKMEMDATAREGBASE + tram, 0, val);
  539. if (!emu->audigy) {
  540. snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + tram, 0, addr);
  541. } else {
  542. snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + tram, 0, addr << 12);
  543. snd_emu10k1_ptr_write(emu, A_TANKMEMCTLREGBASE + tram, 0, addr >> 20);
  544. }
  545. }
  546. return 0;
  547. }
  548. static int snd_emu10k1_tram_peek(struct snd_emu10k1 *emu,
  549. struct snd_emu10k1_fx8010_code *icode)
  550. {
  551. int tram;
  552. u32 val, addr;
  553. memset(icode->tram_valid, 0, sizeof(icode->tram_valid));
  554. for (tram = 0; tram < (emu->audigy ? 0x100 : 0xa0); tram++) {
  555. set_bit(tram, icode->tram_valid);
  556. val = snd_emu10k1_ptr_read(emu, TANKMEMDATAREGBASE + tram, 0);
  557. if (!emu->audigy) {
  558. addr = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + tram, 0);
  559. } else {
  560. addr = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + tram, 0) >> 12;
  561. addr |= snd_emu10k1_ptr_read(emu, A_TANKMEMCTLREGBASE + tram, 0) << 20;
  562. }
  563. if (put_user(val, &icode->tram_data_map[tram]) ||
  564. put_user(addr, &icode->tram_addr_map[tram]))
  565. return -EFAULT;
  566. }
  567. return 0;
  568. }
  569. static int snd_emu10k1_code_poke(struct snd_emu10k1 *emu,
  570. struct snd_emu10k1_fx8010_code *icode)
  571. {
  572. u32 pc, lo, hi;
  573. for (pc = 0; pc < (emu->audigy ? 2*1024 : 2*512); pc += 2) {
  574. if (!test_bit(pc / 2, icode->code_valid))
  575. continue;
  576. if (get_user(lo, &icode->code[pc + 0]) ||
  577. get_user(hi, &icode->code[pc + 1]))
  578. return -EFAULT;
  579. snd_emu10k1_efx_write(emu, pc + 0, lo);
  580. snd_emu10k1_efx_write(emu, pc + 1, hi);
  581. }
  582. return 0;
  583. }
  584. static int snd_emu10k1_code_peek(struct snd_emu10k1 *emu,
  585. struct snd_emu10k1_fx8010_code *icode)
  586. {
  587. u32 pc;
  588. memset(icode->code_valid, 0, sizeof(icode->code_valid));
  589. for (pc = 0; pc < (emu->audigy ? 2*1024 : 2*512); pc += 2) {
  590. set_bit(pc / 2, icode->code_valid);
  591. if (put_user(snd_emu10k1_efx_read(emu, pc + 0), &icode->code[pc + 0]))
  592. return -EFAULT;
  593. if (put_user(snd_emu10k1_efx_read(emu, pc + 1), &icode->code[pc + 1]))
  594. return -EFAULT;
  595. }
  596. return 0;
  597. }
  598. static struct snd_emu10k1_fx8010_ctl *
  599. snd_emu10k1_look_for_ctl(struct snd_emu10k1 *emu, struct snd_ctl_elem_id *id)
  600. {
  601. struct snd_emu10k1_fx8010_ctl *ctl;
  602. struct snd_kcontrol *kcontrol;
  603. list_for_each_entry(ctl, &emu->fx8010.gpr_ctl, list) {
  604. kcontrol = ctl->kcontrol;
  605. if (kcontrol->id.iface == id->iface &&
  606. !strcmp(kcontrol->id.name, id->name) &&
  607. kcontrol->id.index == id->index)
  608. return ctl;
  609. }
  610. return NULL;
  611. }
  612. #define MAX_TLV_SIZE 256
  613. static unsigned int *copy_tlv(const unsigned int __user *_tlv)
  614. {
  615. unsigned int data[2];
  616. unsigned int *tlv;
  617. if (!_tlv)
  618. return NULL;
  619. if (copy_from_user(data, _tlv, sizeof(data)))
  620. return NULL;
  621. if (data[1] >= MAX_TLV_SIZE)
  622. return NULL;
  623. tlv = kmalloc(data[1] + sizeof(data), GFP_KERNEL);
  624. if (!tlv)
  625. return NULL;
  626. memcpy(tlv, data, sizeof(data));
  627. if (copy_from_user(tlv + 2, _tlv + 2, data[1])) {
  628. kfree(tlv);
  629. return NULL;
  630. }
  631. return tlv;
  632. }
  633. static int copy_gctl(struct snd_emu10k1 *emu,
  634. struct snd_emu10k1_fx8010_control_gpr *gctl,
  635. struct snd_emu10k1_fx8010_control_gpr __user *_gctl,
  636. int idx)
  637. {
  638. struct snd_emu10k1_fx8010_control_old_gpr __user *octl;
  639. if (emu->support_tlv)
  640. return copy_from_user(gctl, &_gctl[idx], sizeof(*gctl));
  641. octl = (struct snd_emu10k1_fx8010_control_old_gpr __user *)_gctl;
  642. if (copy_from_user(gctl, &octl[idx], sizeof(*octl)))
  643. return -EFAULT;
  644. gctl->tlv = NULL;
  645. return 0;
  646. }
  647. static int copy_gctl_to_user(struct snd_emu10k1 *emu,
  648. struct snd_emu10k1_fx8010_control_gpr __user *_gctl,
  649. struct snd_emu10k1_fx8010_control_gpr *gctl,
  650. int idx)
  651. {
  652. struct snd_emu10k1_fx8010_control_old_gpr __user *octl;
  653. if (emu->support_tlv)
  654. return copy_to_user(&_gctl[idx], gctl, sizeof(*gctl));
  655. octl = (struct snd_emu10k1_fx8010_control_old_gpr __user *)_gctl;
  656. return copy_to_user(&octl[idx], gctl, sizeof(*octl));
  657. }
  658. static int snd_emu10k1_verify_controls(struct snd_emu10k1 *emu,
  659. struct snd_emu10k1_fx8010_code *icode)
  660. {
  661. unsigned int i;
  662. struct snd_ctl_elem_id __user *_id;
  663. struct snd_ctl_elem_id id;
  664. struct snd_emu10k1_fx8010_control_gpr *gctl;
  665. int err;
  666. for (i = 0, _id = icode->gpr_del_controls;
  667. i < icode->gpr_del_control_count; i++, _id++) {
  668. if (copy_from_user(&id, _id, sizeof(id)))
  669. return -EFAULT;
  670. if (snd_emu10k1_look_for_ctl(emu, &id) == NULL)
  671. return -ENOENT;
  672. }
  673. gctl = kmalloc(sizeof(*gctl), GFP_KERNEL);
  674. if (! gctl)
  675. return -ENOMEM;
  676. err = 0;
  677. for (i = 0; i < icode->gpr_add_control_count; i++) {
  678. if (copy_gctl(emu, gctl, icode->gpr_add_controls, i)) {
  679. err = -EFAULT;
  680. goto __error;
  681. }
  682. if (snd_emu10k1_look_for_ctl(emu, &gctl->id))
  683. continue;
  684. down_read(&emu->card->controls_rwsem);
  685. if (snd_ctl_find_id(emu->card, &gctl->id) != NULL) {
  686. up_read(&emu->card->controls_rwsem);
  687. err = -EEXIST;
  688. goto __error;
  689. }
  690. up_read(&emu->card->controls_rwsem);
  691. if (gctl->id.iface != SNDRV_CTL_ELEM_IFACE_MIXER &&
  692. gctl->id.iface != SNDRV_CTL_ELEM_IFACE_PCM) {
  693. err = -EINVAL;
  694. goto __error;
  695. }
  696. }
  697. for (i = 0; i < icode->gpr_list_control_count; i++) {
  698. /* FIXME: we need to check the WRITE access */
  699. if (copy_gctl(emu, gctl, icode->gpr_list_controls, i)) {
  700. err = -EFAULT;
  701. goto __error;
  702. }
  703. }
  704. __error:
  705. kfree(gctl);
  706. return err;
  707. }
  708. static void snd_emu10k1_ctl_private_free(struct snd_kcontrol *kctl)
  709. {
  710. struct snd_emu10k1_fx8010_ctl *ctl;
  711. ctl = (struct snd_emu10k1_fx8010_ctl *) kctl->private_value;
  712. kctl->private_value = 0;
  713. list_del(&ctl->list);
  714. kfree(ctl);
  715. kfree(kctl->tlv.p);
  716. }
  717. static int snd_emu10k1_add_controls(struct snd_emu10k1 *emu,
  718. struct snd_emu10k1_fx8010_code *icode)
  719. {
  720. unsigned int i, j;
  721. struct snd_emu10k1_fx8010_control_gpr *gctl;
  722. struct snd_emu10k1_fx8010_ctl *ctl, *nctl;
  723. struct snd_kcontrol_new knew;
  724. struct snd_kcontrol *kctl;
  725. struct snd_ctl_elem_value *val;
  726. int err = 0;
  727. val = kmalloc(sizeof(*val), GFP_KERNEL);
  728. gctl = kmalloc(sizeof(*gctl), GFP_KERNEL);
  729. nctl = kmalloc(sizeof(*nctl), GFP_KERNEL);
  730. if (!val || !gctl || !nctl) {
  731. err = -ENOMEM;
  732. goto __error;
  733. }
  734. for (i = 0; i < icode->gpr_add_control_count; i++) {
  735. if (copy_gctl(emu, gctl, icode->gpr_add_controls, i)) {
  736. err = -EFAULT;
  737. goto __error;
  738. }
  739. if (gctl->id.iface != SNDRV_CTL_ELEM_IFACE_MIXER &&
  740. gctl->id.iface != SNDRV_CTL_ELEM_IFACE_PCM) {
  741. err = -EINVAL;
  742. goto __error;
  743. }
  744. if (! gctl->id.name[0]) {
  745. err = -EINVAL;
  746. goto __error;
  747. }
  748. ctl = snd_emu10k1_look_for_ctl(emu, &gctl->id);
  749. memset(&knew, 0, sizeof(knew));
  750. knew.iface = gctl->id.iface;
  751. knew.name = gctl->id.name;
  752. knew.index = gctl->id.index;
  753. knew.device = gctl->id.device;
  754. knew.subdevice = gctl->id.subdevice;
  755. knew.info = snd_emu10k1_gpr_ctl_info;
  756. knew.tlv.p = copy_tlv(gctl->tlv);
  757. if (knew.tlv.p)
  758. knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
  759. SNDRV_CTL_ELEM_ACCESS_TLV_READ;
  760. knew.get = snd_emu10k1_gpr_ctl_get;
  761. knew.put = snd_emu10k1_gpr_ctl_put;
  762. memset(nctl, 0, sizeof(*nctl));
  763. nctl->vcount = gctl->vcount;
  764. nctl->count = gctl->count;
  765. for (j = 0; j < 32; j++) {
  766. nctl->gpr[j] = gctl->gpr[j];
  767. nctl->value[j] = ~gctl->value[j]; /* inverted, we want to write new value in gpr_ctl_put() */
  768. val->value.integer.value[j] = gctl->value[j];
  769. }
  770. nctl->min = gctl->min;
  771. nctl->max = gctl->max;
  772. nctl->translation = gctl->translation;
  773. if (ctl == NULL) {
  774. ctl = kmalloc(sizeof(*ctl), GFP_KERNEL);
  775. if (ctl == NULL) {
  776. err = -ENOMEM;
  777. kfree(knew.tlv.p);
  778. goto __error;
  779. }
  780. knew.private_value = (unsigned long)ctl;
  781. *ctl = *nctl;
  782. if ((err = snd_ctl_add(emu->card, kctl = snd_ctl_new1(&knew, emu))) < 0) {
  783. kfree(ctl);
  784. kfree(knew.tlv.p);
  785. goto __error;
  786. }
  787. kctl->private_free = snd_emu10k1_ctl_private_free;
  788. ctl->kcontrol = kctl;
  789. list_add_tail(&ctl->list, &emu->fx8010.gpr_ctl);
  790. } else {
  791. /* overwrite */
  792. nctl->list = ctl->list;
  793. nctl->kcontrol = ctl->kcontrol;
  794. *ctl = *nctl;
  795. snd_ctl_notify(emu->card, SNDRV_CTL_EVENT_MASK_VALUE |
  796. SNDRV_CTL_EVENT_MASK_INFO, &ctl->kcontrol->id);
  797. }
  798. snd_emu10k1_gpr_ctl_put(ctl->kcontrol, val);
  799. }
  800. __error:
  801. kfree(nctl);
  802. kfree(gctl);
  803. kfree(val);
  804. return err;
  805. }
  806. static int snd_emu10k1_del_controls(struct snd_emu10k1 *emu,
  807. struct snd_emu10k1_fx8010_code *icode)
  808. {
  809. unsigned int i;
  810. struct snd_ctl_elem_id id;
  811. struct snd_ctl_elem_id __user *_id;
  812. struct snd_emu10k1_fx8010_ctl *ctl;
  813. struct snd_card *card = emu->card;
  814. for (i = 0, _id = icode->gpr_del_controls;
  815. i < icode->gpr_del_control_count; i++, _id++) {
  816. if (copy_from_user(&id, _id, sizeof(id)))
  817. return -EFAULT;
  818. down_write(&card->controls_rwsem);
  819. ctl = snd_emu10k1_look_for_ctl(emu, &id);
  820. if (ctl)
  821. snd_ctl_remove(card, ctl->kcontrol);
  822. up_write(&card->controls_rwsem);
  823. }
  824. return 0;
  825. }
  826. static int snd_emu10k1_list_controls(struct snd_emu10k1 *emu,
  827. struct snd_emu10k1_fx8010_code *icode)
  828. {
  829. unsigned int i = 0, j;
  830. unsigned int total = 0;
  831. struct snd_emu10k1_fx8010_control_gpr *gctl;
  832. struct snd_emu10k1_fx8010_ctl *ctl;
  833. struct snd_ctl_elem_id *id;
  834. gctl = kmalloc(sizeof(*gctl), GFP_KERNEL);
  835. if (! gctl)
  836. return -ENOMEM;
  837. list_for_each_entry(ctl, &emu->fx8010.gpr_ctl, list) {
  838. total++;
  839. if (icode->gpr_list_controls &&
  840. i < icode->gpr_list_control_count) {
  841. memset(gctl, 0, sizeof(*gctl));
  842. id = &ctl->kcontrol->id;
  843. gctl->id.iface = id->iface;
  844. strlcpy(gctl->id.name, id->name, sizeof(gctl->id.name));
  845. gctl->id.index = id->index;
  846. gctl->id.device = id->device;
  847. gctl->id.subdevice = id->subdevice;
  848. gctl->vcount = ctl->vcount;
  849. gctl->count = ctl->count;
  850. for (j = 0; j < 32; j++) {
  851. gctl->gpr[j] = ctl->gpr[j];
  852. gctl->value[j] = ctl->value[j];
  853. }
  854. gctl->min = ctl->min;
  855. gctl->max = ctl->max;
  856. gctl->translation = ctl->translation;
  857. if (copy_gctl_to_user(emu, icode->gpr_list_controls,
  858. gctl, i)) {
  859. kfree(gctl);
  860. return -EFAULT;
  861. }
  862. i++;
  863. }
  864. }
  865. icode->gpr_list_control_total = total;
  866. kfree(gctl);
  867. return 0;
  868. }
  869. static int snd_emu10k1_icode_poke(struct snd_emu10k1 *emu,
  870. struct snd_emu10k1_fx8010_code *icode)
  871. {
  872. int err = 0;
  873. mutex_lock(&emu->fx8010.lock);
  874. if ((err = snd_emu10k1_verify_controls(emu, icode)) < 0)
  875. goto __error;
  876. strlcpy(emu->fx8010.name, icode->name, sizeof(emu->fx8010.name));
  877. /* stop FX processor - this may be dangerous, but it's better to miss
  878. some samples than generate wrong ones - [jk] */
  879. if (emu->audigy)
  880. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_SINGLE_STEP);
  881. else
  882. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_SINGLE_STEP);
  883. /* ok, do the main job */
  884. if ((err = snd_emu10k1_del_controls(emu, icode)) < 0 ||
  885. (err = snd_emu10k1_gpr_poke(emu, icode)) < 0 ||
  886. (err = snd_emu10k1_tram_poke(emu, icode)) < 0 ||
  887. (err = snd_emu10k1_code_poke(emu, icode)) < 0 ||
  888. (err = snd_emu10k1_add_controls(emu, icode)) < 0)
  889. goto __error;
  890. /* start FX processor when the DSP code is updated */
  891. if (emu->audigy)
  892. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
  893. else
  894. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);
  895. __error:
  896. mutex_unlock(&emu->fx8010.lock);
  897. return err;
  898. }
  899. static int snd_emu10k1_icode_peek(struct snd_emu10k1 *emu,
  900. struct snd_emu10k1_fx8010_code *icode)
  901. {
  902. int err;
  903. mutex_lock(&emu->fx8010.lock);
  904. strlcpy(icode->name, emu->fx8010.name, sizeof(icode->name));
  905. /* ok, do the main job */
  906. err = snd_emu10k1_gpr_peek(emu, icode);
  907. if (err >= 0)
  908. err = snd_emu10k1_tram_peek(emu, icode);
  909. if (err >= 0)
  910. err = snd_emu10k1_code_peek(emu, icode);
  911. if (err >= 0)
  912. err = snd_emu10k1_list_controls(emu, icode);
  913. mutex_unlock(&emu->fx8010.lock);
  914. return err;
  915. }
  916. static int snd_emu10k1_ipcm_poke(struct snd_emu10k1 *emu,
  917. struct snd_emu10k1_fx8010_pcm_rec *ipcm)
  918. {
  919. unsigned int i;
  920. int err = 0;
  921. struct snd_emu10k1_fx8010_pcm *pcm;
  922. if (ipcm->substream >= EMU10K1_FX8010_PCM_COUNT)
  923. return -EINVAL;
  924. ipcm->substream = array_index_nospec(ipcm->substream,
  925. EMU10K1_FX8010_PCM_COUNT);
  926. if (ipcm->channels > 32)
  927. return -EINVAL;
  928. pcm = &emu->fx8010.pcm[ipcm->substream];
  929. mutex_lock(&emu->fx8010.lock);
  930. spin_lock_irq(&emu->reg_lock);
  931. if (pcm->opened) {
  932. err = -EBUSY;
  933. goto __error;
  934. }
  935. if (ipcm->channels == 0) { /* remove */
  936. pcm->valid = 0;
  937. } else {
  938. /* FIXME: we need to add universal code to the PCM transfer routine */
  939. if (ipcm->channels != 2) {
  940. err = -EINVAL;
  941. goto __error;
  942. }
  943. pcm->valid = 1;
  944. pcm->opened = 0;
  945. pcm->channels = ipcm->channels;
  946. pcm->tram_start = ipcm->tram_start;
  947. pcm->buffer_size = ipcm->buffer_size;
  948. pcm->gpr_size = ipcm->gpr_size;
  949. pcm->gpr_count = ipcm->gpr_count;
  950. pcm->gpr_tmpcount = ipcm->gpr_tmpcount;
  951. pcm->gpr_ptr = ipcm->gpr_ptr;
  952. pcm->gpr_trigger = ipcm->gpr_trigger;
  953. pcm->gpr_running = ipcm->gpr_running;
  954. for (i = 0; i < pcm->channels; i++)
  955. pcm->etram[i] = ipcm->etram[i];
  956. }
  957. __error:
  958. spin_unlock_irq(&emu->reg_lock);
  959. mutex_unlock(&emu->fx8010.lock);
  960. return err;
  961. }
  962. static int snd_emu10k1_ipcm_peek(struct snd_emu10k1 *emu,
  963. struct snd_emu10k1_fx8010_pcm_rec *ipcm)
  964. {
  965. unsigned int i;
  966. int err = 0;
  967. struct snd_emu10k1_fx8010_pcm *pcm;
  968. if (ipcm->substream >= EMU10K1_FX8010_PCM_COUNT)
  969. return -EINVAL;
  970. ipcm->substream = array_index_nospec(ipcm->substream,
  971. EMU10K1_FX8010_PCM_COUNT);
  972. pcm = &emu->fx8010.pcm[ipcm->substream];
  973. mutex_lock(&emu->fx8010.lock);
  974. spin_lock_irq(&emu->reg_lock);
  975. ipcm->channels = pcm->channels;
  976. ipcm->tram_start = pcm->tram_start;
  977. ipcm->buffer_size = pcm->buffer_size;
  978. ipcm->gpr_size = pcm->gpr_size;
  979. ipcm->gpr_ptr = pcm->gpr_ptr;
  980. ipcm->gpr_count = pcm->gpr_count;
  981. ipcm->gpr_tmpcount = pcm->gpr_tmpcount;
  982. ipcm->gpr_trigger = pcm->gpr_trigger;
  983. ipcm->gpr_running = pcm->gpr_running;
  984. for (i = 0; i < pcm->channels; i++)
  985. ipcm->etram[i] = pcm->etram[i];
  986. ipcm->res1 = ipcm->res2 = 0;
  987. ipcm->pad = 0;
  988. spin_unlock_irq(&emu->reg_lock);
  989. mutex_unlock(&emu->fx8010.lock);
  990. return err;
  991. }
  992. #define SND_EMU10K1_GPR_CONTROLS 44
  993. #define SND_EMU10K1_INPUTS 12
  994. #define SND_EMU10K1_PLAYBACK_CHANNELS 8
  995. #define SND_EMU10K1_CAPTURE_CHANNELS 4
  996. static void
  997. snd_emu10k1_init_mono_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
  998. const char *name, int gpr, int defval)
  999. {
  1000. ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  1001. strcpy(ctl->id.name, name);
  1002. ctl->vcount = ctl->count = 1;
  1003. ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
  1004. if (high_res_gpr_volume) {
  1005. ctl->min = 0;
  1006. ctl->max = 0x7fffffff;
  1007. ctl->tlv = snd_emu10k1_db_linear;
  1008. ctl->translation = EMU10K1_GPR_TRANSLATION_NONE;
  1009. } else {
  1010. ctl->min = 0;
  1011. ctl->max = 100;
  1012. ctl->tlv = snd_emu10k1_db_scale1;
  1013. ctl->translation = EMU10K1_GPR_TRANSLATION_TABLE100;
  1014. }
  1015. }
  1016. static void
  1017. snd_emu10k1_init_stereo_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
  1018. const char *name, int gpr, int defval)
  1019. {
  1020. ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  1021. strcpy(ctl->id.name, name);
  1022. ctl->vcount = ctl->count = 2;
  1023. ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
  1024. ctl->gpr[1] = gpr + 1; ctl->value[1] = defval;
  1025. if (high_res_gpr_volume) {
  1026. ctl->min = 0;
  1027. ctl->max = 0x7fffffff;
  1028. ctl->tlv = snd_emu10k1_db_linear;
  1029. ctl->translation = EMU10K1_GPR_TRANSLATION_NONE;
  1030. } else {
  1031. ctl->min = 0;
  1032. ctl->max = 100;
  1033. ctl->tlv = snd_emu10k1_db_scale1;
  1034. ctl->translation = EMU10K1_GPR_TRANSLATION_TABLE100;
  1035. }
  1036. }
  1037. static void
  1038. snd_emu10k1_init_mono_onoff_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
  1039. const char *name, int gpr, int defval)
  1040. {
  1041. ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  1042. strcpy(ctl->id.name, name);
  1043. ctl->vcount = ctl->count = 1;
  1044. ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
  1045. ctl->min = 0;
  1046. ctl->max = 1;
  1047. ctl->translation = EMU10K1_GPR_TRANSLATION_ONOFF;
  1048. }
  1049. static void
  1050. snd_emu10k1_init_stereo_onoff_control(struct snd_emu10k1_fx8010_control_gpr *ctl,
  1051. const char *name, int gpr, int defval)
  1052. {
  1053. ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  1054. strcpy(ctl->id.name, name);
  1055. ctl->vcount = ctl->count = 2;
  1056. ctl->gpr[0] = gpr + 0; ctl->value[0] = defval;
  1057. ctl->gpr[1] = gpr + 1; ctl->value[1] = defval;
  1058. ctl->min = 0;
  1059. ctl->max = 1;
  1060. ctl->translation = EMU10K1_GPR_TRANSLATION_ONOFF;
  1061. }
  1062. /*
  1063. * Used for emu1010 - conversion from 32-bit capture inputs from HANA
  1064. * to 2 x 16-bit registers in audigy - their values are read via DMA.
  1065. * Conversion is performed by Audigy DSP instructions of FX8010.
  1066. */
  1067. static int snd_emu10k1_audigy_dsp_convert_32_to_2x16(
  1068. struct snd_emu10k1_fx8010_code *icode,
  1069. u32 *ptr, int tmp, int bit_shifter16,
  1070. int reg_in, int reg_out)
  1071. {
  1072. A_OP(icode, ptr, iACC3, A_GPR(tmp + 1), reg_in, A_C_00000000, A_C_00000000);
  1073. A_OP(icode, ptr, iANDXOR, A_GPR(tmp), A_GPR(tmp + 1), A_GPR(bit_shifter16 - 1), A_C_00000000);
  1074. A_OP(icode, ptr, iTSTNEG, A_GPR(tmp + 2), A_GPR(tmp), A_C_80000000, A_GPR(bit_shifter16 - 2));
  1075. A_OP(icode, ptr, iANDXOR, A_GPR(tmp + 2), A_GPR(tmp + 2), A_C_80000000, A_C_00000000);
  1076. A_OP(icode, ptr, iANDXOR, A_GPR(tmp), A_GPR(tmp), A_GPR(bit_shifter16 - 3), A_C_00000000);
  1077. A_OP(icode, ptr, iMACINT0, A_GPR(tmp), A_C_00000000, A_GPR(tmp), A_C_00010000);
  1078. A_OP(icode, ptr, iANDXOR, reg_out, A_GPR(tmp), A_C_ffffffff, A_GPR(tmp + 2));
  1079. A_OP(icode, ptr, iACC3, reg_out + 1, A_GPR(tmp + 1), A_C_00000000, A_C_00000000);
  1080. return 1;
  1081. }
  1082. /*
  1083. * initial DSP configuration for Audigy
  1084. */
  1085. static int _snd_emu10k1_audigy_init_efx(struct snd_emu10k1 *emu)
  1086. {
  1087. int err, i, z, gpr, nctl;
  1088. int bit_shifter16;
  1089. const int playback = 10;
  1090. const int capture = playback + (SND_EMU10K1_PLAYBACK_CHANNELS * 2); /* we reserve 10 voices */
  1091. const int stereo_mix = capture + 2;
  1092. const int tmp = 0x88;
  1093. u32 ptr;
  1094. struct snd_emu10k1_fx8010_code *icode = NULL;
  1095. struct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl;
  1096. u32 *gpr_map;
  1097. mm_segment_t seg;
  1098. err = -ENOMEM;
  1099. icode = kzalloc(sizeof(*icode), GFP_KERNEL);
  1100. if (!icode)
  1101. return err;
  1102. icode->gpr_map = (u_int32_t __user *) kcalloc(512 + 256 + 256 + 2 * 1024,
  1103. sizeof(u_int32_t), GFP_KERNEL);
  1104. if (!icode->gpr_map)
  1105. goto __err_gpr;
  1106. controls = kcalloc(SND_EMU10K1_GPR_CONTROLS,
  1107. sizeof(*controls), GFP_KERNEL);
  1108. if (!controls)
  1109. goto __err_ctrls;
  1110. gpr_map = (u32 __force *)icode->gpr_map;
  1111. icode->tram_data_map = icode->gpr_map + 512;
  1112. icode->tram_addr_map = icode->tram_data_map + 256;
  1113. icode->code = icode->tram_addr_map + 256;
  1114. /* clear free GPRs */
  1115. for (i = 0; i < 512; i++)
  1116. set_bit(i, icode->gpr_valid);
  1117. /* clear TRAM data & address lines */
  1118. for (i = 0; i < 256; i++)
  1119. set_bit(i, icode->tram_valid);
  1120. strcpy(icode->name, "Audigy DSP code for ALSA");
  1121. ptr = 0;
  1122. nctl = 0;
  1123. gpr = stereo_mix + 10;
  1124. gpr_map[gpr++] = 0x00007fff;
  1125. gpr_map[gpr++] = 0x00008000;
  1126. gpr_map[gpr++] = 0x0000ffff;
  1127. bit_shifter16 = gpr;
  1128. /* stop FX processor */
  1129. snd_emu10k1_ptr_write(emu, A_DBG, 0, (emu->fx8010.dbg = 0) | A_DBG_SINGLE_STEP);
  1130. #if 1
  1131. /* PCM front Playback Volume (independent from stereo mix)
  1132. * playback = 0 + ( gpr * FXBUS_PCM_LEFT_FRONT >> 31)
  1133. * where gpr contains attenuation from corresponding mixer control
  1134. * (snd_emu10k1_init_stereo_control)
  1135. */
  1136. A_OP(icode, &ptr, iMAC0, A_GPR(playback), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_FRONT));
  1137. A_OP(icode, &ptr, iMAC0, A_GPR(playback+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_FRONT));
  1138. snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Front Playback Volume", gpr, 100);
  1139. gpr += 2;
  1140. /* PCM Surround Playback (independent from stereo mix) */
  1141. A_OP(icode, &ptr, iMAC0, A_GPR(playback+2), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_REAR));
  1142. A_OP(icode, &ptr, iMAC0, A_GPR(playback+3), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_REAR));
  1143. snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Surround Playback Volume", gpr, 100);
  1144. gpr += 2;
  1145. /* PCM Side Playback (independent from stereo mix) */
  1146. if (emu->card_capabilities->spk71) {
  1147. A_OP(icode, &ptr, iMAC0, A_GPR(playback+6), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT_SIDE));
  1148. A_OP(icode, &ptr, iMAC0, A_GPR(playback+7), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT_SIDE));
  1149. snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Side Playback Volume", gpr, 100);
  1150. gpr += 2;
  1151. }
  1152. /* PCM Center Playback (independent from stereo mix) */
  1153. A_OP(icode, &ptr, iMAC0, A_GPR(playback+4), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_CENTER));
  1154. snd_emu10k1_init_mono_control(&controls[nctl++], "PCM Center Playback Volume", gpr, 100);
  1155. gpr++;
  1156. /* PCM LFE Playback (independent from stereo mix) */
  1157. A_OP(icode, &ptr, iMAC0, A_GPR(playback+5), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LFE));
  1158. snd_emu10k1_init_mono_control(&controls[nctl++], "PCM LFE Playback Volume", gpr, 100);
  1159. gpr++;
  1160. /*
  1161. * Stereo Mix
  1162. */
  1163. /* Wave (PCM) Playback Volume (will be renamed later) */
  1164. A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT));
  1165. A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT));
  1166. snd_emu10k1_init_stereo_control(&controls[nctl++], "Wave Playback Volume", gpr, 100);
  1167. gpr += 2;
  1168. /* Synth Playback */
  1169. A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix+0), A_GPR(stereo_mix+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT));
  1170. A_OP(icode, &ptr, iMAC0, A_GPR(stereo_mix+1), A_GPR(stereo_mix+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT));
  1171. snd_emu10k1_init_stereo_control(&controls[nctl++], "Synth Playback Volume", gpr, 100);
  1172. gpr += 2;
  1173. /* Wave (PCM) Capture */
  1174. A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_C_00000000, A_GPR(gpr), A_FXBUS(FXBUS_PCM_LEFT));
  1175. A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_C_00000000, A_GPR(gpr+1), A_FXBUS(FXBUS_PCM_RIGHT));
  1176. snd_emu10k1_init_stereo_control(&controls[nctl++], "PCM Capture Volume", gpr, 0);
  1177. gpr += 2;
  1178. /* Synth Capture */
  1179. A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_FXBUS(FXBUS_MIDI_LEFT));
  1180. A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+1), A_FXBUS(FXBUS_MIDI_RIGHT));
  1181. snd_emu10k1_init_stereo_control(&controls[nctl++], "Synth Capture Volume", gpr, 0);
  1182. gpr += 2;
  1183. /*
  1184. * inputs
  1185. */
  1186. #define A_ADD_VOLUME_IN(var,vol,input) \
  1187. A_OP(icode, &ptr, iMAC0, A_GPR(var), A_GPR(var), A_GPR(vol), A_EXTIN(input))
  1188. /* emu1212 DSP 0 and DSP 1 Capture */
  1189. if (emu->card_capabilities->emu_model) {
  1190. if (emu->card_capabilities->ca0108_chip) {
  1191. /* Note:JCD:No longer bit shift lower 16bits to upper 16bits of 32bit value. */
  1192. A_OP(icode, &ptr, iMACINT0, A_GPR(tmp), A_C_00000000, A3_EMU32IN(0x0), A_C_00000001);
  1193. A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_GPR(tmp));
  1194. A_OP(icode, &ptr, iMACINT0, A_GPR(tmp), A_C_00000000, A3_EMU32IN(0x1), A_C_00000001);
  1195. A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr), A_GPR(tmp));
  1196. } else {
  1197. A_OP(icode, &ptr, iMAC0, A_GPR(capture+0), A_GPR(capture+0), A_GPR(gpr), A_P16VIN(0x0));
  1198. A_OP(icode, &ptr, iMAC0, A_GPR(capture+1), A_GPR(capture+1), A_GPR(gpr+1), A_P16VIN(0x1));
  1199. }
  1200. snd_emu10k1_init_stereo_control(&controls[nctl++], "EMU Capture Volume", gpr, 0);
  1201. gpr += 2;
  1202. }
  1203. /* AC'97 Playback Volume - used only for mic (renamed later) */
  1204. A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AC97_L);
  1205. A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AC97_R);
  1206. snd_emu10k1_init_stereo_control(&controls[nctl++], "AMic Playback Volume", gpr, 0);
  1207. gpr += 2;
  1208. /* AC'97 Capture Volume - used only for mic */
  1209. A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AC97_L);
  1210. A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AC97_R);
  1211. snd_emu10k1_init_stereo_control(&controls[nctl++], "Mic Capture Volume", gpr, 0);
  1212. gpr += 2;
  1213. /* mic capture buffer */
  1214. A_OP(icode, &ptr, iINTERP, A_EXTOUT(A_EXTOUT_MIC_CAP), A_EXTIN(A_EXTIN_AC97_L), 0xcd, A_EXTIN(A_EXTIN_AC97_R));
  1215. /* Audigy CD Playback Volume */
  1216. A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_SPDIF_CD_L);
  1217. A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_SPDIF_CD_R);
  1218. snd_emu10k1_init_stereo_control(&controls[nctl++],
  1219. emu->card_capabilities->ac97_chip ? "Audigy CD Playback Volume" : "CD Playback Volume",
  1220. gpr, 0);
  1221. gpr += 2;
  1222. /* Audigy CD Capture Volume */
  1223. A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_SPDIF_CD_L);
  1224. A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_SPDIF_CD_R);
  1225. snd_emu10k1_init_stereo_control(&controls[nctl++],
  1226. emu->card_capabilities->ac97_chip ? "Audigy CD Capture Volume" : "CD Capture Volume",
  1227. gpr, 0);
  1228. gpr += 2;
  1229. /* Optical SPDIF Playback Volume */
  1230. A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_OPT_SPDIF_L);
  1231. A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_OPT_SPDIF_R);
  1232. snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",PLAYBACK,VOLUME), gpr, 0);
  1233. gpr += 2;
  1234. /* Optical SPDIF Capture Volume */
  1235. A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_OPT_SPDIF_L);
  1236. A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_OPT_SPDIF_R);
  1237. snd_emu10k1_init_stereo_control(&controls[nctl++], SNDRV_CTL_NAME_IEC958("Optical ",CAPTURE,VOLUME), gpr, 0);
  1238. gpr += 2;
  1239. /* Line2 Playback Volume */
  1240. A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_LINE2_L);
  1241. A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_LINE2_R);
  1242. snd_emu10k1_init_stereo_control(&controls[nctl++],
  1243. emu->card_capabilities->ac97_chip ? "Line2 Playback Volume" : "Line Playback Volume",
  1244. gpr, 0);
  1245. gpr += 2;
  1246. /* Line2 Capture Volume */
  1247. A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_LINE2_L);
  1248. A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_LINE2_R);
  1249. snd_emu10k1_init_stereo_control(&controls[nctl++],
  1250. emu->card_capabilities->ac97_chip ? "Line2 Capture Volume" : "Line Capture Volume",
  1251. gpr, 0);
  1252. gpr += 2;
  1253. /* Philips ADC Playback Volume */
  1254. A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_ADC_L);
  1255. A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_ADC_R);
  1256. snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Playback Volume", gpr, 0);
  1257. gpr += 2;
  1258. /* Philips ADC Capture Volume */
  1259. A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_ADC_L);
  1260. A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_ADC_R);
  1261. snd_emu10k1_init_stereo_control(&controls[nctl++], "Analog Mix Capture Volume", gpr, 0);
  1262. gpr += 2;
  1263. /* Aux2 Playback Volume */
  1264. A_ADD_VOLUME_IN(stereo_mix, gpr, A_EXTIN_AUX2_L);
  1265. A_ADD_VOLUME_IN(stereo_mix+1, gpr+1, A_EXTIN_AUX2_R);
  1266. snd_emu10k1_init_stereo_control(&controls[nctl++],
  1267. emu->card_capabilities->ac97_chip ? "Aux2 Playback Volume" : "Aux Playback Volume",
  1268. gpr, 0);
  1269. gpr += 2;
  1270. /* Aux2 Capture Volume */
  1271. A_ADD_VOLUME_IN(capture, gpr, A_EXTIN_AUX2_L);
  1272. A_ADD_VOLUME_IN(capture+1, gpr+1, A_EXTIN_AUX2_R);
  1273. snd_emu10k1_init_stereo_control(&controls[nctl++],
  1274. emu->card_capabilities->ac97_chip ? "Aux2 Capture Volume" : "Aux Capture Volume",
  1275. gpr, 0);
  1276. gpr += 2;
  1277. /* Stereo Mix Front Playback Volume */
  1278. A_OP(icode, &ptr, iMAC0, A_GPR(playback), A_GPR(playback), A_GPR(gpr), A_GPR(stereo_mix));
  1279. A_OP(icode, &ptr, iMAC0, A_GPR(playback+1), A_GPR(playback+1), A_GPR(gpr+1), A_GPR(stereo_mix+1));
  1280. snd_emu10k1_init_stereo_control(&controls[nctl++], "Front Playback Volume", gpr, 100);
  1281. gpr += 2;
  1282. /* Stereo Mix Surround Playback */
  1283. A_OP(icode, &ptr, iMAC0, A_GPR(playback+2), A_GPR(playback+2), A_GPR(gpr), A_GPR(stereo_mix));
  1284. A_OP(icode, &ptr, iMAC0, A_GPR(playback+3), A_GPR(playback+3), A_GPR(gpr+1), A_GPR(stereo_mix+1));
  1285. snd_emu10k1_init_stereo_control(&controls[nctl++], "Surround Playback Volume", gpr, 0);
  1286. gpr += 2;
  1287. /* Stereo Mix Center Playback */
  1288. /* Center = sub = Left/2 + Right/2 */
  1289. A_OP(icode, &ptr, iINTERP, A_GPR(tmp), A_GPR(stereo_mix), 0xcd, A_GPR(stereo_mix+1));
  1290. A_OP(icode, &ptr, iMAC0, A_GPR(playback+4), A_GPR(playback+4), A_GPR(gpr), A_GPR(tmp));
  1291. snd_emu10k1_init_mono_control(&controls[nctl++], "Center Playback Volume", gpr, 0);
  1292. gpr++;
  1293. /* Stereo Mix LFE Playback */
  1294. A_OP(icode, &ptr, iMAC0, A_GPR(playback+5), A_GPR(playback+5), A_GPR(gpr), A_GPR(tmp));
  1295. snd_emu10k1_init_mono_control(&controls[nctl++], "LFE Playback Volume", gpr, 0);
  1296. gpr++;
  1297. if (emu->card_capabilities->spk71) {
  1298. /* Stereo Mix Side Playback */
  1299. A_OP(icode, &ptr, iMAC0, A_GPR(playback+6), A_GPR(playback+6), A_GPR(gpr), A_GPR(stereo_mix));
  1300. A_OP(icode, &ptr, iMAC0, A_GPR(playback+7), A_GPR(playback+7), A_GPR(gpr+1), A_GPR(stereo_mix+1));
  1301. snd_emu10k1_init_stereo_control(&controls[nctl++], "Side Playback Volume", gpr, 0);
  1302. gpr += 2;
  1303. }
  1304. /*
  1305. * outputs
  1306. */
  1307. #define A_PUT_OUTPUT(out,src) A_OP(icode, &ptr, iACC3, A_EXTOUT(out), A_C_00000000, A_C_00000000, A_GPR(src))
  1308. #define A_PUT_STEREO_OUTPUT(out1,out2,src) \
  1309. {A_PUT_OUTPUT(out1,src); A_PUT_OUTPUT(out2,src+1);}
  1310. #define _A_SWITCH(icode, ptr, dst, src, sw) \
  1311. A_OP((icode), ptr, iMACINT0, dst, A_C_00000000, src, sw);
  1312. #define A_SWITCH(icode, ptr, dst, src, sw) \
  1313. _A_SWITCH(icode, ptr, A_GPR(dst), A_GPR(src), A_GPR(sw))
  1314. #define _A_SWITCH_NEG(icode, ptr, dst, src) \
  1315. A_OP((icode), ptr, iANDXOR, dst, src, A_C_00000001, A_C_00000001);
  1316. #define A_SWITCH_NEG(icode, ptr, dst, src) \
  1317. _A_SWITCH_NEG(icode, ptr, A_GPR(dst), A_GPR(src))
  1318. /*
  1319. * Process tone control
  1320. */
  1321. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), A_GPR(playback + 0), A_C_00000000, A_C_00000000); /* left */
  1322. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), A_GPR(playback + 1), A_C_00000000, A_C_00000000); /* right */
  1323. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2), A_GPR(playback + 2), A_C_00000000, A_C_00000000); /* rear left */
  1324. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 3), A_GPR(playback + 3), A_C_00000000, A_C_00000000); /* rear right */
  1325. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), A_GPR(playback + 4), A_C_00000000, A_C_00000000); /* center */
  1326. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), A_GPR(playback + 5), A_C_00000000, A_C_00000000); /* LFE */
  1327. if (emu->card_capabilities->spk71) {
  1328. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 6), A_GPR(playback + 6), A_C_00000000, A_C_00000000); /* side left */
  1329. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 7), A_GPR(playback + 7), A_C_00000000, A_C_00000000); /* side right */
  1330. }
  1331. ctl = &controls[nctl + 0];
  1332. ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  1333. strcpy(ctl->id.name, "Tone Control - Bass");
  1334. ctl->vcount = 2;
  1335. ctl->count = 10;
  1336. ctl->min = 0;
  1337. ctl->max = 40;
  1338. ctl->value[0] = ctl->value[1] = 20;
  1339. ctl->translation = EMU10K1_GPR_TRANSLATION_BASS;
  1340. ctl = &controls[nctl + 1];
  1341. ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  1342. strcpy(ctl->id.name, "Tone Control - Treble");
  1343. ctl->vcount = 2;
  1344. ctl->count = 10;
  1345. ctl->min = 0;
  1346. ctl->max = 40;
  1347. ctl->value[0] = ctl->value[1] = 20;
  1348. ctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE;
  1349. #define BASS_GPR 0x8c
  1350. #define TREBLE_GPR 0x96
  1351. for (z = 0; z < 5; z++) {
  1352. int j;
  1353. for (j = 0; j < 2; j++) {
  1354. controls[nctl + 0].gpr[z * 2 + j] = BASS_GPR + z * 2 + j;
  1355. controls[nctl + 1].gpr[z * 2 + j] = TREBLE_GPR + z * 2 + j;
  1356. }
  1357. }
  1358. for (z = 0; z < 4; z++) { /* front/rear/center-lfe/side */
  1359. int j, k, l, d;
  1360. for (j = 0; j < 2; j++) { /* left/right */
  1361. k = 0xb0 + (z * 8) + (j * 4);
  1362. l = 0xe0 + (z * 8) + (j * 4);
  1363. d = playback + SND_EMU10K1_PLAYBACK_CHANNELS + z * 2 + j;
  1364. A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(d), A_GPR(BASS_GPR + 0 + j));
  1365. A_OP(icode, &ptr, iMACMV, A_GPR(k+1), A_GPR(k), A_GPR(k+1), A_GPR(BASS_GPR + 4 + j));
  1366. A_OP(icode, &ptr, iMACMV, A_GPR(k), A_GPR(d), A_GPR(k), A_GPR(BASS_GPR + 2 + j));
  1367. A_OP(icode, &ptr, iMACMV, A_GPR(k+3), A_GPR(k+2), A_GPR(k+3), A_GPR(BASS_GPR + 8 + j));
  1368. A_OP(icode, &ptr, iMAC0, A_GPR(k+2), A_GPR_ACCU, A_GPR(k+2), A_GPR(BASS_GPR + 6 + j));
  1369. A_OP(icode, &ptr, iACC3, A_GPR(k+2), A_GPR(k+2), A_GPR(k+2), A_C_00000000);
  1370. A_OP(icode, &ptr, iMAC0, A_C_00000000, A_C_00000000, A_GPR(k+2), A_GPR(TREBLE_GPR + 0 + j));
  1371. A_OP(icode, &ptr, iMACMV, A_GPR(l+1), A_GPR(l), A_GPR(l+1), A_GPR(TREBLE_GPR + 4 + j));
  1372. A_OP(icode, &ptr, iMACMV, A_GPR(l), A_GPR(k+2), A_GPR(l), A_GPR(TREBLE_GPR + 2 + j));
  1373. A_OP(icode, &ptr, iMACMV, A_GPR(l+3), A_GPR(l+2), A_GPR(l+3), A_GPR(TREBLE_GPR + 8 + j));
  1374. A_OP(icode, &ptr, iMAC0, A_GPR(l+2), A_GPR_ACCU, A_GPR(l+2), A_GPR(TREBLE_GPR + 6 + j));
  1375. A_OP(icode, &ptr, iMACINT0, A_GPR(l+2), A_C_00000000, A_GPR(l+2), A_C_00000010);
  1376. A_OP(icode, &ptr, iACC3, A_GPR(d), A_GPR(l+2), A_C_00000000, A_C_00000000);
  1377. if (z == 2) /* center */
  1378. break;
  1379. }
  1380. }
  1381. nctl += 2;
  1382. #undef BASS_GPR
  1383. #undef TREBLE_GPR
  1384. for (z = 0; z < 8; z++) {
  1385. A_SWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, gpr + 0);
  1386. A_SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 0);
  1387. A_SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1);
  1388. A_OP(icode, &ptr, iACC3, A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000);
  1389. }
  1390. snd_emu10k1_init_stereo_onoff_control(controls + nctl++, "Tone Control - Switch", gpr, 0);
  1391. gpr += 2;
  1392. /* Master volume (will be renamed later) */
  1393. A_OP(icode, &ptr, iMAC0, A_GPR(playback+0+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+0+SND_EMU10K1_PLAYBACK_CHANNELS));
  1394. A_OP(icode, &ptr, iMAC0, A_GPR(playback+1+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+1+SND_EMU10K1_PLAYBACK_CHANNELS));
  1395. A_OP(icode, &ptr, iMAC0, A_GPR(playback+2+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+2+SND_EMU10K1_PLAYBACK_CHANNELS));
  1396. A_OP(icode, &ptr, iMAC0, A_GPR(playback+3+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+3+SND_EMU10K1_PLAYBACK_CHANNELS));
  1397. A_OP(icode, &ptr, iMAC0, A_GPR(playback+4+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+4+SND_EMU10K1_PLAYBACK_CHANNELS));
  1398. A_OP(icode, &ptr, iMAC0, A_GPR(playback+5+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+5+SND_EMU10K1_PLAYBACK_CHANNELS));
  1399. A_OP(icode, &ptr, iMAC0, A_GPR(playback+6+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+6+SND_EMU10K1_PLAYBACK_CHANNELS));
  1400. A_OP(icode, &ptr, iMAC0, A_GPR(playback+7+SND_EMU10K1_PLAYBACK_CHANNELS), A_C_00000000, A_GPR(gpr), A_GPR(playback+7+SND_EMU10K1_PLAYBACK_CHANNELS));
  1401. snd_emu10k1_init_mono_control(&controls[nctl++], "Wave Master Playback Volume", gpr, 0);
  1402. gpr += 2;
  1403. /* analog speakers */
  1404. A_PUT_STEREO_OUTPUT(A_EXTOUT_AFRONT_L, A_EXTOUT_AFRONT_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS);
  1405. A_PUT_STEREO_OUTPUT(A_EXTOUT_AREAR_L, A_EXTOUT_AREAR_R, playback+2 + SND_EMU10K1_PLAYBACK_CHANNELS);
  1406. A_PUT_OUTPUT(A_EXTOUT_ACENTER, playback+4 + SND_EMU10K1_PLAYBACK_CHANNELS);
  1407. A_PUT_OUTPUT(A_EXTOUT_ALFE, playback+5 + SND_EMU10K1_PLAYBACK_CHANNELS);
  1408. if (emu->card_capabilities->spk71)
  1409. A_PUT_STEREO_OUTPUT(A_EXTOUT_ASIDE_L, A_EXTOUT_ASIDE_R, playback+6 + SND_EMU10K1_PLAYBACK_CHANNELS);
  1410. /* headphone */
  1411. A_PUT_STEREO_OUTPUT(A_EXTOUT_HEADPHONE_L, A_EXTOUT_HEADPHONE_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS);
  1412. /* digital outputs */
  1413. /* A_PUT_STEREO_OUTPUT(A_EXTOUT_FRONT_L, A_EXTOUT_FRONT_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS); */
  1414. if (emu->card_capabilities->emu_model) {
  1415. /* EMU1010 Outputs from PCM Front, Rear, Center, LFE, Side */
  1416. dev_info(emu->card->dev, "EMU outputs on\n");
  1417. for (z = 0; z < 8; z++) {
  1418. if (emu->card_capabilities->ca0108_chip) {
  1419. A_OP(icode, &ptr, iACC3, A3_EMU32OUT(z), A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), A_C_00000000, A_C_00000000);
  1420. } else {
  1421. A_OP(icode, &ptr, iACC3, A_EMU32OUTL(z), A_GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), A_C_00000000, A_C_00000000);
  1422. }
  1423. }
  1424. }
  1425. /* IEC958 Optical Raw Playback Switch */
  1426. gpr_map[gpr++] = 0;
  1427. gpr_map[gpr++] = 0x1008;
  1428. gpr_map[gpr++] = 0xffff0000;
  1429. for (z = 0; z < 2; z++) {
  1430. A_OP(icode, &ptr, iMAC0, A_GPR(tmp + 2), A_FXBUS(FXBUS_PT_LEFT + z), A_C_00000000, A_C_00000000);
  1431. A_OP(icode, &ptr, iSKIP, A_GPR_COND, A_GPR_COND, A_GPR(gpr - 2), A_C_00000001);
  1432. A_OP(icode, &ptr, iACC3, A_GPR(tmp + 2), A_C_00000000, A_C_00010000, A_GPR(tmp + 2));
  1433. A_OP(icode, &ptr, iANDXOR, A_GPR(tmp + 2), A_GPR(tmp + 2), A_GPR(gpr - 1), A_C_00000000);
  1434. A_SWITCH(icode, &ptr, tmp + 0, tmp + 2, gpr + z);
  1435. A_SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z);
  1436. A_SWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, tmp + 1);
  1437. if ((z==1) && (emu->card_capabilities->spdif_bug)) {
  1438. /* Due to a SPDIF output bug on some Audigy cards, this code delays the Right channel by 1 sample */
  1439. dev_info(emu->card->dev,
  1440. "Installing spdif_bug patch: %s\n",
  1441. emu->card_capabilities->name);
  1442. A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(gpr - 3), A_C_00000000, A_C_00000000);
  1443. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 3), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000);
  1444. } else {
  1445. A_OP(icode, &ptr, iACC3, A_EXTOUT(A_EXTOUT_FRONT_L + z), A_GPR(tmp + 0), A_GPR(tmp + 1), A_C_00000000);
  1446. }
  1447. }
  1448. snd_emu10k1_init_stereo_onoff_control(controls + nctl++, SNDRV_CTL_NAME_IEC958("Optical Raw ",PLAYBACK,SWITCH), gpr, 0);
  1449. gpr += 2;
  1450. A_PUT_STEREO_OUTPUT(A_EXTOUT_REAR_L, A_EXTOUT_REAR_R, playback+2 + SND_EMU10K1_PLAYBACK_CHANNELS);
  1451. A_PUT_OUTPUT(A_EXTOUT_CENTER, playback+4 + SND_EMU10K1_PLAYBACK_CHANNELS);
  1452. A_PUT_OUTPUT(A_EXTOUT_LFE, playback+5 + SND_EMU10K1_PLAYBACK_CHANNELS);
  1453. /* ADC buffer */
  1454. #ifdef EMU10K1_CAPTURE_DIGITAL_OUT
  1455. A_PUT_STEREO_OUTPUT(A_EXTOUT_ADC_CAP_L, A_EXTOUT_ADC_CAP_R, playback + SND_EMU10K1_PLAYBACK_CHANNELS);
  1456. #else
  1457. A_PUT_OUTPUT(A_EXTOUT_ADC_CAP_L, capture);
  1458. A_PUT_OUTPUT(A_EXTOUT_ADC_CAP_R, capture+1);
  1459. #endif
  1460. if (emu->card_capabilities->emu_model) {
  1461. if (emu->card_capabilities->ca0108_chip) {
  1462. dev_info(emu->card->dev, "EMU2 inputs on\n");
  1463. for (z = 0; z < 0x10; z++) {
  1464. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp,
  1465. bit_shifter16,
  1466. A3_EMU32IN(z),
  1467. A_FXBUS2(z*2) );
  1468. }
  1469. } else {
  1470. dev_info(emu->card->dev, "EMU inputs on\n");
  1471. /* Capture 16 (originally 8) channels of S32_LE sound */
  1472. /*
  1473. dev_dbg(emu->card->dev, "emufx.c: gpr=0x%x, tmp=0x%x\n",
  1474. gpr, tmp);
  1475. */
  1476. /* For the EMU1010: How to get 32bit values from the DSP. High 16bits into L, low 16bits into R. */
  1477. /* A_P16VIN(0) is delayed by one sample,
  1478. * so all other A_P16VIN channels will need to also be delayed
  1479. */
  1480. /* Left ADC in. 1 of 2 */
  1481. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_P16VIN(0x0), A_FXBUS2(0) );
  1482. /* Right ADC in 1 of 2 */
  1483. gpr_map[gpr++] = 0x00000000;
  1484. /* Delaying by one sample: instead of copying the input
  1485. * value A_P16VIN to output A_FXBUS2 as in the first channel,
  1486. * we use an auxiliary register, delaying the value by one
  1487. * sample
  1488. */
  1489. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(2) );
  1490. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x1), A_C_00000000, A_C_00000000);
  1491. gpr_map[gpr++] = 0x00000000;
  1492. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(4) );
  1493. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x2), A_C_00000000, A_C_00000000);
  1494. gpr_map[gpr++] = 0x00000000;
  1495. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(6) );
  1496. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x3), A_C_00000000, A_C_00000000);
  1497. /* For 96kHz mode */
  1498. /* Left ADC in. 2 of 2 */
  1499. gpr_map[gpr++] = 0x00000000;
  1500. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0x8) );
  1501. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x4), A_C_00000000, A_C_00000000);
  1502. /* Right ADC in 2 of 2 */
  1503. gpr_map[gpr++] = 0x00000000;
  1504. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xa) );
  1505. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x5), A_C_00000000, A_C_00000000);
  1506. gpr_map[gpr++] = 0x00000000;
  1507. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xc) );
  1508. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x6), A_C_00000000, A_C_00000000);
  1509. gpr_map[gpr++] = 0x00000000;
  1510. snd_emu10k1_audigy_dsp_convert_32_to_2x16( icode, &ptr, tmp, bit_shifter16, A_GPR(gpr - 1), A_FXBUS2(0xe) );
  1511. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x7), A_C_00000000, A_C_00000000);
  1512. /* Pavel Hofman - we still have voices, A_FXBUS2s, and
  1513. * A_P16VINs available -
  1514. * let's add 8 more capture channels - total of 16
  1515. */
  1516. gpr_map[gpr++] = 0x00000000;
  1517. snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
  1518. bit_shifter16,
  1519. A_GPR(gpr - 1),
  1520. A_FXBUS2(0x10));
  1521. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x8),
  1522. A_C_00000000, A_C_00000000);
  1523. gpr_map[gpr++] = 0x00000000;
  1524. snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
  1525. bit_shifter16,
  1526. A_GPR(gpr - 1),
  1527. A_FXBUS2(0x12));
  1528. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0x9),
  1529. A_C_00000000, A_C_00000000);
  1530. gpr_map[gpr++] = 0x00000000;
  1531. snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
  1532. bit_shifter16,
  1533. A_GPR(gpr - 1),
  1534. A_FXBUS2(0x14));
  1535. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xa),
  1536. A_C_00000000, A_C_00000000);
  1537. gpr_map[gpr++] = 0x00000000;
  1538. snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
  1539. bit_shifter16,
  1540. A_GPR(gpr - 1),
  1541. A_FXBUS2(0x16));
  1542. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xb),
  1543. A_C_00000000, A_C_00000000);
  1544. gpr_map[gpr++] = 0x00000000;
  1545. snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
  1546. bit_shifter16,
  1547. A_GPR(gpr - 1),
  1548. A_FXBUS2(0x18));
  1549. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xc),
  1550. A_C_00000000, A_C_00000000);
  1551. gpr_map[gpr++] = 0x00000000;
  1552. snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
  1553. bit_shifter16,
  1554. A_GPR(gpr - 1),
  1555. A_FXBUS2(0x1a));
  1556. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xd),
  1557. A_C_00000000, A_C_00000000);
  1558. gpr_map[gpr++] = 0x00000000;
  1559. snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
  1560. bit_shifter16,
  1561. A_GPR(gpr - 1),
  1562. A_FXBUS2(0x1c));
  1563. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xe),
  1564. A_C_00000000, A_C_00000000);
  1565. gpr_map[gpr++] = 0x00000000;
  1566. snd_emu10k1_audigy_dsp_convert_32_to_2x16(icode, &ptr, tmp,
  1567. bit_shifter16,
  1568. A_GPR(gpr - 1),
  1569. A_FXBUS2(0x1e));
  1570. A_OP(icode, &ptr, iACC3, A_GPR(gpr - 1), A_P16VIN(0xf),
  1571. A_C_00000000, A_C_00000000);
  1572. }
  1573. #if 0
  1574. for (z = 4; z < 8; z++) {
  1575. A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_C_00000000);
  1576. }
  1577. for (z = 0xc; z < 0x10; z++) {
  1578. A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_C_00000000);
  1579. }
  1580. #endif
  1581. } else {
  1582. /* EFX capture - capture the 16 EXTINs */
  1583. /* Capture 16 channels of S16_LE sound */
  1584. for (z = 0; z < 16; z++) {
  1585. A_OP(icode, &ptr, iACC3, A_FXBUS2(z), A_C_00000000, A_C_00000000, A_EXTIN(z));
  1586. }
  1587. }
  1588. #endif /* JCD test */
  1589. /*
  1590. * ok, set up done..
  1591. */
  1592. if (gpr > tmp) {
  1593. snd_BUG();
  1594. err = -EIO;
  1595. goto __err;
  1596. }
  1597. /* clear remaining instruction memory */
  1598. while (ptr < 0x400)
  1599. A_OP(icode, &ptr, 0x0f, 0xc0, 0xc0, 0xcf, 0xc0);
  1600. seg = snd_enter_user();
  1601. icode->gpr_add_control_count = nctl;
  1602. icode->gpr_add_controls = (struct snd_emu10k1_fx8010_control_gpr __user *)controls;
  1603. emu->support_tlv = 1; /* support TLV */
  1604. err = snd_emu10k1_icode_poke(emu, icode);
  1605. emu->support_tlv = 0; /* clear again */
  1606. snd_leave_user(seg);
  1607. __err:
  1608. kfree(controls);
  1609. __err_ctrls:
  1610. kfree((void __force *)icode->gpr_map);
  1611. __err_gpr:
  1612. kfree(icode);
  1613. return err;
  1614. }
  1615. /*
  1616. * initial DSP configuration for Emu10k1
  1617. */
  1618. /* when volume = max, then copy only to avoid volume modification */
  1619. /* with iMAC0 (negative values) */
  1620. static void _volume(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol)
  1621. {
  1622. OP(icode, ptr, iMAC0, dst, C_00000000, src, vol);
  1623. OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff);
  1624. OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000001);
  1625. OP(icode, ptr, iACC3, dst, src, C_00000000, C_00000000);
  1626. }
  1627. static void _volume_add(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol)
  1628. {
  1629. OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff);
  1630. OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002);
  1631. OP(icode, ptr, iMACINT0, dst, dst, src, C_00000001);
  1632. OP(icode, ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000001);
  1633. OP(icode, ptr, iMAC0, dst, dst, src, vol);
  1634. }
  1635. static void _volume_out(struct snd_emu10k1_fx8010_code *icode, u32 *ptr, u32 dst, u32 src, u32 vol)
  1636. {
  1637. OP(icode, ptr, iANDXOR, C_00000000, vol, C_ffffffff, C_7fffffff);
  1638. OP(icode, ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002);
  1639. OP(icode, ptr, iACC3, dst, src, C_00000000, C_00000000);
  1640. OP(icode, ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000001);
  1641. OP(icode, ptr, iMAC0, dst, C_00000000, src, vol);
  1642. }
  1643. #define VOLUME(icode, ptr, dst, src, vol) \
  1644. _volume(icode, ptr, GPR(dst), GPR(src), GPR(vol))
  1645. #define VOLUME_IN(icode, ptr, dst, src, vol) \
  1646. _volume(icode, ptr, GPR(dst), EXTIN(src), GPR(vol))
  1647. #define VOLUME_ADD(icode, ptr, dst, src, vol) \
  1648. _volume_add(icode, ptr, GPR(dst), GPR(src), GPR(vol))
  1649. #define VOLUME_ADDIN(icode, ptr, dst, src, vol) \
  1650. _volume_add(icode, ptr, GPR(dst), EXTIN(src), GPR(vol))
  1651. #define VOLUME_OUT(icode, ptr, dst, src, vol) \
  1652. _volume_out(icode, ptr, EXTOUT(dst), GPR(src), GPR(vol))
  1653. #define _SWITCH(icode, ptr, dst, src, sw) \
  1654. OP((icode), ptr, iMACINT0, dst, C_00000000, src, sw);
  1655. #define SWITCH(icode, ptr, dst, src, sw) \
  1656. _SWITCH(icode, ptr, GPR(dst), GPR(src), GPR(sw))
  1657. #define SWITCH_IN(icode, ptr, dst, src, sw) \
  1658. _SWITCH(icode, ptr, GPR(dst), EXTIN(src), GPR(sw))
  1659. #define _SWITCH_NEG(icode, ptr, dst, src) \
  1660. OP((icode), ptr, iANDXOR, dst, src, C_00000001, C_00000001);
  1661. #define SWITCH_NEG(icode, ptr, dst, src) \
  1662. _SWITCH_NEG(icode, ptr, GPR(dst), GPR(src))
  1663. static int _snd_emu10k1_init_efx(struct snd_emu10k1 *emu)
  1664. {
  1665. int err, i, z, gpr, tmp, playback, capture;
  1666. u32 ptr;
  1667. struct snd_emu10k1_fx8010_code *icode;
  1668. struct snd_emu10k1_fx8010_pcm_rec *ipcm = NULL;
  1669. struct snd_emu10k1_fx8010_control_gpr *controls = NULL, *ctl;
  1670. u32 *gpr_map;
  1671. mm_segment_t seg;
  1672. err = -ENOMEM;
  1673. icode = kzalloc(sizeof(*icode), GFP_KERNEL);
  1674. if (!icode)
  1675. return err;
  1676. icode->gpr_map = (u_int32_t __user *) kcalloc(256 + 160 + 160 + 2 * 512,
  1677. sizeof(u_int32_t), GFP_KERNEL);
  1678. if (!icode->gpr_map)
  1679. goto __err_gpr;
  1680. controls = kcalloc(SND_EMU10K1_GPR_CONTROLS,
  1681. sizeof(struct snd_emu10k1_fx8010_control_gpr),
  1682. GFP_KERNEL);
  1683. if (!controls)
  1684. goto __err_ctrls;
  1685. ipcm = kzalloc(sizeof(*ipcm), GFP_KERNEL);
  1686. if (!ipcm)
  1687. goto __err_ipcm;
  1688. gpr_map = (u32 __force *)icode->gpr_map;
  1689. icode->tram_data_map = icode->gpr_map + 256;
  1690. icode->tram_addr_map = icode->tram_data_map + 160;
  1691. icode->code = icode->tram_addr_map + 160;
  1692. /* clear free GPRs */
  1693. for (i = 0; i < 256; i++)
  1694. set_bit(i, icode->gpr_valid);
  1695. /* clear TRAM data & address lines */
  1696. for (i = 0; i < 160; i++)
  1697. set_bit(i, icode->tram_valid);
  1698. strcpy(icode->name, "SB Live! FX8010 code for ALSA v1.2 by Jaroslav Kysela");
  1699. ptr = 0; i = 0;
  1700. /* we have 12 inputs */
  1701. playback = SND_EMU10K1_INPUTS;
  1702. /* we have 6 playback channels and tone control doubles */
  1703. capture = playback + (SND_EMU10K1_PLAYBACK_CHANNELS * 2);
  1704. gpr = capture + SND_EMU10K1_CAPTURE_CHANNELS;
  1705. tmp = 0x88; /* we need 4 temporary GPR */
  1706. /* from 0x8c to 0xff is the area for tone control */
  1707. /* stop FX processor */
  1708. snd_emu10k1_ptr_write(emu, DBG, 0, (emu->fx8010.dbg = 0) | EMU10K1_DBG_SINGLE_STEP);
  1709. /*
  1710. * Process FX Buses
  1711. */
  1712. OP(icode, &ptr, iMACINT0, GPR(0), C_00000000, FXBUS(FXBUS_PCM_LEFT), C_00000004);
  1713. OP(icode, &ptr, iMACINT0, GPR(1), C_00000000, FXBUS(FXBUS_PCM_RIGHT), C_00000004);
  1714. OP(icode, &ptr, iMACINT0, GPR(2), C_00000000, FXBUS(FXBUS_MIDI_LEFT), C_00000004);
  1715. OP(icode, &ptr, iMACINT0, GPR(3), C_00000000, FXBUS(FXBUS_MIDI_RIGHT), C_00000004);
  1716. OP(icode, &ptr, iMACINT0, GPR(4), C_00000000, FXBUS(FXBUS_PCM_LEFT_REAR), C_00000004);
  1717. OP(icode, &ptr, iMACINT0, GPR(5), C_00000000, FXBUS(FXBUS_PCM_RIGHT_REAR), C_00000004);
  1718. OP(icode, &ptr, iMACINT0, GPR(6), C_00000000, FXBUS(FXBUS_PCM_CENTER), C_00000004);
  1719. OP(icode, &ptr, iMACINT0, GPR(7), C_00000000, FXBUS(FXBUS_PCM_LFE), C_00000004);
  1720. OP(icode, &ptr, iMACINT0, GPR(8), C_00000000, C_00000000, C_00000000); /* S/PDIF left */
  1721. OP(icode, &ptr, iMACINT0, GPR(9), C_00000000, C_00000000, C_00000000); /* S/PDIF right */
  1722. OP(icode, &ptr, iMACINT0, GPR(10), C_00000000, FXBUS(FXBUS_PCM_LEFT_FRONT), C_00000004);
  1723. OP(icode, &ptr, iMACINT0, GPR(11), C_00000000, FXBUS(FXBUS_PCM_RIGHT_FRONT), C_00000004);
  1724. /* Raw S/PDIF PCM */
  1725. ipcm->substream = 0;
  1726. ipcm->channels = 2;
  1727. ipcm->tram_start = 0;
  1728. ipcm->buffer_size = (64 * 1024) / 2;
  1729. ipcm->gpr_size = gpr++;
  1730. ipcm->gpr_ptr = gpr++;
  1731. ipcm->gpr_count = gpr++;
  1732. ipcm->gpr_tmpcount = gpr++;
  1733. ipcm->gpr_trigger = gpr++;
  1734. ipcm->gpr_running = gpr++;
  1735. ipcm->etram[0] = 0;
  1736. ipcm->etram[1] = 1;
  1737. gpr_map[gpr + 0] = 0xfffff000;
  1738. gpr_map[gpr + 1] = 0xffff0000;
  1739. gpr_map[gpr + 2] = 0x70000000;
  1740. gpr_map[gpr + 3] = 0x00000007;
  1741. gpr_map[gpr + 4] = 0x001f << 11;
  1742. gpr_map[gpr + 5] = 0x001c << 11;
  1743. gpr_map[gpr + 6] = (0x22 - 0x01) - 1; /* skip at 01 to 22 */
  1744. gpr_map[gpr + 7] = (0x22 - 0x06) - 1; /* skip at 06 to 22 */
  1745. gpr_map[gpr + 8] = 0x2000000 + (2<<11);
  1746. gpr_map[gpr + 9] = 0x4000000 + (2<<11);
  1747. gpr_map[gpr + 10] = 1<<11;
  1748. gpr_map[gpr + 11] = (0x24 - 0x0a) - 1; /* skip at 0a to 24 */
  1749. gpr_map[gpr + 12] = 0;
  1750. /* if the trigger flag is not set, skip */
  1751. /* 00: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_trigger), C_00000000, C_00000000);
  1752. /* 01: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_ZERO, GPR(gpr + 6));
  1753. /* if the running flag is set, we're running */
  1754. /* 02: */ OP(icode, &ptr, iMAC0, C_00000000, GPR(ipcm->gpr_running), C_00000000, C_00000000);
  1755. /* 03: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000004);
  1756. /* wait until ((GPR_DBAC>>11) & 0x1f) == 0x1c) */
  1757. /* 04: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), GPR_DBAC, GPR(gpr + 4), C_00000000);
  1758. /* 05: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(gpr + 5));
  1759. /* 06: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 7));
  1760. /* 07: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000010, C_00000001, C_00000000);
  1761. /* 08: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000000, C_00000001);
  1762. /* 09: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), GPR(gpr + 12), C_ffffffff, C_00000000);
  1763. /* 0a: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, GPR(gpr + 11));
  1764. /* 0b: */ OP(icode, &ptr, iACC3, GPR(gpr + 12), C_00000001, C_00000000, C_00000000);
  1765. /* 0c: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[0]), GPR(gpr + 0), C_00000000);
  1766. /* 0d: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000);
  1767. /* 0e: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2));
  1768. /* 0f: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001);
  1769. /* 10: */ OP(icode, &ptr, iANDXOR, GPR(8), GPR(8), GPR(gpr + 1), GPR(gpr + 2));
  1770. /* 11: */ OP(icode, &ptr, iANDXOR, GPR(tmp + 0), ETRAM_DATA(ipcm->etram[1]), GPR(gpr + 0), C_00000000);
  1771. /* 12: */ OP(icode, &ptr, iLOG, GPR(tmp + 0), GPR(tmp + 0), GPR(gpr + 3), C_00000000);
  1772. /* 13: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(tmp + 0), GPR(gpr + 1), GPR(gpr + 2));
  1773. /* 14: */ OP(icode, &ptr, iSKIP, C_00000000, GPR_COND, CC_REG_MINUS, C_00000001);
  1774. /* 15: */ OP(icode, &ptr, iANDXOR, GPR(9), GPR(9), GPR(gpr + 1), GPR(gpr + 2));
  1775. /* 16: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(ipcm->gpr_ptr), C_00000001, C_00000000);
  1776. /* 17: */ OP(icode, &ptr, iMACINT0, C_00000000, GPR(tmp + 0), C_ffffffff, GPR(ipcm->gpr_size));
  1777. /* 18: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_MINUS, C_00000001);
  1778. /* 19: */ OP(icode, &ptr, iACC3, GPR(tmp + 0), C_00000000, C_00000000, C_00000000);
  1779. /* 1a: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_ptr), GPR(tmp + 0), C_00000000, C_00000000);
  1780. /* 1b: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_tmpcount), C_ffffffff, C_00000000);
  1781. /* 1c: */ OP(icode, &ptr, iSKIP, GPR_COND, GPR_COND, CC_REG_NONZERO, C_00000002);
  1782. /* 1d: */ OP(icode, &ptr, iACC3, GPR(ipcm->gpr_tmpcount), GPR(ipcm->gpr_count), C_00000000, C_00000000);
  1783. /* 1e: */ OP(icode, &ptr, iACC3, GPR_IRQ, C_80000000, C_00000000, C_00000000);
  1784. /* 1f: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00000001, C_00010000);
  1785. /* 20: */ OP(icode, &ptr, iANDXOR, GPR(ipcm->gpr_running), GPR(ipcm->gpr_running), C_00010000, C_00000001);
  1786. /* 21: */ OP(icode, &ptr, iSKIP, C_00000000, C_7fffffff, C_7fffffff, C_00000002);
  1787. /* 22: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[0]), GPR(gpr + 8), GPR_DBAC, C_ffffffff);
  1788. /* 23: */ OP(icode, &ptr, iMACINT1, ETRAM_ADDR(ipcm->etram[1]), GPR(gpr + 9), GPR_DBAC, C_ffffffff);
  1789. /* 24: */
  1790. gpr += 13;
  1791. /* Wave Playback Volume */
  1792. for (z = 0; z < 2; z++)
  1793. VOLUME(icode, &ptr, playback + z, z, gpr + z);
  1794. snd_emu10k1_init_stereo_control(controls + i++, "Wave Playback Volume", gpr, 100);
  1795. gpr += 2;
  1796. /* Wave Surround Playback Volume */
  1797. for (z = 0; z < 2; z++)
  1798. VOLUME(icode, &ptr, playback + 2 + z, z, gpr + z);
  1799. snd_emu10k1_init_stereo_control(controls + i++, "Wave Surround Playback Volume", gpr, 0);
  1800. gpr += 2;
  1801. /* Wave Center/LFE Playback Volume */
  1802. OP(icode, &ptr, iACC3, GPR(tmp + 0), FXBUS(FXBUS_PCM_LEFT), FXBUS(FXBUS_PCM_RIGHT), C_00000000);
  1803. OP(icode, &ptr, iMACINT0, GPR(tmp + 0), C_00000000, GPR(tmp + 0), C_00000002);
  1804. VOLUME(icode, &ptr, playback + 4, tmp + 0, gpr);
  1805. snd_emu10k1_init_mono_control(controls + i++, "Wave Center Playback Volume", gpr++, 0);
  1806. VOLUME(icode, &ptr, playback + 5, tmp + 0, gpr);
  1807. snd_emu10k1_init_mono_control(controls + i++, "Wave LFE Playback Volume", gpr++, 0);
  1808. /* Wave Capture Volume + Switch */
  1809. for (z = 0; z < 2; z++) {
  1810. SWITCH(icode, &ptr, tmp + 0, z, gpr + 2 + z);
  1811. VOLUME(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1812. }
  1813. snd_emu10k1_init_stereo_control(controls + i++, "Wave Capture Volume", gpr, 0);
  1814. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Wave Capture Switch", gpr + 2, 0);
  1815. gpr += 4;
  1816. /* Synth Playback Volume */
  1817. for (z = 0; z < 2; z++)
  1818. VOLUME_ADD(icode, &ptr, playback + z, 2 + z, gpr + z);
  1819. snd_emu10k1_init_stereo_control(controls + i++, "Synth Playback Volume", gpr, 100);
  1820. gpr += 2;
  1821. /* Synth Capture Volume + Switch */
  1822. for (z = 0; z < 2; z++) {
  1823. SWITCH(icode, &ptr, tmp + 0, 2 + z, gpr + 2 + z);
  1824. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1825. }
  1826. snd_emu10k1_init_stereo_control(controls + i++, "Synth Capture Volume", gpr, 0);
  1827. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Synth Capture Switch", gpr + 2, 0);
  1828. gpr += 4;
  1829. /* Surround Digital Playback Volume (renamed later without Digital) */
  1830. for (z = 0; z < 2; z++)
  1831. VOLUME_ADD(icode, &ptr, playback + 2 + z, 4 + z, gpr + z);
  1832. snd_emu10k1_init_stereo_control(controls + i++, "Surround Digital Playback Volume", gpr, 100);
  1833. gpr += 2;
  1834. /* Surround Capture Volume + Switch */
  1835. for (z = 0; z < 2; z++) {
  1836. SWITCH(icode, &ptr, tmp + 0, 4 + z, gpr + 2 + z);
  1837. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1838. }
  1839. snd_emu10k1_init_stereo_control(controls + i++, "Surround Capture Volume", gpr, 0);
  1840. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Surround Capture Switch", gpr + 2, 0);
  1841. gpr += 4;
  1842. /* Center Playback Volume (renamed later without Digital) */
  1843. VOLUME_ADD(icode, &ptr, playback + 4, 6, gpr);
  1844. snd_emu10k1_init_mono_control(controls + i++, "Center Digital Playback Volume", gpr++, 100);
  1845. /* LFE Playback Volume + Switch (renamed later without Digital) */
  1846. VOLUME_ADD(icode, &ptr, playback + 5, 7, gpr);
  1847. snd_emu10k1_init_mono_control(controls + i++, "LFE Digital Playback Volume", gpr++, 100);
  1848. /* Front Playback Volume */
  1849. for (z = 0; z < 2; z++)
  1850. VOLUME_ADD(icode, &ptr, playback + z, 10 + z, gpr + z);
  1851. snd_emu10k1_init_stereo_control(controls + i++, "Front Playback Volume", gpr, 100);
  1852. gpr += 2;
  1853. /* Front Capture Volume + Switch */
  1854. for (z = 0; z < 2; z++) {
  1855. SWITCH(icode, &ptr, tmp + 0, 10 + z, gpr + 2);
  1856. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1857. }
  1858. snd_emu10k1_init_stereo_control(controls + i++, "Front Capture Volume", gpr, 0);
  1859. snd_emu10k1_init_mono_onoff_control(controls + i++, "Front Capture Switch", gpr + 2, 0);
  1860. gpr += 3;
  1861. /*
  1862. * Process inputs
  1863. */
  1864. if (emu->fx8010.extin_mask & ((1<<EXTIN_AC97_L)|(1<<EXTIN_AC97_R))) {
  1865. /* AC'97 Playback Volume */
  1866. VOLUME_ADDIN(icode, &ptr, playback + 0, EXTIN_AC97_L, gpr); gpr++;
  1867. VOLUME_ADDIN(icode, &ptr, playback + 1, EXTIN_AC97_R, gpr); gpr++;
  1868. snd_emu10k1_init_stereo_control(controls + i++, "AC97 Playback Volume", gpr-2, 0);
  1869. /* AC'97 Capture Volume */
  1870. VOLUME_ADDIN(icode, &ptr, capture + 0, EXTIN_AC97_L, gpr); gpr++;
  1871. VOLUME_ADDIN(icode, &ptr, capture + 1, EXTIN_AC97_R, gpr); gpr++;
  1872. snd_emu10k1_init_stereo_control(controls + i++, "AC97 Capture Volume", gpr-2, 100);
  1873. }
  1874. if (emu->fx8010.extin_mask & ((1<<EXTIN_SPDIF_CD_L)|(1<<EXTIN_SPDIF_CD_R))) {
  1875. /* IEC958 TTL Playback Volume */
  1876. for (z = 0; z < 2; z++)
  1877. VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_SPDIF_CD_L + z, gpr + z);
  1878. snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",PLAYBACK,VOLUME), gpr, 0);
  1879. gpr += 2;
  1880. /* IEC958 TTL Capture Volume + Switch */
  1881. for (z = 0; z < 2; z++) {
  1882. SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_SPDIF_CD_L + z, gpr + 2 + z);
  1883. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1884. }
  1885. snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",CAPTURE,VOLUME), gpr, 0);
  1886. snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("TTL ",CAPTURE,SWITCH), gpr + 2, 0);
  1887. gpr += 4;
  1888. }
  1889. if (emu->fx8010.extin_mask & ((1<<EXTIN_ZOOM_L)|(1<<EXTIN_ZOOM_R))) {
  1890. /* Zoom Video Playback Volume */
  1891. for (z = 0; z < 2; z++)
  1892. VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_ZOOM_L + z, gpr + z);
  1893. snd_emu10k1_init_stereo_control(controls + i++, "Zoom Video Playback Volume", gpr, 0);
  1894. gpr += 2;
  1895. /* Zoom Video Capture Volume + Switch */
  1896. for (z = 0; z < 2; z++) {
  1897. SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_ZOOM_L + z, gpr + 2 + z);
  1898. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1899. }
  1900. snd_emu10k1_init_stereo_control(controls + i++, "Zoom Video Capture Volume", gpr, 0);
  1901. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Zoom Video Capture Switch", gpr + 2, 0);
  1902. gpr += 4;
  1903. }
  1904. if (emu->fx8010.extin_mask & ((1<<EXTIN_TOSLINK_L)|(1<<EXTIN_TOSLINK_R))) {
  1905. /* IEC958 Optical Playback Volume */
  1906. for (z = 0; z < 2; z++)
  1907. VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_TOSLINK_L + z, gpr + z);
  1908. snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",PLAYBACK,VOLUME), gpr, 0);
  1909. gpr += 2;
  1910. /* IEC958 Optical Capture Volume */
  1911. for (z = 0; z < 2; z++) {
  1912. SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_TOSLINK_L + z, gpr + 2 + z);
  1913. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1914. }
  1915. snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",CAPTURE,VOLUME), gpr, 0);
  1916. snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("LiveDrive ",CAPTURE,SWITCH), gpr + 2, 0);
  1917. gpr += 4;
  1918. }
  1919. if (emu->fx8010.extin_mask & ((1<<EXTIN_LINE1_L)|(1<<EXTIN_LINE1_R))) {
  1920. /* Line LiveDrive Playback Volume */
  1921. for (z = 0; z < 2; z++)
  1922. VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_LINE1_L + z, gpr + z);
  1923. snd_emu10k1_init_stereo_control(controls + i++, "Line LiveDrive Playback Volume", gpr, 0);
  1924. gpr += 2;
  1925. /* Line LiveDrive Capture Volume + Switch */
  1926. for (z = 0; z < 2; z++) {
  1927. SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_LINE1_L + z, gpr + 2 + z);
  1928. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1929. }
  1930. snd_emu10k1_init_stereo_control(controls + i++, "Line LiveDrive Capture Volume", gpr, 0);
  1931. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Line LiveDrive Capture Switch", gpr + 2, 0);
  1932. gpr += 4;
  1933. }
  1934. if (emu->fx8010.extin_mask & ((1<<EXTIN_COAX_SPDIF_L)|(1<<EXTIN_COAX_SPDIF_R))) {
  1935. /* IEC958 Coax Playback Volume */
  1936. for (z = 0; z < 2; z++)
  1937. VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_COAX_SPDIF_L + z, gpr + z);
  1938. snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",PLAYBACK,VOLUME), gpr, 0);
  1939. gpr += 2;
  1940. /* IEC958 Coax Capture Volume + Switch */
  1941. for (z = 0; z < 2; z++) {
  1942. SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_COAX_SPDIF_L + z, gpr + 2 + z);
  1943. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1944. }
  1945. snd_emu10k1_init_stereo_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",CAPTURE,VOLUME), gpr, 0);
  1946. snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("Coaxial ",CAPTURE,SWITCH), gpr + 2, 0);
  1947. gpr += 4;
  1948. }
  1949. if (emu->fx8010.extin_mask & ((1<<EXTIN_LINE2_L)|(1<<EXTIN_LINE2_R))) {
  1950. /* Line LiveDrive Playback Volume */
  1951. for (z = 0; z < 2; z++)
  1952. VOLUME_ADDIN(icode, &ptr, playback + z, EXTIN_LINE2_L + z, gpr + z);
  1953. snd_emu10k1_init_stereo_control(controls + i++, "Line2 LiveDrive Playback Volume", gpr, 0);
  1954. controls[i-1].id.index = 1;
  1955. gpr += 2;
  1956. /* Line LiveDrive Capture Volume */
  1957. for (z = 0; z < 2; z++) {
  1958. SWITCH_IN(icode, &ptr, tmp + 0, EXTIN_LINE2_L + z, gpr + 2 + z);
  1959. VOLUME_ADD(icode, &ptr, capture + z, tmp + 0, gpr + z);
  1960. }
  1961. snd_emu10k1_init_stereo_control(controls + i++, "Line2 LiveDrive Capture Volume", gpr, 0);
  1962. controls[i-1].id.index = 1;
  1963. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Line2 LiveDrive Capture Switch", gpr + 2, 0);
  1964. controls[i-1].id.index = 1;
  1965. gpr += 4;
  1966. }
  1967. /*
  1968. * Process tone control
  1969. */
  1970. OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), GPR(playback + 0), C_00000000, C_00000000); /* left */
  1971. OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), GPR(playback + 1), C_00000000, C_00000000); /* right */
  1972. OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2), GPR(playback + 2), C_00000000, C_00000000); /* rear left */
  1973. OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 3), GPR(playback + 3), C_00000000, C_00000000); /* rear right */
  1974. OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), GPR(playback + 4), C_00000000, C_00000000); /* center */
  1975. OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), GPR(playback + 5), C_00000000, C_00000000); /* LFE */
  1976. ctl = &controls[i + 0];
  1977. ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  1978. strcpy(ctl->id.name, "Tone Control - Bass");
  1979. ctl->vcount = 2;
  1980. ctl->count = 10;
  1981. ctl->min = 0;
  1982. ctl->max = 40;
  1983. ctl->value[0] = ctl->value[1] = 20;
  1984. ctl->tlv = snd_emu10k1_bass_treble_db_scale;
  1985. ctl->translation = EMU10K1_GPR_TRANSLATION_BASS;
  1986. ctl = &controls[i + 1];
  1987. ctl->id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  1988. strcpy(ctl->id.name, "Tone Control - Treble");
  1989. ctl->vcount = 2;
  1990. ctl->count = 10;
  1991. ctl->min = 0;
  1992. ctl->max = 40;
  1993. ctl->value[0] = ctl->value[1] = 20;
  1994. ctl->tlv = snd_emu10k1_bass_treble_db_scale;
  1995. ctl->translation = EMU10K1_GPR_TRANSLATION_TREBLE;
  1996. #define BASS_GPR 0x8c
  1997. #define TREBLE_GPR 0x96
  1998. for (z = 0; z < 5; z++) {
  1999. int j;
  2000. for (j = 0; j < 2; j++) {
  2001. controls[i + 0].gpr[z * 2 + j] = BASS_GPR + z * 2 + j;
  2002. controls[i + 1].gpr[z * 2 + j] = TREBLE_GPR + z * 2 + j;
  2003. }
  2004. }
  2005. for (z = 0; z < 3; z++) { /* front/rear/center-lfe */
  2006. int j, k, l, d;
  2007. for (j = 0; j < 2; j++) { /* left/right */
  2008. k = 0xa0 + (z * 8) + (j * 4);
  2009. l = 0xd0 + (z * 8) + (j * 4);
  2010. d = playback + SND_EMU10K1_PLAYBACK_CHANNELS + z * 2 + j;
  2011. OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(d), GPR(BASS_GPR + 0 + j));
  2012. OP(icode, &ptr, iMACMV, GPR(k+1), GPR(k), GPR(k+1), GPR(BASS_GPR + 4 + j));
  2013. OP(icode, &ptr, iMACMV, GPR(k), GPR(d), GPR(k), GPR(BASS_GPR + 2 + j));
  2014. OP(icode, &ptr, iMACMV, GPR(k+3), GPR(k+2), GPR(k+3), GPR(BASS_GPR + 8 + j));
  2015. OP(icode, &ptr, iMAC0, GPR(k+2), GPR_ACCU, GPR(k+2), GPR(BASS_GPR + 6 + j));
  2016. OP(icode, &ptr, iACC3, GPR(k+2), GPR(k+2), GPR(k+2), C_00000000);
  2017. OP(icode, &ptr, iMAC0, C_00000000, C_00000000, GPR(k+2), GPR(TREBLE_GPR + 0 + j));
  2018. OP(icode, &ptr, iMACMV, GPR(l+1), GPR(l), GPR(l+1), GPR(TREBLE_GPR + 4 + j));
  2019. OP(icode, &ptr, iMACMV, GPR(l), GPR(k+2), GPR(l), GPR(TREBLE_GPR + 2 + j));
  2020. OP(icode, &ptr, iMACMV, GPR(l+3), GPR(l+2), GPR(l+3), GPR(TREBLE_GPR + 8 + j));
  2021. OP(icode, &ptr, iMAC0, GPR(l+2), GPR_ACCU, GPR(l+2), GPR(TREBLE_GPR + 6 + j));
  2022. OP(icode, &ptr, iMACINT0, GPR(l+2), C_00000000, GPR(l+2), C_00000010);
  2023. OP(icode, &ptr, iACC3, GPR(d), GPR(l+2), C_00000000, C_00000000);
  2024. if (z == 2) /* center */
  2025. break;
  2026. }
  2027. }
  2028. i += 2;
  2029. #undef BASS_GPR
  2030. #undef TREBLE_GPR
  2031. for (z = 0; z < 6; z++) {
  2032. SWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, gpr + 0);
  2033. SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 0);
  2034. SWITCH(icode, &ptr, tmp + 1, playback + z, tmp + 1);
  2035. OP(icode, &ptr, iACC3, GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
  2036. }
  2037. snd_emu10k1_init_stereo_onoff_control(controls + i++, "Tone Control - Switch", gpr, 0);
  2038. gpr += 2;
  2039. /*
  2040. * Process outputs
  2041. */
  2042. if (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_L)|(1<<EXTOUT_AC97_R))) {
  2043. /* AC'97 Playback Volume */
  2044. for (z = 0; z < 2; z++)
  2045. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + z), C_00000000, C_00000000);
  2046. }
  2047. if (emu->fx8010.extout_mask & ((1<<EXTOUT_TOSLINK_L)|(1<<EXTOUT_TOSLINK_R))) {
  2048. /* IEC958 Optical Raw Playback Switch */
  2049. for (z = 0; z < 2; z++) {
  2050. SWITCH(icode, &ptr, tmp + 0, 8 + z, gpr + z);
  2051. SWITCH_NEG(icode, &ptr, tmp + 1, gpr + z);
  2052. SWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, tmp + 1);
  2053. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_TOSLINK_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
  2054. #ifdef EMU10K1_CAPTURE_DIGITAL_OUT
  2055. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
  2056. #endif
  2057. }
  2058. snd_emu10k1_init_stereo_onoff_control(controls + i++, SNDRV_CTL_NAME_IEC958("Optical Raw ",PLAYBACK,SWITCH), gpr, 0);
  2059. gpr += 2;
  2060. }
  2061. if (emu->fx8010.extout_mask & ((1<<EXTOUT_HEADPHONE_L)|(1<<EXTOUT_HEADPHONE_R))) {
  2062. /* Headphone Playback Volume */
  2063. for (z = 0; z < 2; z++) {
  2064. SWITCH(icode, &ptr, tmp + 0, playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4 + z, gpr + 2 + z);
  2065. SWITCH_NEG(icode, &ptr, tmp + 1, gpr + 2 + z);
  2066. SWITCH(icode, &ptr, tmp + 1, playback + SND_EMU10K1_PLAYBACK_CHANNELS + z, tmp + 1);
  2067. OP(icode, &ptr, iACC3, GPR(tmp + 0), GPR(tmp + 0), GPR(tmp + 1), C_00000000);
  2068. VOLUME_OUT(icode, &ptr, EXTOUT_HEADPHONE_L + z, tmp + 0, gpr + z);
  2069. }
  2070. snd_emu10k1_init_stereo_control(controls + i++, "Headphone Playback Volume", gpr + 0, 0);
  2071. controls[i-1].id.index = 1; /* AC'97 can have also Headphone control */
  2072. snd_emu10k1_init_mono_onoff_control(controls + i++, "Headphone Center Playback Switch", gpr + 2, 0);
  2073. controls[i-1].id.index = 1;
  2074. snd_emu10k1_init_mono_onoff_control(controls + i++, "Headphone LFE Playback Switch", gpr + 3, 0);
  2075. controls[i-1].id.index = 1;
  2076. gpr += 4;
  2077. }
  2078. if (emu->fx8010.extout_mask & ((1<<EXTOUT_REAR_L)|(1<<EXTOUT_REAR_R)))
  2079. for (z = 0; z < 2; z++)
  2080. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_REAR_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2 + z), C_00000000, C_00000000);
  2081. if (emu->fx8010.extout_mask & ((1<<EXTOUT_AC97_REAR_L)|(1<<EXTOUT_AC97_REAR_R)))
  2082. for (z = 0; z < 2; z++)
  2083. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_REAR_L + z), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 2 + z), C_00000000, C_00000000);
  2084. if (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_CENTER)) {
  2085. #ifndef EMU10K1_CENTER_LFE_FROM_FRONT
  2086. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), C_00000000, C_00000000);
  2087. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 4), C_00000000, C_00000000);
  2088. #else
  2089. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_CENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), C_00000000, C_00000000);
  2090. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ACENTER), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 0), C_00000000, C_00000000);
  2091. #endif
  2092. }
  2093. if (emu->fx8010.extout_mask & (1<<EXTOUT_AC97_LFE)) {
  2094. #ifndef EMU10K1_CENTER_LFE_FROM_FRONT
  2095. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), C_00000000, C_00000000);
  2096. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 5), C_00000000, C_00000000);
  2097. #else
  2098. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_AC97_LFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), C_00000000, C_00000000);
  2099. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ALFE), GPR(playback + SND_EMU10K1_PLAYBACK_CHANNELS + 1), C_00000000, C_00000000);
  2100. #endif
  2101. }
  2102. #ifndef EMU10K1_CAPTURE_DIGITAL_OUT
  2103. for (z = 0; z < 2; z++)
  2104. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_ADC_CAP_L + z), GPR(capture + z), C_00000000, C_00000000);
  2105. #endif
  2106. if (emu->fx8010.extout_mask & (1<<EXTOUT_MIC_CAP))
  2107. OP(icode, &ptr, iACC3, EXTOUT(EXTOUT_MIC_CAP), GPR(capture + 2), C_00000000, C_00000000);
  2108. /* EFX capture - capture the 16 EXTINS */
  2109. if (emu->card_capabilities->sblive51) {
  2110. /* On the Live! 5.1, FXBUS2(1) and FXBUS(2) are shared with EXTOUT_ACENTER
  2111. * and EXTOUT_ALFE, so we can't connect inputs to them for multitrack recording.
  2112. *
  2113. * Since only 14 of the 16 EXTINs are used, this is not a big problem.
  2114. * We route AC97L and R to FX capture 14 and 15, SPDIF CD in to FX capture
  2115. * 0 and 3, then the rest of the EXTINs to the corresponding FX capture
  2116. * channel. Multitrack recorders will still see the center/lfe output signal
  2117. * on the second and third channels.
  2118. */
  2119. OP(icode, &ptr, iACC3, FXBUS2(14), C_00000000, C_00000000, EXTIN(0));
  2120. OP(icode, &ptr, iACC3, FXBUS2(15), C_00000000, C_00000000, EXTIN(1));
  2121. OP(icode, &ptr, iACC3, FXBUS2(0), C_00000000, C_00000000, EXTIN(2));
  2122. OP(icode, &ptr, iACC3, FXBUS2(3), C_00000000, C_00000000, EXTIN(3));
  2123. for (z = 4; z < 14; z++)
  2124. OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(z));
  2125. } else {
  2126. for (z = 0; z < 16; z++)
  2127. OP(icode, &ptr, iACC3, FXBUS2(z), C_00000000, C_00000000, EXTIN(z));
  2128. }
  2129. if (gpr > tmp) {
  2130. snd_BUG();
  2131. err = -EIO;
  2132. goto __err;
  2133. }
  2134. if (i > SND_EMU10K1_GPR_CONTROLS) {
  2135. snd_BUG();
  2136. err = -EIO;
  2137. goto __err;
  2138. }
  2139. /* clear remaining instruction memory */
  2140. while (ptr < 0x200)
  2141. OP(icode, &ptr, iACC3, C_00000000, C_00000000, C_00000000, C_00000000);
  2142. if ((err = snd_emu10k1_fx8010_tram_setup(emu, ipcm->buffer_size)) < 0)
  2143. goto __err;
  2144. seg = snd_enter_user();
  2145. icode->gpr_add_control_count = i;
  2146. icode->gpr_add_controls = (struct snd_emu10k1_fx8010_control_gpr __user *)controls;
  2147. emu->support_tlv = 1; /* support TLV */
  2148. err = snd_emu10k1_icode_poke(emu, icode);
  2149. emu->support_tlv = 0; /* clear again */
  2150. snd_leave_user(seg);
  2151. if (err >= 0)
  2152. err = snd_emu10k1_ipcm_poke(emu, ipcm);
  2153. __err:
  2154. kfree(ipcm);
  2155. __err_ipcm:
  2156. kfree(controls);
  2157. __err_ctrls:
  2158. kfree((void __force *)icode->gpr_map);
  2159. __err_gpr:
  2160. kfree(icode);
  2161. return err;
  2162. }
  2163. int snd_emu10k1_init_efx(struct snd_emu10k1 *emu)
  2164. {
  2165. spin_lock_init(&emu->fx8010.irq_lock);
  2166. INIT_LIST_HEAD(&emu->fx8010.gpr_ctl);
  2167. if (emu->audigy)
  2168. return _snd_emu10k1_audigy_init_efx(emu);
  2169. else
  2170. return _snd_emu10k1_init_efx(emu);
  2171. }
  2172. void snd_emu10k1_free_efx(struct snd_emu10k1 *emu)
  2173. {
  2174. /* stop processor */
  2175. if (emu->audigy)
  2176. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg = A_DBG_SINGLE_STEP);
  2177. else
  2178. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg = EMU10K1_DBG_SINGLE_STEP);
  2179. }
  2180. #if 0 /* FIXME: who use them? */
  2181. int snd_emu10k1_fx8010_tone_control_activate(struct snd_emu10k1 *emu, int output)
  2182. {
  2183. if (output < 0 || output >= 6)
  2184. return -EINVAL;
  2185. snd_emu10k1_ptr_write(emu, emu->gpr_base + 0x94 + output, 0, 1);
  2186. return 0;
  2187. }
  2188. int snd_emu10k1_fx8010_tone_control_deactivate(struct snd_emu10k1 *emu, int output)
  2189. {
  2190. if (output < 0 || output >= 6)
  2191. return -EINVAL;
  2192. snd_emu10k1_ptr_write(emu, emu->gpr_base + 0x94 + output, 0, 0);
  2193. return 0;
  2194. }
  2195. #endif
  2196. int snd_emu10k1_fx8010_tram_setup(struct snd_emu10k1 *emu, u32 size)
  2197. {
  2198. u8 size_reg = 0;
  2199. /* size is in samples */
  2200. if (size != 0) {
  2201. size = (size - 1) >> 13;
  2202. while (size) {
  2203. size >>= 1;
  2204. size_reg++;
  2205. }
  2206. size = 0x2000 << size_reg;
  2207. }
  2208. if ((emu->fx8010.etram_pages.bytes / 2) == size)
  2209. return 0;
  2210. spin_lock_irq(&emu->emu_lock);
  2211. outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG);
  2212. spin_unlock_irq(&emu->emu_lock);
  2213. snd_emu10k1_ptr_write(emu, TCB, 0, 0);
  2214. snd_emu10k1_ptr_write(emu, TCBS, 0, 0);
  2215. if (emu->fx8010.etram_pages.area != NULL) {
  2216. snd_dma_free_pages(&emu->fx8010.etram_pages);
  2217. emu->fx8010.etram_pages.area = NULL;
  2218. emu->fx8010.etram_pages.bytes = 0;
  2219. }
  2220. if (size > 0) {
  2221. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(emu->pci),
  2222. size * 2, &emu->fx8010.etram_pages) < 0)
  2223. return -ENOMEM;
  2224. memset(emu->fx8010.etram_pages.area, 0, size * 2);
  2225. snd_emu10k1_ptr_write(emu, TCB, 0, emu->fx8010.etram_pages.addr);
  2226. snd_emu10k1_ptr_write(emu, TCBS, 0, size_reg);
  2227. spin_lock_irq(&emu->emu_lock);
  2228. outl(inl(emu->port + HCFG) & ~HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG);
  2229. spin_unlock_irq(&emu->emu_lock);
  2230. }
  2231. return 0;
  2232. }
  2233. static int snd_emu10k1_fx8010_open(struct snd_hwdep * hw, struct file *file)
  2234. {
  2235. return 0;
  2236. }
  2237. static void copy_string(char *dst, char *src, char *null, int idx)
  2238. {
  2239. if (src == NULL)
  2240. sprintf(dst, "%s %02X", null, idx);
  2241. else
  2242. strcpy(dst, src);
  2243. }
  2244. static void snd_emu10k1_fx8010_info(struct snd_emu10k1 *emu,
  2245. struct snd_emu10k1_fx8010_info *info)
  2246. {
  2247. char **fxbus, **extin, **extout;
  2248. unsigned short fxbus_mask, extin_mask, extout_mask;
  2249. int res;
  2250. info->internal_tram_size = emu->fx8010.itram_size;
  2251. info->external_tram_size = emu->fx8010.etram_pages.bytes / 2;
  2252. fxbus = fxbuses;
  2253. extin = emu->audigy ? audigy_ins : creative_ins;
  2254. extout = emu->audigy ? audigy_outs : creative_outs;
  2255. fxbus_mask = emu->fx8010.fxbus_mask;
  2256. extin_mask = emu->fx8010.extin_mask;
  2257. extout_mask = emu->fx8010.extout_mask;
  2258. for (res = 0; res < 16; res++, fxbus++, extin++, extout++) {
  2259. copy_string(info->fxbus_names[res], fxbus_mask & (1 << res) ? *fxbus : NULL, "FXBUS", res);
  2260. copy_string(info->extin_names[res], extin_mask & (1 << res) ? *extin : NULL, "Unused", res);
  2261. copy_string(info->extout_names[res], extout_mask & (1 << res) ? *extout : NULL, "Unused", res);
  2262. }
  2263. for (res = 16; res < 32; res++, extout++)
  2264. copy_string(info->extout_names[res], extout_mask & (1 << res) ? *extout : NULL, "Unused", res);
  2265. info->gpr_controls = emu->fx8010.gpr_count;
  2266. }
  2267. static int snd_emu10k1_fx8010_ioctl(struct snd_hwdep * hw, struct file *file, unsigned int cmd, unsigned long arg)
  2268. {
  2269. struct snd_emu10k1 *emu = hw->private_data;
  2270. struct snd_emu10k1_fx8010_info *info;
  2271. struct snd_emu10k1_fx8010_code *icode;
  2272. struct snd_emu10k1_fx8010_pcm_rec *ipcm;
  2273. unsigned int addr;
  2274. void __user *argp = (void __user *)arg;
  2275. int res;
  2276. switch (cmd) {
  2277. case SNDRV_EMU10K1_IOCTL_PVERSION:
  2278. emu->support_tlv = 1;
  2279. return put_user(SNDRV_EMU10K1_VERSION, (int __user *)argp);
  2280. case SNDRV_EMU10K1_IOCTL_INFO:
  2281. info = kzalloc(sizeof(*info), GFP_KERNEL);
  2282. if (!info)
  2283. return -ENOMEM;
  2284. snd_emu10k1_fx8010_info(emu, info);
  2285. if (copy_to_user(argp, info, sizeof(*info))) {
  2286. kfree(info);
  2287. return -EFAULT;
  2288. }
  2289. kfree(info);
  2290. return 0;
  2291. case SNDRV_EMU10K1_IOCTL_CODE_POKE:
  2292. if (!capable(CAP_SYS_ADMIN))
  2293. return -EPERM;
  2294. icode = memdup_user(argp, sizeof(*icode));
  2295. if (IS_ERR(icode))
  2296. return PTR_ERR(icode);
  2297. res = snd_emu10k1_icode_poke(emu, icode);
  2298. kfree(icode);
  2299. return res;
  2300. case SNDRV_EMU10K1_IOCTL_CODE_PEEK:
  2301. icode = memdup_user(argp, sizeof(*icode));
  2302. if (IS_ERR(icode))
  2303. return PTR_ERR(icode);
  2304. res = snd_emu10k1_icode_peek(emu, icode);
  2305. if (res == 0 && copy_to_user(argp, icode, sizeof(*icode))) {
  2306. kfree(icode);
  2307. return -EFAULT;
  2308. }
  2309. kfree(icode);
  2310. return res;
  2311. case SNDRV_EMU10K1_IOCTL_PCM_POKE:
  2312. ipcm = memdup_user(argp, sizeof(*ipcm));
  2313. if (IS_ERR(ipcm))
  2314. return PTR_ERR(ipcm);
  2315. res = snd_emu10k1_ipcm_poke(emu, ipcm);
  2316. kfree(ipcm);
  2317. return res;
  2318. case SNDRV_EMU10K1_IOCTL_PCM_PEEK:
  2319. ipcm = memdup_user(argp, sizeof(*ipcm));
  2320. if (IS_ERR(ipcm))
  2321. return PTR_ERR(ipcm);
  2322. res = snd_emu10k1_ipcm_peek(emu, ipcm);
  2323. if (res == 0 && copy_to_user(argp, ipcm, sizeof(*ipcm))) {
  2324. kfree(ipcm);
  2325. return -EFAULT;
  2326. }
  2327. kfree(ipcm);
  2328. return res;
  2329. case SNDRV_EMU10K1_IOCTL_TRAM_SETUP:
  2330. if (!capable(CAP_SYS_ADMIN))
  2331. return -EPERM;
  2332. if (get_user(addr, (unsigned int __user *)argp))
  2333. return -EFAULT;
  2334. mutex_lock(&emu->fx8010.lock);
  2335. res = snd_emu10k1_fx8010_tram_setup(emu, addr);
  2336. mutex_unlock(&emu->fx8010.lock);
  2337. return res;
  2338. case SNDRV_EMU10K1_IOCTL_STOP:
  2339. if (!capable(CAP_SYS_ADMIN))
  2340. return -EPERM;
  2341. if (emu->audigy)
  2342. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP);
  2343. else
  2344. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP);
  2345. return 0;
  2346. case SNDRV_EMU10K1_IOCTL_CONTINUE:
  2347. if (!capable(CAP_SYS_ADMIN))
  2348. return -EPERM;
  2349. if (emu->audigy)
  2350. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg = 0);
  2351. else
  2352. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg = 0);
  2353. return 0;
  2354. case SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER:
  2355. if (!capable(CAP_SYS_ADMIN))
  2356. return -EPERM;
  2357. if (emu->audigy)
  2358. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_ZC);
  2359. else
  2360. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_ZC);
  2361. udelay(10);
  2362. if (emu->audigy)
  2363. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
  2364. else
  2365. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);
  2366. return 0;
  2367. case SNDRV_EMU10K1_IOCTL_SINGLE_STEP:
  2368. if (!capable(CAP_SYS_ADMIN))
  2369. return -EPERM;
  2370. if (get_user(addr, (unsigned int __user *)argp))
  2371. return -EFAULT;
  2372. if (addr > 0x1ff)
  2373. return -EINVAL;
  2374. if (emu->audigy)
  2375. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP | addr);
  2376. else
  2377. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP | addr);
  2378. udelay(10);
  2379. if (emu->audigy)
  2380. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg |= A_DBG_SINGLE_STEP | A_DBG_STEP_ADDR | addr);
  2381. else
  2382. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg |= EMU10K1_DBG_SINGLE_STEP | EMU10K1_DBG_STEP | addr);
  2383. return 0;
  2384. case SNDRV_EMU10K1_IOCTL_DBG_READ:
  2385. if (emu->audigy)
  2386. addr = snd_emu10k1_ptr_read(emu, A_DBG, 0);
  2387. else
  2388. addr = snd_emu10k1_ptr_read(emu, DBG, 0);
  2389. if (put_user(addr, (unsigned int __user *)argp))
  2390. return -EFAULT;
  2391. return 0;
  2392. }
  2393. return -ENOTTY;
  2394. }
  2395. static int snd_emu10k1_fx8010_release(struct snd_hwdep * hw, struct file *file)
  2396. {
  2397. return 0;
  2398. }
  2399. int snd_emu10k1_fx8010_new(struct snd_emu10k1 *emu, int device)
  2400. {
  2401. struct snd_hwdep *hw;
  2402. int err;
  2403. if ((err = snd_hwdep_new(emu->card, "FX8010", device, &hw)) < 0)
  2404. return err;
  2405. strcpy(hw->name, "EMU10K1 (FX8010)");
  2406. hw->iface = SNDRV_HWDEP_IFACE_EMU10K1;
  2407. hw->ops.open = snd_emu10k1_fx8010_open;
  2408. hw->ops.ioctl = snd_emu10k1_fx8010_ioctl;
  2409. hw->ops.release = snd_emu10k1_fx8010_release;
  2410. hw->private_data = emu;
  2411. return 0;
  2412. }
  2413. #ifdef CONFIG_PM_SLEEP
  2414. int snd_emu10k1_efx_alloc_pm_buffer(struct snd_emu10k1 *emu)
  2415. {
  2416. int len;
  2417. len = emu->audigy ? 0x200 : 0x100;
  2418. emu->saved_gpr = kmalloc(len * 4, GFP_KERNEL);
  2419. if (! emu->saved_gpr)
  2420. return -ENOMEM;
  2421. len = emu->audigy ? 0x100 : 0xa0;
  2422. emu->tram_val_saved = kmalloc(len * 4, GFP_KERNEL);
  2423. emu->tram_addr_saved = kmalloc(len * 4, GFP_KERNEL);
  2424. if (! emu->tram_val_saved || ! emu->tram_addr_saved)
  2425. return -ENOMEM;
  2426. len = emu->audigy ? 2 * 1024 : 2 * 512;
  2427. emu->saved_icode = vmalloc(len * 4);
  2428. if (! emu->saved_icode)
  2429. return -ENOMEM;
  2430. return 0;
  2431. }
  2432. void snd_emu10k1_efx_free_pm_buffer(struct snd_emu10k1 *emu)
  2433. {
  2434. kfree(emu->saved_gpr);
  2435. kfree(emu->tram_val_saved);
  2436. kfree(emu->tram_addr_saved);
  2437. vfree(emu->saved_icode);
  2438. }
  2439. /*
  2440. * save/restore GPR, TRAM and codes
  2441. */
  2442. void snd_emu10k1_efx_suspend(struct snd_emu10k1 *emu)
  2443. {
  2444. int i, len;
  2445. len = emu->audigy ? 0x200 : 0x100;
  2446. for (i = 0; i < len; i++)
  2447. emu->saved_gpr[i] = snd_emu10k1_ptr_read(emu, emu->gpr_base + i, 0);
  2448. len = emu->audigy ? 0x100 : 0xa0;
  2449. for (i = 0; i < len; i++) {
  2450. emu->tram_val_saved[i] = snd_emu10k1_ptr_read(emu, TANKMEMDATAREGBASE + i, 0);
  2451. emu->tram_addr_saved[i] = snd_emu10k1_ptr_read(emu, TANKMEMADDRREGBASE + i, 0);
  2452. if (emu->audigy) {
  2453. emu->tram_addr_saved[i] >>= 12;
  2454. emu->tram_addr_saved[i] |=
  2455. snd_emu10k1_ptr_read(emu, A_TANKMEMCTLREGBASE + i, 0) << 20;
  2456. }
  2457. }
  2458. len = emu->audigy ? 2 * 1024 : 2 * 512;
  2459. for (i = 0; i < len; i++)
  2460. emu->saved_icode[i] = snd_emu10k1_efx_read(emu, i);
  2461. }
  2462. void snd_emu10k1_efx_resume(struct snd_emu10k1 *emu)
  2463. {
  2464. int i, len;
  2465. /* set up TRAM */
  2466. if (emu->fx8010.etram_pages.bytes > 0) {
  2467. unsigned size, size_reg = 0;
  2468. size = emu->fx8010.etram_pages.bytes / 2;
  2469. size = (size - 1) >> 13;
  2470. while (size) {
  2471. size >>= 1;
  2472. size_reg++;
  2473. }
  2474. outl(HCFG_LOCKTANKCACHE_MASK | inl(emu->port + HCFG), emu->port + HCFG);
  2475. snd_emu10k1_ptr_write(emu, TCB, 0, emu->fx8010.etram_pages.addr);
  2476. snd_emu10k1_ptr_write(emu, TCBS, 0, size_reg);
  2477. outl(inl(emu->port + HCFG) & ~HCFG_LOCKTANKCACHE_MASK, emu->port + HCFG);
  2478. }
  2479. if (emu->audigy)
  2480. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg | A_DBG_SINGLE_STEP);
  2481. else
  2482. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg | EMU10K1_DBG_SINGLE_STEP);
  2483. len = emu->audigy ? 0x200 : 0x100;
  2484. for (i = 0; i < len; i++)
  2485. snd_emu10k1_ptr_write(emu, emu->gpr_base + i, 0, emu->saved_gpr[i]);
  2486. len = emu->audigy ? 0x100 : 0xa0;
  2487. for (i = 0; i < len; i++) {
  2488. snd_emu10k1_ptr_write(emu, TANKMEMDATAREGBASE + i, 0,
  2489. emu->tram_val_saved[i]);
  2490. if (! emu->audigy)
  2491. snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
  2492. emu->tram_addr_saved[i]);
  2493. else {
  2494. snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
  2495. emu->tram_addr_saved[i] << 12);
  2496. snd_emu10k1_ptr_write(emu, TANKMEMADDRREGBASE + i, 0,
  2497. emu->tram_addr_saved[i] >> 20);
  2498. }
  2499. }
  2500. len = emu->audigy ? 2 * 1024 : 2 * 512;
  2501. for (i = 0; i < len; i++)
  2502. snd_emu10k1_efx_write(emu, i, emu->saved_icode[i]);
  2503. /* start FX processor when the DSP code is updated */
  2504. if (emu->audigy)
  2505. snd_emu10k1_ptr_write(emu, A_DBG, 0, emu->fx8010.dbg);
  2506. else
  2507. snd_emu10k1_ptr_write(emu, DBG, 0, emu->fx8010.dbg);
  2508. }
  2509. #endif