patch_hdmi.c 99 KB

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  1. /*
  2. *
  3. * patch_hdmi.c - routines for HDMI/DisplayPort codecs
  4. *
  5. * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
  6. * Copyright (c) 2006 ATI Technologies Inc.
  7. * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
  8. * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
  9. * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
  10. *
  11. * Authors:
  12. * Wu Fengguang <wfg@linux.intel.com>
  13. *
  14. * Maintained by:
  15. * Wu Fengguang <wfg@linux.intel.com>
  16. *
  17. * This program is free software; you can redistribute it and/or modify it
  18. * under the terms of the GNU General Public License as published by the Free
  19. * Software Foundation; either version 2 of the License, or (at your option)
  20. * any later version.
  21. *
  22. * This program is distributed in the hope that it will be useful, but
  23. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  24. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  25. * for more details.
  26. *
  27. * You should have received a copy of the GNU General Public License
  28. * along with this program; if not, write to the Free Software Foundation,
  29. * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  30. */
  31. #include <linux/init.h>
  32. #include <linux/delay.h>
  33. #include <linux/slab.h>
  34. #include <linux/module.h>
  35. #include <sound/core.h>
  36. #include <sound/jack.h>
  37. #include <sound/asoundef.h>
  38. #include <sound/tlv.h>
  39. #include <sound/hdaudio.h>
  40. #include <sound/hda_i915.h>
  41. #include "hda_codec.h"
  42. #include "hda_local.h"
  43. #include "hda_jack.h"
  44. static bool static_hdmi_pcm;
  45. module_param(static_hdmi_pcm, bool, 0644);
  46. MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
  47. #define is_haswell(codec) ((codec)->core.vendor_id == 0x80862807)
  48. #define is_broadwell(codec) ((codec)->core.vendor_id == 0x80862808)
  49. #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
  50. #define is_broxton(codec) ((codec)->core.vendor_id == 0x8086280a)
  51. #define is_kabylake(codec) ((codec)->core.vendor_id == 0x8086280b)
  52. #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
  53. || is_skylake(codec) || is_broxton(codec) \
  54. || is_kabylake(codec))
  55. #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
  56. #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
  57. #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
  58. struct hdmi_spec_per_cvt {
  59. hda_nid_t cvt_nid;
  60. int assigned;
  61. unsigned int channels_min;
  62. unsigned int channels_max;
  63. u32 rates;
  64. u64 formats;
  65. unsigned int maxbps;
  66. };
  67. /* max. connections to a widget */
  68. #define HDA_MAX_CONNECTIONS 32
  69. struct hdmi_spec_per_pin {
  70. hda_nid_t pin_nid;
  71. int num_mux_nids;
  72. hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
  73. int mux_idx;
  74. hda_nid_t cvt_nid;
  75. struct hda_codec *codec;
  76. struct hdmi_eld sink_eld;
  77. struct mutex lock;
  78. struct delayed_work work;
  79. struct snd_kcontrol *eld_ctl;
  80. int repoll_count;
  81. bool setup; /* the stream has been set up by prepare callback */
  82. int channels; /* current number of channels */
  83. bool non_pcm;
  84. bool chmap_set; /* channel-map override by ALSA API? */
  85. unsigned char chmap[8]; /* ALSA API channel-map */
  86. #ifdef CONFIG_SND_PROC_FS
  87. struct snd_info_entry *proc_entry;
  88. #endif
  89. };
  90. struct cea_channel_speaker_allocation;
  91. /* operations used by generic code that can be overridden by patches */
  92. struct hdmi_ops {
  93. int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
  94. unsigned char *buf, int *eld_size);
  95. /* get and set channel assigned to each HDMI ASP (audio sample packet) slot */
  96. int (*pin_get_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
  97. int asp_slot);
  98. int (*pin_set_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
  99. int asp_slot, int channel);
  100. void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
  101. int ca, int active_channels, int conn_type);
  102. /* enable/disable HBR (HD passthrough) */
  103. int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
  104. int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
  105. hda_nid_t pin_nid, u32 stream_tag, int format);
  106. /* Helpers for producing the channel map TLVs. These can be overridden
  107. * for devices that have non-standard mapping requirements. */
  108. int (*chmap_cea_alloc_validate_get_type)(struct cea_channel_speaker_allocation *cap,
  109. int channels);
  110. void (*cea_alloc_to_tlv_chmap)(struct cea_channel_speaker_allocation *cap,
  111. unsigned int *chmap, int channels);
  112. /* check that the user-given chmap is supported */
  113. int (*chmap_validate)(int ca, int channels, unsigned char *chmap);
  114. };
  115. struct hdmi_spec {
  116. int num_cvts;
  117. struct snd_array cvts; /* struct hdmi_spec_per_cvt */
  118. hda_nid_t cvt_nids[4]; /* only for haswell fix */
  119. int num_pins;
  120. struct snd_array pins; /* struct hdmi_spec_per_pin */
  121. struct hda_pcm *pcm_rec[16];
  122. unsigned int channels_max; /* max over all cvts */
  123. struct hdmi_eld temp_eld;
  124. struct hdmi_ops ops;
  125. bool dyn_pin_out;
  126. /*
  127. * Non-generic VIA/NVIDIA specific
  128. */
  129. struct hda_multi_out multiout;
  130. struct hda_pcm_stream pcm_playback;
  131. /* i915/powerwell (Haswell+/Valleyview+) specific */
  132. struct i915_audio_component_audio_ops i915_audio_ops;
  133. };
  134. struct hdmi_audio_infoframe {
  135. u8 type; /* 0x84 */
  136. u8 ver; /* 0x01 */
  137. u8 len; /* 0x0a */
  138. u8 checksum;
  139. u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
  140. u8 SS01_SF24;
  141. u8 CXT04;
  142. u8 CA;
  143. u8 LFEPBL01_LSV36_DM_INH7;
  144. };
  145. struct dp_audio_infoframe {
  146. u8 type; /* 0x84 */
  147. u8 len; /* 0x1b */
  148. u8 ver; /* 0x11 << 2 */
  149. u8 CC02_CT47; /* match with HDMI infoframe from this on */
  150. u8 SS01_SF24;
  151. u8 CXT04;
  152. u8 CA;
  153. u8 LFEPBL01_LSV36_DM_INH7;
  154. };
  155. union audio_infoframe {
  156. struct hdmi_audio_infoframe hdmi;
  157. struct dp_audio_infoframe dp;
  158. u8 bytes[0];
  159. };
  160. /*
  161. * CEA speaker placement:
  162. *
  163. * FLH FCH FRH
  164. * FLW FL FLC FC FRC FR FRW
  165. *
  166. * LFE
  167. * TC
  168. *
  169. * RL RLC RC RRC RR
  170. *
  171. * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
  172. * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
  173. */
  174. enum cea_speaker_placement {
  175. FL = (1 << 0), /* Front Left */
  176. FC = (1 << 1), /* Front Center */
  177. FR = (1 << 2), /* Front Right */
  178. FLC = (1 << 3), /* Front Left Center */
  179. FRC = (1 << 4), /* Front Right Center */
  180. RL = (1 << 5), /* Rear Left */
  181. RC = (1 << 6), /* Rear Center */
  182. RR = (1 << 7), /* Rear Right */
  183. RLC = (1 << 8), /* Rear Left Center */
  184. RRC = (1 << 9), /* Rear Right Center */
  185. LFE = (1 << 10), /* Low Frequency Effect */
  186. FLW = (1 << 11), /* Front Left Wide */
  187. FRW = (1 << 12), /* Front Right Wide */
  188. FLH = (1 << 13), /* Front Left High */
  189. FCH = (1 << 14), /* Front Center High */
  190. FRH = (1 << 15), /* Front Right High */
  191. TC = (1 << 16), /* Top Center */
  192. };
  193. /*
  194. * ELD SA bits in the CEA Speaker Allocation data block
  195. */
  196. static int eld_speaker_allocation_bits[] = {
  197. [0] = FL | FR,
  198. [1] = LFE,
  199. [2] = FC,
  200. [3] = RL | RR,
  201. [4] = RC,
  202. [5] = FLC | FRC,
  203. [6] = RLC | RRC,
  204. /* the following are not defined in ELD yet */
  205. [7] = FLW | FRW,
  206. [8] = FLH | FRH,
  207. [9] = TC,
  208. [10] = FCH,
  209. };
  210. struct cea_channel_speaker_allocation {
  211. int ca_index;
  212. int speakers[8];
  213. /* derived values, just for convenience */
  214. int channels;
  215. int spk_mask;
  216. };
  217. /*
  218. * ALSA sequence is:
  219. *
  220. * surround40 surround41 surround50 surround51 surround71
  221. * ch0 front left = = = =
  222. * ch1 front right = = = =
  223. * ch2 rear left = = = =
  224. * ch3 rear right = = = =
  225. * ch4 LFE center center center
  226. * ch5 LFE LFE
  227. * ch6 side left
  228. * ch7 side right
  229. *
  230. * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
  231. */
  232. static int hdmi_channel_mapping[0x32][8] = {
  233. /* stereo */
  234. [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
  235. /* 2.1 */
  236. [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
  237. /* Dolby Surround */
  238. [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
  239. /* surround40 */
  240. [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
  241. /* 4ch */
  242. [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
  243. /* surround41 */
  244. [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
  245. /* surround50 */
  246. [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
  247. /* surround51 */
  248. [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
  249. /* 7.1 */
  250. [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
  251. };
  252. /*
  253. * This is an ordered list!
  254. *
  255. * The preceding ones have better chances to be selected by
  256. * hdmi_channel_allocation().
  257. */
  258. static struct cea_channel_speaker_allocation channel_allocations[] = {
  259. /* channel: 7 6 5 4 3 2 1 0 */
  260. { .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
  261. /* 2.1 */
  262. { .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
  263. /* Dolby Surround */
  264. { .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
  265. /* surround40 */
  266. { .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
  267. /* surround41 */
  268. { .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
  269. /* surround50 */
  270. { .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
  271. /* surround51 */
  272. { .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
  273. /* 6.1 */
  274. { .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
  275. /* surround71 */
  276. { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
  277. { .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
  278. { .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
  279. { .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
  280. { .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
  281. { .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
  282. { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
  283. { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
  284. { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
  285. { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
  286. { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
  287. { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
  288. { .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
  289. { .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
  290. { .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
  291. { .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
  292. { .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
  293. { .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
  294. { .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
  295. { .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
  296. { .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
  297. { .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
  298. { .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
  299. { .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
  300. { .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
  301. { .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
  302. { .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
  303. { .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
  304. { .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
  305. { .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
  306. { .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
  307. { .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
  308. { .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
  309. { .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
  310. { .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
  311. { .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
  312. { .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
  313. { .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
  314. { .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
  315. { .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
  316. { .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
  317. { .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
  318. };
  319. /*
  320. * HDMI routines
  321. */
  322. #define get_pin(spec, idx) \
  323. ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
  324. #define get_cvt(spec, idx) \
  325. ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx))
  326. #define get_pcm_rec(spec, idx) ((spec)->pcm_rec[idx])
  327. static int pin_nid_to_pin_index(struct hda_codec *codec, hda_nid_t pin_nid)
  328. {
  329. struct hdmi_spec *spec = codec->spec;
  330. int pin_idx;
  331. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
  332. if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
  333. return pin_idx;
  334. codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
  335. return -EINVAL;
  336. }
  337. static int hinfo_to_pin_index(struct hda_codec *codec,
  338. struct hda_pcm_stream *hinfo)
  339. {
  340. struct hdmi_spec *spec = codec->spec;
  341. int pin_idx;
  342. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
  343. if (get_pcm_rec(spec, pin_idx)->stream == hinfo)
  344. return pin_idx;
  345. codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
  346. return -EINVAL;
  347. }
  348. static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
  349. {
  350. struct hdmi_spec *spec = codec->spec;
  351. int cvt_idx;
  352. for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
  353. if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
  354. return cvt_idx;
  355. codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
  356. return -EINVAL;
  357. }
  358. static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
  359. struct snd_ctl_elem_info *uinfo)
  360. {
  361. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  362. struct hdmi_spec *spec = codec->spec;
  363. struct hdmi_spec_per_pin *per_pin;
  364. struct hdmi_eld *eld;
  365. int pin_idx;
  366. uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
  367. pin_idx = kcontrol->private_value;
  368. per_pin = get_pin(spec, pin_idx);
  369. eld = &per_pin->sink_eld;
  370. mutex_lock(&per_pin->lock);
  371. uinfo->count = eld->eld_valid ? eld->eld_size : 0;
  372. mutex_unlock(&per_pin->lock);
  373. return 0;
  374. }
  375. static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
  376. struct snd_ctl_elem_value *ucontrol)
  377. {
  378. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  379. struct hdmi_spec *spec = codec->spec;
  380. struct hdmi_spec_per_pin *per_pin;
  381. struct hdmi_eld *eld;
  382. int pin_idx;
  383. pin_idx = kcontrol->private_value;
  384. per_pin = get_pin(spec, pin_idx);
  385. eld = &per_pin->sink_eld;
  386. mutex_lock(&per_pin->lock);
  387. if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) ||
  388. eld->eld_size > ELD_MAX_SIZE) {
  389. mutex_unlock(&per_pin->lock);
  390. snd_BUG();
  391. return -EINVAL;
  392. }
  393. memset(ucontrol->value.bytes.data, 0,
  394. ARRAY_SIZE(ucontrol->value.bytes.data));
  395. if (eld->eld_valid)
  396. memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
  397. eld->eld_size);
  398. mutex_unlock(&per_pin->lock);
  399. return 0;
  400. }
  401. static struct snd_kcontrol_new eld_bytes_ctl = {
  402. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  403. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  404. .name = "ELD",
  405. .info = hdmi_eld_ctl_info,
  406. .get = hdmi_eld_ctl_get,
  407. };
  408. static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
  409. int device)
  410. {
  411. struct snd_kcontrol *kctl;
  412. struct hdmi_spec *spec = codec->spec;
  413. int err;
  414. kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
  415. if (!kctl)
  416. return -ENOMEM;
  417. kctl->private_value = pin_idx;
  418. kctl->id.device = device;
  419. err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl);
  420. if (err < 0)
  421. return err;
  422. get_pin(spec, pin_idx)->eld_ctl = kctl;
  423. return 0;
  424. }
  425. #ifdef BE_PARANOID
  426. static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
  427. int *packet_index, int *byte_index)
  428. {
  429. int val;
  430. val = snd_hda_codec_read(codec, pin_nid, 0,
  431. AC_VERB_GET_HDMI_DIP_INDEX, 0);
  432. *packet_index = val >> 5;
  433. *byte_index = val & 0x1f;
  434. }
  435. #endif
  436. static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
  437. int packet_index, int byte_index)
  438. {
  439. int val;
  440. val = (packet_index << 5) | (byte_index & 0x1f);
  441. snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
  442. }
  443. static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
  444. unsigned char val)
  445. {
  446. snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
  447. }
  448. static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
  449. {
  450. struct hdmi_spec *spec = codec->spec;
  451. int pin_out;
  452. /* Unmute */
  453. if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
  454. snd_hda_codec_write(codec, pin_nid, 0,
  455. AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
  456. if (spec->dyn_pin_out)
  457. /* Disable pin out until stream is active */
  458. pin_out = 0;
  459. else
  460. /* Enable pin out: some machines with GM965 gets broken output
  461. * when the pin is disabled or changed while using with HDMI
  462. */
  463. pin_out = PIN_OUT;
  464. snd_hda_codec_write(codec, pin_nid, 0,
  465. AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
  466. }
  467. static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
  468. {
  469. return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
  470. AC_VERB_GET_CVT_CHAN_COUNT, 0);
  471. }
  472. static void hdmi_set_channel_count(struct hda_codec *codec,
  473. hda_nid_t cvt_nid, int chs)
  474. {
  475. if (chs != hdmi_get_channel_count(codec, cvt_nid))
  476. snd_hda_codec_write(codec, cvt_nid, 0,
  477. AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
  478. }
  479. /*
  480. * ELD proc files
  481. */
  482. #ifdef CONFIG_SND_PROC_FS
  483. static void print_eld_info(struct snd_info_entry *entry,
  484. struct snd_info_buffer *buffer)
  485. {
  486. struct hdmi_spec_per_pin *per_pin = entry->private_data;
  487. mutex_lock(&per_pin->lock);
  488. snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
  489. mutex_unlock(&per_pin->lock);
  490. }
  491. static void write_eld_info(struct snd_info_entry *entry,
  492. struct snd_info_buffer *buffer)
  493. {
  494. struct hdmi_spec_per_pin *per_pin = entry->private_data;
  495. mutex_lock(&per_pin->lock);
  496. snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
  497. mutex_unlock(&per_pin->lock);
  498. }
  499. static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
  500. {
  501. char name[32];
  502. struct hda_codec *codec = per_pin->codec;
  503. struct snd_info_entry *entry;
  504. int err;
  505. snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
  506. err = snd_card_proc_new(codec->card, name, &entry);
  507. if (err < 0)
  508. return err;
  509. snd_info_set_text_ops(entry, per_pin, print_eld_info);
  510. entry->c.text.write = write_eld_info;
  511. entry->mode |= S_IWUSR;
  512. per_pin->proc_entry = entry;
  513. return 0;
  514. }
  515. static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
  516. {
  517. if (!per_pin->codec->bus->shutdown) {
  518. snd_info_free_entry(per_pin->proc_entry);
  519. per_pin->proc_entry = NULL;
  520. }
  521. }
  522. #else
  523. static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
  524. int index)
  525. {
  526. return 0;
  527. }
  528. static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
  529. {
  530. }
  531. #endif
  532. /*
  533. * Channel mapping routines
  534. */
  535. /*
  536. * Compute derived values in channel_allocations[].
  537. */
  538. static void init_channel_allocations(void)
  539. {
  540. int i, j;
  541. struct cea_channel_speaker_allocation *p;
  542. for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
  543. p = channel_allocations + i;
  544. p->channels = 0;
  545. p->spk_mask = 0;
  546. for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
  547. if (p->speakers[j]) {
  548. p->channels++;
  549. p->spk_mask |= p->speakers[j];
  550. }
  551. }
  552. }
  553. static int get_channel_allocation_order(int ca)
  554. {
  555. int i;
  556. for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
  557. if (channel_allocations[i].ca_index == ca)
  558. break;
  559. }
  560. return i;
  561. }
  562. /*
  563. * The transformation takes two steps:
  564. *
  565. * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
  566. * spk_mask => (channel_allocations[]) => ai->CA
  567. *
  568. * TODO: it could select the wrong CA from multiple candidates.
  569. */
  570. static int hdmi_channel_allocation(struct hda_codec *codec,
  571. struct hdmi_eld *eld, int channels)
  572. {
  573. int i;
  574. int ca = 0;
  575. int spk_mask = 0;
  576. char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
  577. /*
  578. * CA defaults to 0 for basic stereo audio
  579. */
  580. if (channels <= 2)
  581. return 0;
  582. /*
  583. * expand ELD's speaker allocation mask
  584. *
  585. * ELD tells the speaker mask in a compact(paired) form,
  586. * expand ELD's notions to match the ones used by Audio InfoFrame.
  587. */
  588. for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
  589. if (eld->info.spk_alloc & (1 << i))
  590. spk_mask |= eld_speaker_allocation_bits[i];
  591. }
  592. /* search for the first working match in the CA table */
  593. for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
  594. if (channels == channel_allocations[i].channels &&
  595. (spk_mask & channel_allocations[i].spk_mask) ==
  596. channel_allocations[i].spk_mask) {
  597. ca = channel_allocations[i].ca_index;
  598. break;
  599. }
  600. }
  601. if (!ca) {
  602. /* if there was no match, select the regular ALSA channel
  603. * allocation with the matching number of channels */
  604. for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
  605. if (channels == channel_allocations[i].channels) {
  606. ca = channel_allocations[i].ca_index;
  607. break;
  608. }
  609. }
  610. }
  611. snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
  612. codec_dbg(codec, "HDMI: select CA 0x%x for %d-channel allocation: %s\n",
  613. ca, channels, buf);
  614. return ca;
  615. }
  616. static void hdmi_debug_channel_mapping(struct hda_codec *codec,
  617. hda_nid_t pin_nid)
  618. {
  619. #ifdef CONFIG_SND_DEBUG_VERBOSE
  620. struct hdmi_spec *spec = codec->spec;
  621. int i;
  622. int channel;
  623. for (i = 0; i < 8; i++) {
  624. channel = spec->ops.pin_get_slot_channel(codec, pin_nid, i);
  625. codec_dbg(codec, "HDMI: ASP channel %d => slot %d\n",
  626. channel, i);
  627. }
  628. #endif
  629. }
  630. static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
  631. hda_nid_t pin_nid,
  632. bool non_pcm,
  633. int ca)
  634. {
  635. struct hdmi_spec *spec = codec->spec;
  636. struct cea_channel_speaker_allocation *ch_alloc;
  637. int i;
  638. int err;
  639. int order;
  640. int non_pcm_mapping[8];
  641. order = get_channel_allocation_order(ca);
  642. ch_alloc = &channel_allocations[order];
  643. if (hdmi_channel_mapping[ca][1] == 0) {
  644. int hdmi_slot = 0;
  645. /* fill actual channel mappings in ALSA channel (i) order */
  646. for (i = 0; i < ch_alloc->channels; i++) {
  647. while (!ch_alloc->speakers[7 - hdmi_slot] && !WARN_ON(hdmi_slot >= 8))
  648. hdmi_slot++; /* skip zero slots */
  649. hdmi_channel_mapping[ca][i] = (i << 4) | hdmi_slot++;
  650. }
  651. /* fill the rest of the slots with ALSA channel 0xf */
  652. for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++)
  653. if (!ch_alloc->speakers[7 - hdmi_slot])
  654. hdmi_channel_mapping[ca][i++] = (0xf << 4) | hdmi_slot;
  655. }
  656. if (non_pcm) {
  657. for (i = 0; i < ch_alloc->channels; i++)
  658. non_pcm_mapping[i] = (i << 4) | i;
  659. for (; i < 8; i++)
  660. non_pcm_mapping[i] = (0xf << 4) | i;
  661. }
  662. for (i = 0; i < 8; i++) {
  663. int slotsetup = non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i];
  664. int hdmi_slot = slotsetup & 0x0f;
  665. int channel = (slotsetup & 0xf0) >> 4;
  666. err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot, channel);
  667. if (err) {
  668. codec_dbg(codec, "HDMI: channel mapping failed\n");
  669. break;
  670. }
  671. }
  672. }
  673. struct channel_map_table {
  674. unsigned char map; /* ALSA API channel map position */
  675. int spk_mask; /* speaker position bit mask */
  676. };
  677. static struct channel_map_table map_tables[] = {
  678. { SNDRV_CHMAP_FL, FL },
  679. { SNDRV_CHMAP_FR, FR },
  680. { SNDRV_CHMAP_RL, RL },
  681. { SNDRV_CHMAP_RR, RR },
  682. { SNDRV_CHMAP_LFE, LFE },
  683. { SNDRV_CHMAP_FC, FC },
  684. { SNDRV_CHMAP_RLC, RLC },
  685. { SNDRV_CHMAP_RRC, RRC },
  686. { SNDRV_CHMAP_RC, RC },
  687. { SNDRV_CHMAP_FLC, FLC },
  688. { SNDRV_CHMAP_FRC, FRC },
  689. { SNDRV_CHMAP_TFL, FLH },
  690. { SNDRV_CHMAP_TFR, FRH },
  691. { SNDRV_CHMAP_FLW, FLW },
  692. { SNDRV_CHMAP_FRW, FRW },
  693. { SNDRV_CHMAP_TC, TC },
  694. { SNDRV_CHMAP_TFC, FCH },
  695. {} /* terminator */
  696. };
  697. /* from ALSA API channel position to speaker bit mask */
  698. static int to_spk_mask(unsigned char c)
  699. {
  700. struct channel_map_table *t = map_tables;
  701. for (; t->map; t++) {
  702. if (t->map == c)
  703. return t->spk_mask;
  704. }
  705. return 0;
  706. }
  707. /* from ALSA API channel position to CEA slot */
  708. static int to_cea_slot(int ordered_ca, unsigned char pos)
  709. {
  710. int mask = to_spk_mask(pos);
  711. int i;
  712. if (mask) {
  713. for (i = 0; i < 8; i++) {
  714. if (channel_allocations[ordered_ca].speakers[7 - i] == mask)
  715. return i;
  716. }
  717. }
  718. return -1;
  719. }
  720. /* from speaker bit mask to ALSA API channel position */
  721. static int spk_to_chmap(int spk)
  722. {
  723. struct channel_map_table *t = map_tables;
  724. for (; t->map; t++) {
  725. if (t->spk_mask == spk)
  726. return t->map;
  727. }
  728. return 0;
  729. }
  730. /* from CEA slot to ALSA API channel position */
  731. static int from_cea_slot(int ordered_ca, unsigned char slot)
  732. {
  733. int mask = channel_allocations[ordered_ca].speakers[7 - slot];
  734. return spk_to_chmap(mask);
  735. }
  736. /* get the CA index corresponding to the given ALSA API channel map */
  737. static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
  738. {
  739. int i, spks = 0, spk_mask = 0;
  740. for (i = 0; i < chs; i++) {
  741. int mask = to_spk_mask(map[i]);
  742. if (mask) {
  743. spk_mask |= mask;
  744. spks++;
  745. }
  746. }
  747. for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
  748. if ((chs == channel_allocations[i].channels ||
  749. spks == channel_allocations[i].channels) &&
  750. (spk_mask & channel_allocations[i].spk_mask) ==
  751. channel_allocations[i].spk_mask)
  752. return channel_allocations[i].ca_index;
  753. }
  754. return -1;
  755. }
  756. /* set up the channel slots for the given ALSA API channel map */
  757. static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
  758. hda_nid_t pin_nid,
  759. int chs, unsigned char *map,
  760. int ca)
  761. {
  762. struct hdmi_spec *spec = codec->spec;
  763. int ordered_ca = get_channel_allocation_order(ca);
  764. int alsa_pos, hdmi_slot;
  765. int assignments[8] = {[0 ... 7] = 0xf};
  766. for (alsa_pos = 0; alsa_pos < chs; alsa_pos++) {
  767. hdmi_slot = to_cea_slot(ordered_ca, map[alsa_pos]);
  768. if (hdmi_slot < 0)
  769. continue; /* unassigned channel */
  770. assignments[hdmi_slot] = alsa_pos;
  771. }
  772. for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) {
  773. int err;
  774. err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot,
  775. assignments[hdmi_slot]);
  776. if (err)
  777. return -EINVAL;
  778. }
  779. return 0;
  780. }
  781. /* store ALSA API channel map from the current default map */
  782. static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
  783. {
  784. int i;
  785. int ordered_ca = get_channel_allocation_order(ca);
  786. for (i = 0; i < 8; i++) {
  787. if (i < channel_allocations[ordered_ca].channels)
  788. map[i] = from_cea_slot(ordered_ca, hdmi_channel_mapping[ca][i] & 0x0f);
  789. else
  790. map[i] = 0;
  791. }
  792. }
  793. static void hdmi_setup_channel_mapping(struct hda_codec *codec,
  794. hda_nid_t pin_nid, bool non_pcm, int ca,
  795. int channels, unsigned char *map,
  796. bool chmap_set)
  797. {
  798. if (!non_pcm && chmap_set) {
  799. hdmi_manual_setup_channel_mapping(codec, pin_nid,
  800. channels, map, ca);
  801. } else {
  802. hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
  803. hdmi_setup_fake_chmap(map, ca);
  804. }
  805. hdmi_debug_channel_mapping(codec, pin_nid);
  806. }
  807. static int hdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
  808. int asp_slot, int channel)
  809. {
  810. return snd_hda_codec_write(codec, pin_nid, 0,
  811. AC_VERB_SET_HDMI_CHAN_SLOT,
  812. (channel << 4) | asp_slot);
  813. }
  814. static int hdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
  815. int asp_slot)
  816. {
  817. return (snd_hda_codec_read(codec, pin_nid, 0,
  818. AC_VERB_GET_HDMI_CHAN_SLOT,
  819. asp_slot) & 0xf0) >> 4;
  820. }
  821. /*
  822. * Audio InfoFrame routines
  823. */
  824. /*
  825. * Enable Audio InfoFrame Transmission
  826. */
  827. static void hdmi_start_infoframe_trans(struct hda_codec *codec,
  828. hda_nid_t pin_nid)
  829. {
  830. hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
  831. snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
  832. AC_DIPXMIT_BEST);
  833. }
  834. /*
  835. * Disable Audio InfoFrame Transmission
  836. */
  837. static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
  838. hda_nid_t pin_nid)
  839. {
  840. hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
  841. snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
  842. AC_DIPXMIT_DISABLE);
  843. }
  844. static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
  845. {
  846. #ifdef CONFIG_SND_DEBUG_VERBOSE
  847. int i;
  848. int size;
  849. size = snd_hdmi_get_eld_size(codec, pin_nid);
  850. codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
  851. for (i = 0; i < 8; i++) {
  852. size = snd_hda_codec_read(codec, pin_nid, 0,
  853. AC_VERB_GET_HDMI_DIP_SIZE, i);
  854. codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
  855. }
  856. #endif
  857. }
  858. static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
  859. {
  860. #ifdef BE_PARANOID
  861. int i, j;
  862. int size;
  863. int pi, bi;
  864. for (i = 0; i < 8; i++) {
  865. size = snd_hda_codec_read(codec, pin_nid, 0,
  866. AC_VERB_GET_HDMI_DIP_SIZE, i);
  867. if (size == 0)
  868. continue;
  869. hdmi_set_dip_index(codec, pin_nid, i, 0x0);
  870. for (j = 1; j < 1000; j++) {
  871. hdmi_write_dip_byte(codec, pin_nid, 0x0);
  872. hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
  873. if (pi != i)
  874. codec_dbg(codec, "dip index %d: %d != %d\n",
  875. bi, pi, i);
  876. if (bi == 0) /* byte index wrapped around */
  877. break;
  878. }
  879. codec_dbg(codec,
  880. "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
  881. i, size, j);
  882. }
  883. #endif
  884. }
  885. static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
  886. {
  887. u8 *bytes = (u8 *)hdmi_ai;
  888. u8 sum = 0;
  889. int i;
  890. hdmi_ai->checksum = 0;
  891. for (i = 0; i < sizeof(*hdmi_ai); i++)
  892. sum += bytes[i];
  893. hdmi_ai->checksum = -sum;
  894. }
  895. static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
  896. hda_nid_t pin_nid,
  897. u8 *dip, int size)
  898. {
  899. int i;
  900. hdmi_debug_dip_size(codec, pin_nid);
  901. hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
  902. hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
  903. for (i = 0; i < size; i++)
  904. hdmi_write_dip_byte(codec, pin_nid, dip[i]);
  905. }
  906. static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
  907. u8 *dip, int size)
  908. {
  909. u8 val;
  910. int i;
  911. if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
  912. != AC_DIPXMIT_BEST)
  913. return false;
  914. hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
  915. for (i = 0; i < size; i++) {
  916. val = snd_hda_codec_read(codec, pin_nid, 0,
  917. AC_VERB_GET_HDMI_DIP_DATA, 0);
  918. if (val != dip[i])
  919. return false;
  920. }
  921. return true;
  922. }
  923. static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
  924. hda_nid_t pin_nid,
  925. int ca, int active_channels,
  926. int conn_type)
  927. {
  928. union audio_infoframe ai;
  929. memset(&ai, 0, sizeof(ai));
  930. if (conn_type == 0) { /* HDMI */
  931. struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
  932. hdmi_ai->type = 0x84;
  933. hdmi_ai->ver = 0x01;
  934. hdmi_ai->len = 0x0a;
  935. hdmi_ai->CC02_CT47 = active_channels - 1;
  936. hdmi_ai->CA = ca;
  937. hdmi_checksum_audio_infoframe(hdmi_ai);
  938. } else if (conn_type == 1) { /* DisplayPort */
  939. struct dp_audio_infoframe *dp_ai = &ai.dp;
  940. dp_ai->type = 0x84;
  941. dp_ai->len = 0x1b;
  942. dp_ai->ver = 0x11 << 2;
  943. dp_ai->CC02_CT47 = active_channels - 1;
  944. dp_ai->CA = ca;
  945. } else {
  946. codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
  947. pin_nid);
  948. return;
  949. }
  950. /*
  951. * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
  952. * sizeof(*dp_ai) to avoid partial match/update problems when
  953. * the user switches between HDMI/DP monitors.
  954. */
  955. if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
  956. sizeof(ai))) {
  957. codec_dbg(codec,
  958. "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
  959. pin_nid,
  960. active_channels, ca);
  961. hdmi_stop_infoframe_trans(codec, pin_nid);
  962. hdmi_fill_audio_infoframe(codec, pin_nid,
  963. ai.bytes, sizeof(ai));
  964. hdmi_start_infoframe_trans(codec, pin_nid);
  965. }
  966. }
  967. static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
  968. struct hdmi_spec_per_pin *per_pin,
  969. bool non_pcm)
  970. {
  971. struct hdmi_spec *spec = codec->spec;
  972. hda_nid_t pin_nid = per_pin->pin_nid;
  973. int channels = per_pin->channels;
  974. int active_channels;
  975. struct hdmi_eld *eld;
  976. int ca, ordered_ca;
  977. if (!channels)
  978. return;
  979. if (is_haswell_plus(codec))
  980. snd_hda_codec_write(codec, pin_nid, 0,
  981. AC_VERB_SET_AMP_GAIN_MUTE,
  982. AMP_OUT_UNMUTE);
  983. eld = &per_pin->sink_eld;
  984. if (!non_pcm && per_pin->chmap_set)
  985. ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
  986. else
  987. ca = hdmi_channel_allocation(codec, eld, channels);
  988. if (ca < 0)
  989. ca = 0;
  990. ordered_ca = get_channel_allocation_order(ca);
  991. active_channels = channel_allocations[ordered_ca].channels;
  992. hdmi_set_channel_count(codec, per_pin->cvt_nid, active_channels);
  993. /*
  994. * always configure channel mapping, it may have been changed by the
  995. * user in the meantime
  996. */
  997. hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
  998. channels, per_pin->chmap,
  999. per_pin->chmap_set);
  1000. spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
  1001. eld->info.conn_type);
  1002. per_pin->non_pcm = non_pcm;
  1003. }
  1004. /*
  1005. * Unsolicited events
  1006. */
  1007. static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
  1008. static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid)
  1009. {
  1010. struct hdmi_spec *spec = codec->spec;
  1011. int pin_idx = pin_nid_to_pin_index(codec, nid);
  1012. if (pin_idx < 0)
  1013. return;
  1014. if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
  1015. snd_hda_jack_report_sync(codec);
  1016. }
  1017. static void jack_callback(struct hda_codec *codec,
  1018. struct hda_jack_callback *jack)
  1019. {
  1020. check_presence_and_report(codec, jack->nid);
  1021. }
  1022. static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
  1023. {
  1024. int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
  1025. struct hda_jack_tbl *jack;
  1026. int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
  1027. jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
  1028. if (!jack)
  1029. return;
  1030. jack->jack_dirty = 1;
  1031. codec_dbg(codec,
  1032. "HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
  1033. codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
  1034. !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
  1035. check_presence_and_report(codec, jack->nid);
  1036. }
  1037. static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
  1038. {
  1039. int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
  1040. int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
  1041. int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
  1042. int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
  1043. codec_info(codec,
  1044. "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
  1045. codec->addr,
  1046. tag,
  1047. subtag,
  1048. cp_state,
  1049. cp_ready);
  1050. /* TODO */
  1051. if (cp_state)
  1052. ;
  1053. if (cp_ready)
  1054. ;
  1055. }
  1056. static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
  1057. {
  1058. int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
  1059. int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
  1060. if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
  1061. codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
  1062. return;
  1063. }
  1064. if (subtag == 0)
  1065. hdmi_intrinsic_event(codec, res);
  1066. else
  1067. hdmi_non_intrinsic_event(codec, res);
  1068. }
  1069. static void haswell_verify_D0(struct hda_codec *codec,
  1070. hda_nid_t cvt_nid, hda_nid_t nid)
  1071. {
  1072. int pwr;
  1073. /* For Haswell, the converter 1/2 may keep in D3 state after bootup,
  1074. * thus pins could only choose converter 0 for use. Make sure the
  1075. * converters are in correct power state */
  1076. if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
  1077. snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
  1078. if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
  1079. snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
  1080. AC_PWRST_D0);
  1081. msleep(40);
  1082. pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
  1083. pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
  1084. codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
  1085. }
  1086. }
  1087. /*
  1088. * Callbacks
  1089. */
  1090. /* HBR should be Non-PCM, 8 channels */
  1091. #define is_hbr_format(format) \
  1092. ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
  1093. static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
  1094. bool hbr)
  1095. {
  1096. int pinctl, new_pinctl;
  1097. if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
  1098. pinctl = snd_hda_codec_read(codec, pin_nid, 0,
  1099. AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
  1100. if (pinctl < 0)
  1101. return hbr ? -EINVAL : 0;
  1102. new_pinctl = pinctl & ~AC_PINCTL_EPT;
  1103. if (hbr)
  1104. new_pinctl |= AC_PINCTL_EPT_HBR;
  1105. else
  1106. new_pinctl |= AC_PINCTL_EPT_NATIVE;
  1107. codec_dbg(codec,
  1108. "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
  1109. pin_nid,
  1110. pinctl == new_pinctl ? "" : "new-",
  1111. new_pinctl);
  1112. if (pinctl != new_pinctl)
  1113. snd_hda_codec_write(codec, pin_nid, 0,
  1114. AC_VERB_SET_PIN_WIDGET_CONTROL,
  1115. new_pinctl);
  1116. } else if (hbr)
  1117. return -EINVAL;
  1118. return 0;
  1119. }
  1120. static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
  1121. hda_nid_t pin_nid, u32 stream_tag, int format)
  1122. {
  1123. struct hdmi_spec *spec = codec->spec;
  1124. int err;
  1125. if (is_haswell_plus(codec))
  1126. haswell_verify_D0(codec, cvt_nid, pin_nid);
  1127. err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
  1128. if (err) {
  1129. codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
  1130. return err;
  1131. }
  1132. snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
  1133. return 0;
  1134. }
  1135. static int hdmi_choose_cvt(struct hda_codec *codec,
  1136. int pin_idx, int *cvt_id, int *mux_id)
  1137. {
  1138. struct hdmi_spec *spec = codec->spec;
  1139. struct hdmi_spec_per_pin *per_pin;
  1140. struct hdmi_spec_per_cvt *per_cvt = NULL;
  1141. int cvt_idx, mux_idx = 0;
  1142. per_pin = get_pin(spec, pin_idx);
  1143. /* Dynamically assign converter to stream */
  1144. for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
  1145. per_cvt = get_cvt(spec, cvt_idx);
  1146. /* Must not already be assigned */
  1147. if (per_cvt->assigned)
  1148. continue;
  1149. /* Must be in pin's mux's list of converters */
  1150. for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
  1151. if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
  1152. break;
  1153. /* Not in mux list */
  1154. if (mux_idx == per_pin->num_mux_nids)
  1155. continue;
  1156. break;
  1157. }
  1158. /* No free converters */
  1159. if (cvt_idx == spec->num_cvts)
  1160. return -ENODEV;
  1161. per_pin->mux_idx = mux_idx;
  1162. if (cvt_id)
  1163. *cvt_id = cvt_idx;
  1164. if (mux_id)
  1165. *mux_id = mux_idx;
  1166. return 0;
  1167. }
  1168. /* Assure the pin select the right convetor */
  1169. static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
  1170. struct hdmi_spec_per_pin *per_pin)
  1171. {
  1172. hda_nid_t pin_nid = per_pin->pin_nid;
  1173. int mux_idx, curr;
  1174. mux_idx = per_pin->mux_idx;
  1175. curr = snd_hda_codec_read(codec, pin_nid, 0,
  1176. AC_VERB_GET_CONNECT_SEL, 0);
  1177. if (curr != mux_idx)
  1178. snd_hda_codec_write_cache(codec, pin_nid, 0,
  1179. AC_VERB_SET_CONNECT_SEL,
  1180. mux_idx);
  1181. }
  1182. /* Intel HDMI workaround to fix audio routing issue:
  1183. * For some Intel display codecs, pins share the same connection list.
  1184. * So a conveter can be selected by multiple pins and playback on any of these
  1185. * pins will generate sound on the external display, because audio flows from
  1186. * the same converter to the display pipeline. Also muting one pin may make
  1187. * other pins have no sound output.
  1188. * So this function assures that an assigned converter for a pin is not selected
  1189. * by any other pins.
  1190. */
  1191. static void intel_not_share_assigned_cvt(struct hda_codec *codec,
  1192. hda_nid_t pin_nid, int mux_idx)
  1193. {
  1194. struct hdmi_spec *spec = codec->spec;
  1195. hda_nid_t nid;
  1196. int cvt_idx, curr;
  1197. struct hdmi_spec_per_cvt *per_cvt;
  1198. /* configure all pins, including "no physical connection" ones */
  1199. for_each_hda_codec_node(nid, codec) {
  1200. unsigned int wid_caps = get_wcaps(codec, nid);
  1201. unsigned int wid_type = get_wcaps_type(wid_caps);
  1202. if (wid_type != AC_WID_PIN)
  1203. continue;
  1204. if (nid == pin_nid)
  1205. continue;
  1206. curr = snd_hda_codec_read(codec, nid, 0,
  1207. AC_VERB_GET_CONNECT_SEL, 0);
  1208. if (curr != mux_idx)
  1209. continue;
  1210. /* choose an unassigned converter. The conveters in the
  1211. * connection list are in the same order as in the codec.
  1212. */
  1213. for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
  1214. per_cvt = get_cvt(spec, cvt_idx);
  1215. if (!per_cvt->assigned) {
  1216. codec_dbg(codec,
  1217. "choose cvt %d for pin nid %d\n",
  1218. cvt_idx, nid);
  1219. snd_hda_codec_write_cache(codec, nid, 0,
  1220. AC_VERB_SET_CONNECT_SEL,
  1221. cvt_idx);
  1222. break;
  1223. }
  1224. }
  1225. }
  1226. }
  1227. /*
  1228. * HDA PCM callbacks
  1229. */
  1230. static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
  1231. struct hda_codec *codec,
  1232. struct snd_pcm_substream *substream)
  1233. {
  1234. struct hdmi_spec *spec = codec->spec;
  1235. struct snd_pcm_runtime *runtime = substream->runtime;
  1236. int pin_idx, cvt_idx, mux_idx = 0;
  1237. struct hdmi_spec_per_pin *per_pin;
  1238. struct hdmi_eld *eld;
  1239. struct hdmi_spec_per_cvt *per_cvt = NULL;
  1240. int err;
  1241. /* Validate hinfo */
  1242. pin_idx = hinfo_to_pin_index(codec, hinfo);
  1243. if (snd_BUG_ON(pin_idx < 0))
  1244. return -EINVAL;
  1245. per_pin = get_pin(spec, pin_idx);
  1246. eld = &per_pin->sink_eld;
  1247. err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
  1248. if (err < 0)
  1249. return err;
  1250. per_cvt = get_cvt(spec, cvt_idx);
  1251. /* Claim converter */
  1252. per_cvt->assigned = 1;
  1253. per_pin->cvt_nid = per_cvt->cvt_nid;
  1254. hinfo->nid = per_cvt->cvt_nid;
  1255. snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
  1256. AC_VERB_SET_CONNECT_SEL,
  1257. mux_idx);
  1258. /* configure unused pins to choose other converters */
  1259. if (is_haswell_plus(codec) || is_valleyview_plus(codec))
  1260. intel_not_share_assigned_cvt(codec, per_pin->pin_nid, mux_idx);
  1261. snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
  1262. /* Initially set the converter's capabilities */
  1263. hinfo->channels_min = per_cvt->channels_min;
  1264. hinfo->channels_max = per_cvt->channels_max;
  1265. hinfo->rates = per_cvt->rates;
  1266. hinfo->formats = per_cvt->formats;
  1267. hinfo->maxbps = per_cvt->maxbps;
  1268. /* Restrict capabilities by ELD if this isn't disabled */
  1269. if (!static_hdmi_pcm && eld->eld_valid) {
  1270. snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
  1271. if (hinfo->channels_min > hinfo->channels_max ||
  1272. !hinfo->rates || !hinfo->formats) {
  1273. per_cvt->assigned = 0;
  1274. hinfo->nid = 0;
  1275. snd_hda_spdif_ctls_unassign(codec, pin_idx);
  1276. return -ENODEV;
  1277. }
  1278. }
  1279. /* Store the updated parameters */
  1280. runtime->hw.channels_min = hinfo->channels_min;
  1281. runtime->hw.channels_max = hinfo->channels_max;
  1282. runtime->hw.formats = hinfo->formats;
  1283. runtime->hw.rates = hinfo->rates;
  1284. snd_pcm_hw_constraint_step(substream->runtime, 0,
  1285. SNDRV_PCM_HW_PARAM_CHANNELS, 2);
  1286. return 0;
  1287. }
  1288. /*
  1289. * HDA/HDMI auto parsing
  1290. */
  1291. static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
  1292. {
  1293. struct hdmi_spec *spec = codec->spec;
  1294. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  1295. hda_nid_t pin_nid = per_pin->pin_nid;
  1296. if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
  1297. codec_warn(codec,
  1298. "HDMI: pin %d wcaps %#x does not support connection list\n",
  1299. pin_nid, get_wcaps(codec, pin_nid));
  1300. return -EINVAL;
  1301. }
  1302. per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
  1303. per_pin->mux_nids,
  1304. HDA_MAX_CONNECTIONS);
  1305. return 0;
  1306. }
  1307. static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
  1308. {
  1309. struct hda_jack_tbl *jack;
  1310. struct hda_codec *codec = per_pin->codec;
  1311. struct hdmi_spec *spec = codec->spec;
  1312. struct hdmi_eld *eld = &spec->temp_eld;
  1313. struct hdmi_eld *pin_eld = &per_pin->sink_eld;
  1314. hda_nid_t pin_nid = per_pin->pin_nid;
  1315. /*
  1316. * Always execute a GetPinSense verb here, even when called from
  1317. * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
  1318. * response's PD bit is not the real PD value, but indicates that
  1319. * the real PD value changed. An older version of the HD-audio
  1320. * specification worked this way. Hence, we just ignore the data in
  1321. * the unsolicited response to avoid custom WARs.
  1322. */
  1323. int present;
  1324. bool update_eld = false;
  1325. bool eld_changed = false;
  1326. bool ret;
  1327. snd_hda_power_up_pm(codec);
  1328. present = snd_hda_pin_sense(codec, pin_nid);
  1329. mutex_lock(&per_pin->lock);
  1330. pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
  1331. if (pin_eld->monitor_present)
  1332. eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
  1333. else
  1334. eld->eld_valid = false;
  1335. codec_dbg(codec,
  1336. "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
  1337. codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
  1338. if (eld->eld_valid) {
  1339. if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
  1340. &eld->eld_size) < 0)
  1341. eld->eld_valid = false;
  1342. else {
  1343. memset(&eld->info, 0, sizeof(struct parsed_hdmi_eld));
  1344. if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
  1345. eld->eld_size) < 0)
  1346. eld->eld_valid = false;
  1347. }
  1348. if (eld->eld_valid) {
  1349. snd_hdmi_show_eld(codec, &eld->info);
  1350. update_eld = true;
  1351. }
  1352. else if (repoll) {
  1353. schedule_delayed_work(&per_pin->work,
  1354. msecs_to_jiffies(300));
  1355. goto unlock;
  1356. }
  1357. }
  1358. if (pin_eld->eld_valid != eld->eld_valid)
  1359. eld_changed = true;
  1360. if (pin_eld->eld_valid && !eld->eld_valid)
  1361. update_eld = true;
  1362. if (update_eld) {
  1363. bool old_eld_valid = pin_eld->eld_valid;
  1364. pin_eld->eld_valid = eld->eld_valid;
  1365. if (pin_eld->eld_size != eld->eld_size ||
  1366. memcmp(pin_eld->eld_buffer, eld->eld_buffer,
  1367. eld->eld_size) != 0) {
  1368. memcpy(pin_eld->eld_buffer, eld->eld_buffer,
  1369. eld->eld_size);
  1370. eld_changed = true;
  1371. }
  1372. pin_eld->eld_size = eld->eld_size;
  1373. pin_eld->info = eld->info;
  1374. /*
  1375. * Re-setup pin and infoframe. This is needed e.g. when
  1376. * - sink is first plugged-in (infoframe is not set up if !monitor_present)
  1377. * - transcoder can change during stream playback on Haswell
  1378. * and this can make HW reset converter selection on a pin.
  1379. */
  1380. if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
  1381. if (is_haswell_plus(codec) ||
  1382. is_valleyview_plus(codec)) {
  1383. intel_verify_pin_cvt_connect(codec, per_pin);
  1384. intel_not_share_assigned_cvt(codec, pin_nid,
  1385. per_pin->mux_idx);
  1386. }
  1387. hdmi_setup_audio_infoframe(codec, per_pin,
  1388. per_pin->non_pcm);
  1389. }
  1390. }
  1391. if (eld_changed)
  1392. snd_ctl_notify(codec->card,
  1393. SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO,
  1394. &per_pin->eld_ctl->id);
  1395. unlock:
  1396. ret = !repoll || !pin_eld->monitor_present || pin_eld->eld_valid;
  1397. jack = snd_hda_jack_tbl_get(codec, pin_nid);
  1398. if (jack)
  1399. jack->block_report = !ret;
  1400. mutex_unlock(&per_pin->lock);
  1401. snd_hda_power_down_pm(codec);
  1402. return ret;
  1403. }
  1404. static void hdmi_repoll_eld(struct work_struct *work)
  1405. {
  1406. struct hdmi_spec_per_pin *per_pin =
  1407. container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
  1408. if (per_pin->repoll_count++ > 6)
  1409. per_pin->repoll_count = 0;
  1410. if (hdmi_present_sense(per_pin, per_pin->repoll_count))
  1411. snd_hda_jack_report_sync(per_pin->codec);
  1412. }
  1413. static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
  1414. hda_nid_t nid);
  1415. static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
  1416. {
  1417. struct hdmi_spec *spec = codec->spec;
  1418. unsigned int caps, config;
  1419. int pin_idx;
  1420. struct hdmi_spec_per_pin *per_pin;
  1421. int err;
  1422. caps = snd_hda_query_pin_caps(codec, pin_nid);
  1423. if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
  1424. return 0;
  1425. config = snd_hda_codec_get_pincfg(codec, pin_nid);
  1426. if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
  1427. return 0;
  1428. if (is_haswell_plus(codec))
  1429. intel_haswell_fixup_connect_list(codec, pin_nid);
  1430. pin_idx = spec->num_pins;
  1431. per_pin = snd_array_new(&spec->pins);
  1432. if (!per_pin)
  1433. return -ENOMEM;
  1434. per_pin->pin_nid = pin_nid;
  1435. per_pin->non_pcm = false;
  1436. err = hdmi_read_pin_conn(codec, pin_idx);
  1437. if (err < 0)
  1438. return err;
  1439. spec->num_pins++;
  1440. return 0;
  1441. }
  1442. static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
  1443. {
  1444. struct hdmi_spec *spec = codec->spec;
  1445. struct hdmi_spec_per_cvt *per_cvt;
  1446. unsigned int chans;
  1447. int err;
  1448. chans = get_wcaps(codec, cvt_nid);
  1449. chans = get_wcaps_channels(chans);
  1450. per_cvt = snd_array_new(&spec->cvts);
  1451. if (!per_cvt)
  1452. return -ENOMEM;
  1453. per_cvt->cvt_nid = cvt_nid;
  1454. per_cvt->channels_min = 2;
  1455. if (chans <= 16) {
  1456. per_cvt->channels_max = chans;
  1457. if (chans > spec->channels_max)
  1458. spec->channels_max = chans;
  1459. }
  1460. err = snd_hda_query_supported_pcm(codec, cvt_nid,
  1461. &per_cvt->rates,
  1462. &per_cvt->formats,
  1463. &per_cvt->maxbps);
  1464. if (err < 0)
  1465. return err;
  1466. if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
  1467. spec->cvt_nids[spec->num_cvts] = cvt_nid;
  1468. spec->num_cvts++;
  1469. return 0;
  1470. }
  1471. static int hdmi_parse_codec(struct hda_codec *codec)
  1472. {
  1473. hda_nid_t nid;
  1474. int i, nodes;
  1475. nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
  1476. if (!nid || nodes < 0) {
  1477. codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
  1478. return -EINVAL;
  1479. }
  1480. for (i = 0; i < nodes; i++, nid++) {
  1481. unsigned int caps;
  1482. unsigned int type;
  1483. caps = get_wcaps(codec, nid);
  1484. type = get_wcaps_type(caps);
  1485. if (!(caps & AC_WCAP_DIGITAL))
  1486. continue;
  1487. switch (type) {
  1488. case AC_WID_AUD_OUT:
  1489. hdmi_add_cvt(codec, nid);
  1490. break;
  1491. case AC_WID_PIN:
  1492. hdmi_add_pin(codec, nid);
  1493. break;
  1494. }
  1495. }
  1496. return 0;
  1497. }
  1498. /*
  1499. */
  1500. static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
  1501. {
  1502. struct hda_spdif_out *spdif;
  1503. bool non_pcm;
  1504. mutex_lock(&codec->spdif_mutex);
  1505. spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
  1506. non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
  1507. mutex_unlock(&codec->spdif_mutex);
  1508. return non_pcm;
  1509. }
  1510. /* There is a fixed mapping between audio pin node and display port
  1511. * on current Intel platforms:
  1512. * Pin Widget 5 - PORT B (port = 1 in i915 driver)
  1513. * Pin Widget 6 - PORT C (port = 2 in i915 driver)
  1514. * Pin Widget 7 - PORT D (port = 3 in i915 driver)
  1515. */
  1516. static int intel_pin2port(hda_nid_t pin_nid)
  1517. {
  1518. return pin_nid - 4;
  1519. }
  1520. /*
  1521. * HDMI callbacks
  1522. */
  1523. static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
  1524. struct hda_codec *codec,
  1525. unsigned int stream_tag,
  1526. unsigned int format,
  1527. struct snd_pcm_substream *substream)
  1528. {
  1529. hda_nid_t cvt_nid = hinfo->nid;
  1530. struct hdmi_spec *spec = codec->spec;
  1531. int pin_idx = hinfo_to_pin_index(codec, hinfo);
  1532. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  1533. hda_nid_t pin_nid = per_pin->pin_nid;
  1534. struct snd_pcm_runtime *runtime = substream->runtime;
  1535. struct i915_audio_component *acomp = codec->bus->core.audio_component;
  1536. bool non_pcm;
  1537. int pinctl;
  1538. if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
  1539. /* Verify pin:cvt selections to avoid silent audio after S3.
  1540. * After S3, the audio driver restores pin:cvt selections
  1541. * but this can happen before gfx is ready and such selection
  1542. * is overlooked by HW. Thus multiple pins can share a same
  1543. * default convertor and mute control will affect each other,
  1544. * which can cause a resumed audio playback become silent
  1545. * after S3.
  1546. */
  1547. intel_verify_pin_cvt_connect(codec, per_pin);
  1548. intel_not_share_assigned_cvt(codec, pin_nid, per_pin->mux_idx);
  1549. }
  1550. /* Call sync_audio_rate to set the N/CTS/M manually if necessary */
  1551. /* Todo: add DP1.2 MST audio support later */
  1552. if (acomp && acomp->ops && acomp->ops->sync_audio_rate)
  1553. acomp->ops->sync_audio_rate(acomp->dev,
  1554. intel_pin2port(pin_nid),
  1555. runtime->rate);
  1556. non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
  1557. mutex_lock(&per_pin->lock);
  1558. per_pin->channels = substream->runtime->channels;
  1559. per_pin->setup = true;
  1560. hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
  1561. mutex_unlock(&per_pin->lock);
  1562. if (spec->dyn_pin_out) {
  1563. pinctl = snd_hda_codec_read(codec, pin_nid, 0,
  1564. AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
  1565. snd_hda_codec_write(codec, pin_nid, 0,
  1566. AC_VERB_SET_PIN_WIDGET_CONTROL,
  1567. pinctl | PIN_OUT);
  1568. }
  1569. return spec->ops.setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
  1570. }
  1571. static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
  1572. struct hda_codec *codec,
  1573. struct snd_pcm_substream *substream)
  1574. {
  1575. snd_hda_codec_cleanup_stream(codec, hinfo->nid);
  1576. return 0;
  1577. }
  1578. static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
  1579. struct hda_codec *codec,
  1580. struct snd_pcm_substream *substream)
  1581. {
  1582. struct hdmi_spec *spec = codec->spec;
  1583. int cvt_idx, pin_idx;
  1584. struct hdmi_spec_per_cvt *per_cvt;
  1585. struct hdmi_spec_per_pin *per_pin;
  1586. int pinctl;
  1587. if (hinfo->nid) {
  1588. cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
  1589. if (snd_BUG_ON(cvt_idx < 0))
  1590. return -EINVAL;
  1591. per_cvt = get_cvt(spec, cvt_idx);
  1592. snd_BUG_ON(!per_cvt->assigned);
  1593. per_cvt->assigned = 0;
  1594. hinfo->nid = 0;
  1595. pin_idx = hinfo_to_pin_index(codec, hinfo);
  1596. if (snd_BUG_ON(pin_idx < 0))
  1597. return -EINVAL;
  1598. per_pin = get_pin(spec, pin_idx);
  1599. if (spec->dyn_pin_out) {
  1600. pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
  1601. AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
  1602. snd_hda_codec_write(codec, per_pin->pin_nid, 0,
  1603. AC_VERB_SET_PIN_WIDGET_CONTROL,
  1604. pinctl & ~PIN_OUT);
  1605. }
  1606. snd_hda_spdif_ctls_unassign(codec, pin_idx);
  1607. mutex_lock(&per_pin->lock);
  1608. per_pin->chmap_set = false;
  1609. memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
  1610. per_pin->setup = false;
  1611. per_pin->channels = 0;
  1612. mutex_unlock(&per_pin->lock);
  1613. }
  1614. return 0;
  1615. }
  1616. static const struct hda_pcm_ops generic_ops = {
  1617. .open = hdmi_pcm_open,
  1618. .close = hdmi_pcm_close,
  1619. .prepare = generic_hdmi_playback_pcm_prepare,
  1620. .cleanup = generic_hdmi_playback_pcm_cleanup,
  1621. };
  1622. /*
  1623. * ALSA API channel-map control callbacks
  1624. */
  1625. static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
  1626. struct snd_ctl_elem_info *uinfo)
  1627. {
  1628. struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
  1629. struct hda_codec *codec = info->private_data;
  1630. struct hdmi_spec *spec = codec->spec;
  1631. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1632. uinfo->count = spec->channels_max;
  1633. uinfo->value.integer.min = 0;
  1634. uinfo->value.integer.max = SNDRV_CHMAP_LAST;
  1635. return 0;
  1636. }
  1637. static int hdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
  1638. int channels)
  1639. {
  1640. /* If the speaker allocation matches the channel count, it is OK.*/
  1641. if (cap->channels != channels)
  1642. return -1;
  1643. /* all channels are remappable freely */
  1644. return SNDRV_CTL_TLVT_CHMAP_VAR;
  1645. }
  1646. static void hdmi_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
  1647. unsigned int *chmap, int channels)
  1648. {
  1649. int count = 0;
  1650. int c;
  1651. for (c = 7; c >= 0; c--) {
  1652. int spk = cap->speakers[c];
  1653. if (!spk)
  1654. continue;
  1655. chmap[count++] = spk_to_chmap(spk);
  1656. }
  1657. WARN_ON(count != channels);
  1658. }
  1659. static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
  1660. unsigned int size, unsigned int __user *tlv)
  1661. {
  1662. struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
  1663. struct hda_codec *codec = info->private_data;
  1664. struct hdmi_spec *spec = codec->spec;
  1665. unsigned int __user *dst;
  1666. int chs, count = 0;
  1667. if (size < 8)
  1668. return -ENOMEM;
  1669. if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
  1670. return -EFAULT;
  1671. size -= 8;
  1672. dst = tlv + 2;
  1673. for (chs = 2; chs <= spec->channels_max; chs++) {
  1674. int i;
  1675. struct cea_channel_speaker_allocation *cap;
  1676. cap = channel_allocations;
  1677. for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
  1678. int chs_bytes = chs * 4;
  1679. int type = spec->ops.chmap_cea_alloc_validate_get_type(cap, chs);
  1680. unsigned int tlv_chmap[8];
  1681. if (type < 0)
  1682. continue;
  1683. if (size < 8)
  1684. return -ENOMEM;
  1685. if (put_user(type, dst) ||
  1686. put_user(chs_bytes, dst + 1))
  1687. return -EFAULT;
  1688. dst += 2;
  1689. size -= 8;
  1690. count += 8;
  1691. if (size < chs_bytes)
  1692. return -ENOMEM;
  1693. size -= chs_bytes;
  1694. count += chs_bytes;
  1695. spec->ops.cea_alloc_to_tlv_chmap(cap, tlv_chmap, chs);
  1696. if (copy_to_user(dst, tlv_chmap, chs_bytes))
  1697. return -EFAULT;
  1698. dst += chs;
  1699. }
  1700. }
  1701. if (put_user(count, tlv + 1))
  1702. return -EFAULT;
  1703. return 0;
  1704. }
  1705. static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
  1706. struct snd_ctl_elem_value *ucontrol)
  1707. {
  1708. struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
  1709. struct hda_codec *codec = info->private_data;
  1710. struct hdmi_spec *spec = codec->spec;
  1711. int pin_idx = kcontrol->private_value;
  1712. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  1713. int i;
  1714. for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
  1715. ucontrol->value.integer.value[i] = per_pin->chmap[i];
  1716. return 0;
  1717. }
  1718. static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
  1719. struct snd_ctl_elem_value *ucontrol)
  1720. {
  1721. struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
  1722. struct hda_codec *codec = info->private_data;
  1723. struct hdmi_spec *spec = codec->spec;
  1724. int pin_idx = kcontrol->private_value;
  1725. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  1726. unsigned int ctl_idx;
  1727. struct snd_pcm_substream *substream;
  1728. unsigned char chmap[8];
  1729. int i, err, ca, prepared = 0;
  1730. ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1731. substream = snd_pcm_chmap_substream(info, ctl_idx);
  1732. if (!substream || !substream->runtime)
  1733. return 0; /* just for avoiding error from alsactl restore */
  1734. switch (substream->runtime->status->state) {
  1735. case SNDRV_PCM_STATE_OPEN:
  1736. case SNDRV_PCM_STATE_SETUP:
  1737. break;
  1738. case SNDRV_PCM_STATE_PREPARED:
  1739. prepared = 1;
  1740. break;
  1741. default:
  1742. return -EBUSY;
  1743. }
  1744. memset(chmap, 0, sizeof(chmap));
  1745. for (i = 0; i < ARRAY_SIZE(chmap); i++)
  1746. chmap[i] = ucontrol->value.integer.value[i];
  1747. if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
  1748. return 0;
  1749. ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
  1750. if (ca < 0)
  1751. return -EINVAL;
  1752. if (spec->ops.chmap_validate) {
  1753. err = spec->ops.chmap_validate(ca, ARRAY_SIZE(chmap), chmap);
  1754. if (err)
  1755. return err;
  1756. }
  1757. mutex_lock(&per_pin->lock);
  1758. per_pin->chmap_set = true;
  1759. memcpy(per_pin->chmap, chmap, sizeof(chmap));
  1760. if (prepared)
  1761. hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
  1762. mutex_unlock(&per_pin->lock);
  1763. return 0;
  1764. }
  1765. static int generic_hdmi_build_pcms(struct hda_codec *codec)
  1766. {
  1767. struct hdmi_spec *spec = codec->spec;
  1768. int pin_idx;
  1769. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  1770. struct hda_pcm *info;
  1771. struct hda_pcm_stream *pstr;
  1772. info = snd_hda_codec_pcm_new(codec, "HDMI %d", pin_idx);
  1773. if (!info)
  1774. return -ENOMEM;
  1775. spec->pcm_rec[pin_idx] = info;
  1776. info->pcm_type = HDA_PCM_TYPE_HDMI;
  1777. info->own_chmap = true;
  1778. pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
  1779. pstr->substreams = 1;
  1780. pstr->ops = generic_ops;
  1781. /* other pstr fields are set in open */
  1782. }
  1783. return 0;
  1784. }
  1785. static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
  1786. {
  1787. char hdmi_str[32] = "HDMI/DP";
  1788. struct hdmi_spec *spec = codec->spec;
  1789. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  1790. int pcmdev = get_pcm_rec(spec, pin_idx)->device;
  1791. bool phantom_jack;
  1792. if (pcmdev > 0)
  1793. sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
  1794. phantom_jack = !is_jack_detectable(codec, per_pin->pin_nid);
  1795. if (phantom_jack)
  1796. strncat(hdmi_str, " Phantom",
  1797. sizeof(hdmi_str) - strlen(hdmi_str) - 1);
  1798. return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str,
  1799. phantom_jack);
  1800. }
  1801. static int generic_hdmi_build_controls(struct hda_codec *codec)
  1802. {
  1803. struct hdmi_spec *spec = codec->spec;
  1804. int err;
  1805. int pin_idx;
  1806. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  1807. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  1808. err = generic_hdmi_build_jack(codec, pin_idx);
  1809. if (err < 0)
  1810. return err;
  1811. err = snd_hda_create_dig_out_ctls(codec,
  1812. per_pin->pin_nid,
  1813. per_pin->mux_nids[0],
  1814. HDA_PCM_TYPE_HDMI);
  1815. if (err < 0)
  1816. return err;
  1817. snd_hda_spdif_ctls_unassign(codec, pin_idx);
  1818. /* add control for ELD Bytes */
  1819. err = hdmi_create_eld_ctl(codec, pin_idx,
  1820. get_pcm_rec(spec, pin_idx)->device);
  1821. if (err < 0)
  1822. return err;
  1823. hdmi_present_sense(per_pin, 0);
  1824. }
  1825. /* add channel maps */
  1826. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  1827. struct hda_pcm *pcm;
  1828. struct snd_pcm_chmap *chmap;
  1829. struct snd_kcontrol *kctl;
  1830. int i;
  1831. pcm = spec->pcm_rec[pin_idx];
  1832. if (!pcm || !pcm->pcm)
  1833. break;
  1834. err = snd_pcm_add_chmap_ctls(pcm->pcm,
  1835. SNDRV_PCM_STREAM_PLAYBACK,
  1836. NULL, 0, pin_idx, &chmap);
  1837. if (err < 0)
  1838. return err;
  1839. /* override handlers */
  1840. chmap->private_data = codec;
  1841. kctl = chmap->kctl;
  1842. for (i = 0; i < kctl->count; i++)
  1843. kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
  1844. kctl->info = hdmi_chmap_ctl_info;
  1845. kctl->get = hdmi_chmap_ctl_get;
  1846. kctl->put = hdmi_chmap_ctl_put;
  1847. kctl->tlv.c = hdmi_chmap_ctl_tlv;
  1848. }
  1849. return 0;
  1850. }
  1851. static int generic_hdmi_init_per_pins(struct hda_codec *codec)
  1852. {
  1853. struct hdmi_spec *spec = codec->spec;
  1854. int pin_idx;
  1855. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  1856. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  1857. per_pin->codec = codec;
  1858. mutex_init(&per_pin->lock);
  1859. INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
  1860. eld_proc_new(per_pin, pin_idx);
  1861. }
  1862. return 0;
  1863. }
  1864. static int generic_hdmi_init(struct hda_codec *codec)
  1865. {
  1866. struct hdmi_spec *spec = codec->spec;
  1867. int pin_idx;
  1868. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  1869. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  1870. hda_nid_t pin_nid = per_pin->pin_nid;
  1871. hdmi_init_pin(codec, pin_nid);
  1872. snd_hda_jack_detect_enable_callback(codec, pin_nid,
  1873. codec->jackpoll_interval > 0 ? jack_callback : NULL);
  1874. }
  1875. return 0;
  1876. }
  1877. static void hdmi_array_init(struct hdmi_spec *spec, int nums)
  1878. {
  1879. snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
  1880. snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
  1881. }
  1882. static void hdmi_array_free(struct hdmi_spec *spec)
  1883. {
  1884. snd_array_free(&spec->pins);
  1885. snd_array_free(&spec->cvts);
  1886. }
  1887. static void generic_hdmi_free(struct hda_codec *codec)
  1888. {
  1889. struct hdmi_spec *spec = codec->spec;
  1890. int pin_idx;
  1891. if (is_haswell_plus(codec) || is_valleyview_plus(codec))
  1892. snd_hdac_i915_register_notifier(NULL);
  1893. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  1894. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  1895. cancel_delayed_work_sync(&per_pin->work);
  1896. eld_proc_free(per_pin);
  1897. }
  1898. hdmi_array_free(spec);
  1899. kfree(spec);
  1900. }
  1901. #ifdef CONFIG_PM
  1902. static int generic_hdmi_resume(struct hda_codec *codec)
  1903. {
  1904. struct hdmi_spec *spec = codec->spec;
  1905. int pin_idx;
  1906. codec->patch_ops.init(codec);
  1907. regcache_sync(codec->core.regmap);
  1908. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  1909. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  1910. hdmi_present_sense(per_pin, 1);
  1911. }
  1912. return 0;
  1913. }
  1914. #endif
  1915. static const struct hda_codec_ops generic_hdmi_patch_ops = {
  1916. .init = generic_hdmi_init,
  1917. .free = generic_hdmi_free,
  1918. .build_pcms = generic_hdmi_build_pcms,
  1919. .build_controls = generic_hdmi_build_controls,
  1920. .unsol_event = hdmi_unsol_event,
  1921. #ifdef CONFIG_PM
  1922. .resume = generic_hdmi_resume,
  1923. #endif
  1924. };
  1925. static const struct hdmi_ops generic_standard_hdmi_ops = {
  1926. .pin_get_eld = snd_hdmi_get_eld,
  1927. .pin_get_slot_channel = hdmi_pin_get_slot_channel,
  1928. .pin_set_slot_channel = hdmi_pin_set_slot_channel,
  1929. .pin_setup_infoframe = hdmi_pin_setup_infoframe,
  1930. .pin_hbr_setup = hdmi_pin_hbr_setup,
  1931. .setup_stream = hdmi_setup_stream,
  1932. .chmap_cea_alloc_validate_get_type = hdmi_chmap_cea_alloc_validate_get_type,
  1933. .cea_alloc_to_tlv_chmap = hdmi_cea_alloc_to_tlv_chmap,
  1934. };
  1935. static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
  1936. hda_nid_t nid)
  1937. {
  1938. struct hdmi_spec *spec = codec->spec;
  1939. hda_nid_t conns[4];
  1940. int nconns;
  1941. nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
  1942. if (nconns == spec->num_cvts &&
  1943. !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
  1944. return;
  1945. /* override pins connection list */
  1946. codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
  1947. snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
  1948. }
  1949. #define INTEL_VENDOR_NID 0x08
  1950. #define INTEL_GET_VENDOR_VERB 0xf81
  1951. #define INTEL_SET_VENDOR_VERB 0x781
  1952. #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */
  1953. #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */
  1954. static void intel_haswell_enable_all_pins(struct hda_codec *codec,
  1955. bool update_tree)
  1956. {
  1957. unsigned int vendor_param;
  1958. vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
  1959. INTEL_GET_VENDOR_VERB, 0);
  1960. if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
  1961. return;
  1962. vendor_param |= INTEL_EN_ALL_PIN_CVTS;
  1963. vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
  1964. INTEL_SET_VENDOR_VERB, vendor_param);
  1965. if (vendor_param == -1)
  1966. return;
  1967. if (update_tree)
  1968. snd_hda_codec_update_widgets(codec);
  1969. }
  1970. static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
  1971. {
  1972. unsigned int vendor_param;
  1973. vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
  1974. INTEL_GET_VENDOR_VERB, 0);
  1975. if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
  1976. return;
  1977. /* enable DP1.2 mode */
  1978. vendor_param |= INTEL_EN_DP12;
  1979. snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
  1980. snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
  1981. INTEL_SET_VENDOR_VERB, vendor_param);
  1982. }
  1983. /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
  1984. * Otherwise you may get severe h/w communication errors.
  1985. */
  1986. static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
  1987. unsigned int power_state)
  1988. {
  1989. if (power_state == AC_PWRST_D0) {
  1990. intel_haswell_enable_all_pins(codec, false);
  1991. intel_haswell_fixup_enable_dp12(codec);
  1992. }
  1993. snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
  1994. snd_hda_codec_set_power_to_all(codec, fg, power_state);
  1995. }
  1996. static void intel_pin_eld_notify(void *audio_ptr, int port)
  1997. {
  1998. struct hda_codec *codec = audio_ptr;
  1999. int pin_nid = port + 0x04;
  2000. /* we assume only from port-B to port-D */
  2001. if (port < 1 || port > 3)
  2002. return;
  2003. /* skip notification during system suspend (but not in runtime PM);
  2004. * the state will be updated at resume
  2005. */
  2006. if (snd_power_get_state(codec->card) != SNDRV_CTL_POWER_D0)
  2007. return;
  2008. check_presence_and_report(codec, pin_nid);
  2009. }
  2010. static int patch_generic_hdmi(struct hda_codec *codec)
  2011. {
  2012. struct hdmi_spec *spec;
  2013. spec = kzalloc(sizeof(*spec), GFP_KERNEL);
  2014. if (spec == NULL)
  2015. return -ENOMEM;
  2016. spec->ops = generic_standard_hdmi_ops;
  2017. codec->spec = spec;
  2018. hdmi_array_init(spec, 4);
  2019. if (is_haswell_plus(codec)) {
  2020. intel_haswell_enable_all_pins(codec, true);
  2021. intel_haswell_fixup_enable_dp12(codec);
  2022. }
  2023. /* For Valleyview/Cherryview, only the display codec is in the display
  2024. * power well and can use link_power ops to request/release the power.
  2025. * For Haswell/Broadwell, the controller is also in the power well and
  2026. * can cover the codec power request, and so need not set this flag.
  2027. * For previous platforms, there is no such power well feature.
  2028. */
  2029. if (is_valleyview_plus(codec) || is_skylake(codec) ||
  2030. is_broxton(codec))
  2031. codec->core.link_power_control = 1;
  2032. if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
  2033. codec->depop_delay = 0;
  2034. spec->i915_audio_ops.audio_ptr = codec;
  2035. spec->i915_audio_ops.pin_eld_notify = intel_pin_eld_notify;
  2036. snd_hdac_i915_register_notifier(&spec->i915_audio_ops);
  2037. }
  2038. if (hdmi_parse_codec(codec) < 0) {
  2039. codec->spec = NULL;
  2040. kfree(spec);
  2041. return -EINVAL;
  2042. }
  2043. codec->patch_ops = generic_hdmi_patch_ops;
  2044. if (is_haswell_plus(codec)) {
  2045. codec->patch_ops.set_power_state = haswell_set_power_state;
  2046. codec->dp_mst = true;
  2047. }
  2048. /* Enable runtime pm for HDMI audio codec of HSW/BDW/SKL/BYT/BSW */
  2049. if (is_haswell_plus(codec) || is_valleyview_plus(codec))
  2050. codec->auto_runtime_pm = 1;
  2051. generic_hdmi_init_per_pins(codec);
  2052. init_channel_allocations();
  2053. return 0;
  2054. }
  2055. /*
  2056. * Shared non-generic implementations
  2057. */
  2058. static int simple_playback_build_pcms(struct hda_codec *codec)
  2059. {
  2060. struct hdmi_spec *spec = codec->spec;
  2061. struct hda_pcm *info;
  2062. unsigned int chans;
  2063. struct hda_pcm_stream *pstr;
  2064. struct hdmi_spec_per_cvt *per_cvt;
  2065. per_cvt = get_cvt(spec, 0);
  2066. chans = get_wcaps(codec, per_cvt->cvt_nid);
  2067. chans = get_wcaps_channels(chans);
  2068. info = snd_hda_codec_pcm_new(codec, "HDMI 0");
  2069. if (!info)
  2070. return -ENOMEM;
  2071. spec->pcm_rec[0] = info;
  2072. info->pcm_type = HDA_PCM_TYPE_HDMI;
  2073. pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
  2074. *pstr = spec->pcm_playback;
  2075. pstr->nid = per_cvt->cvt_nid;
  2076. if (pstr->channels_max <= 2 && chans && chans <= 16)
  2077. pstr->channels_max = chans;
  2078. return 0;
  2079. }
  2080. /* unsolicited event for jack sensing */
  2081. static void simple_hdmi_unsol_event(struct hda_codec *codec,
  2082. unsigned int res)
  2083. {
  2084. snd_hda_jack_set_dirty_all(codec);
  2085. snd_hda_jack_report_sync(codec);
  2086. }
  2087. /* generic_hdmi_build_jack can be used for simple_hdmi, too,
  2088. * as long as spec->pins[] is set correctly
  2089. */
  2090. #define simple_hdmi_build_jack generic_hdmi_build_jack
  2091. static int simple_playback_build_controls(struct hda_codec *codec)
  2092. {
  2093. struct hdmi_spec *spec = codec->spec;
  2094. struct hdmi_spec_per_cvt *per_cvt;
  2095. int err;
  2096. per_cvt = get_cvt(spec, 0);
  2097. err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
  2098. per_cvt->cvt_nid,
  2099. HDA_PCM_TYPE_HDMI);
  2100. if (err < 0)
  2101. return err;
  2102. return simple_hdmi_build_jack(codec, 0);
  2103. }
  2104. static int simple_playback_init(struct hda_codec *codec)
  2105. {
  2106. struct hdmi_spec *spec = codec->spec;
  2107. struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
  2108. hda_nid_t pin = per_pin->pin_nid;
  2109. snd_hda_codec_write(codec, pin, 0,
  2110. AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
  2111. /* some codecs require to unmute the pin */
  2112. if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
  2113. snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
  2114. AMP_OUT_UNMUTE);
  2115. snd_hda_jack_detect_enable(codec, pin);
  2116. return 0;
  2117. }
  2118. static void simple_playback_free(struct hda_codec *codec)
  2119. {
  2120. struct hdmi_spec *spec = codec->spec;
  2121. hdmi_array_free(spec);
  2122. kfree(spec);
  2123. }
  2124. /*
  2125. * Nvidia specific implementations
  2126. */
  2127. #define Nv_VERB_SET_Channel_Allocation 0xF79
  2128. #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
  2129. #define Nv_VERB_SET_Audio_Protection_On 0xF98
  2130. #define Nv_VERB_SET_Audio_Protection_Off 0xF99
  2131. #define nvhdmi_master_con_nid_7x 0x04
  2132. #define nvhdmi_master_pin_nid_7x 0x05
  2133. static const hda_nid_t nvhdmi_con_nids_7x[4] = {
  2134. /*front, rear, clfe, rear_surr */
  2135. 0x6, 0x8, 0xa, 0xc,
  2136. };
  2137. static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
  2138. /* set audio protect on */
  2139. { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
  2140. /* enable digital output on pin widget */
  2141. { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  2142. {} /* terminator */
  2143. };
  2144. static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
  2145. /* set audio protect on */
  2146. { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
  2147. /* enable digital output on pin widget */
  2148. { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  2149. { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  2150. { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  2151. { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  2152. { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  2153. {} /* terminator */
  2154. };
  2155. #ifdef LIMITED_RATE_FMT_SUPPORT
  2156. /* support only the safe format and rate */
  2157. #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
  2158. #define SUPPORTED_MAXBPS 16
  2159. #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
  2160. #else
  2161. /* support all rates and formats */
  2162. #define SUPPORTED_RATES \
  2163. (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
  2164. SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
  2165. SNDRV_PCM_RATE_192000)
  2166. #define SUPPORTED_MAXBPS 24
  2167. #define SUPPORTED_FORMATS \
  2168. (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
  2169. #endif
  2170. static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
  2171. {
  2172. snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
  2173. return 0;
  2174. }
  2175. static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
  2176. {
  2177. snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
  2178. return 0;
  2179. }
  2180. static unsigned int channels_2_6_8[] = {
  2181. 2, 6, 8
  2182. };
  2183. static unsigned int channels_2_8[] = {
  2184. 2, 8
  2185. };
  2186. static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
  2187. .count = ARRAY_SIZE(channels_2_6_8),
  2188. .list = channels_2_6_8,
  2189. .mask = 0,
  2190. };
  2191. static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
  2192. .count = ARRAY_SIZE(channels_2_8),
  2193. .list = channels_2_8,
  2194. .mask = 0,
  2195. };
  2196. static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
  2197. struct hda_codec *codec,
  2198. struct snd_pcm_substream *substream)
  2199. {
  2200. struct hdmi_spec *spec = codec->spec;
  2201. struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
  2202. switch (codec->preset->vendor_id) {
  2203. case 0x10de0002:
  2204. case 0x10de0003:
  2205. case 0x10de0005:
  2206. case 0x10de0006:
  2207. hw_constraints_channels = &hw_constraints_2_8_channels;
  2208. break;
  2209. case 0x10de0007:
  2210. hw_constraints_channels = &hw_constraints_2_6_8_channels;
  2211. break;
  2212. default:
  2213. break;
  2214. }
  2215. if (hw_constraints_channels != NULL) {
  2216. snd_pcm_hw_constraint_list(substream->runtime, 0,
  2217. SNDRV_PCM_HW_PARAM_CHANNELS,
  2218. hw_constraints_channels);
  2219. } else {
  2220. snd_pcm_hw_constraint_step(substream->runtime, 0,
  2221. SNDRV_PCM_HW_PARAM_CHANNELS, 2);
  2222. }
  2223. return snd_hda_multi_out_dig_open(codec, &spec->multiout);
  2224. }
  2225. static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
  2226. struct hda_codec *codec,
  2227. struct snd_pcm_substream *substream)
  2228. {
  2229. struct hdmi_spec *spec = codec->spec;
  2230. return snd_hda_multi_out_dig_close(codec, &spec->multiout);
  2231. }
  2232. static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
  2233. struct hda_codec *codec,
  2234. unsigned int stream_tag,
  2235. unsigned int format,
  2236. struct snd_pcm_substream *substream)
  2237. {
  2238. struct hdmi_spec *spec = codec->spec;
  2239. return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
  2240. stream_tag, format, substream);
  2241. }
  2242. static const struct hda_pcm_stream simple_pcm_playback = {
  2243. .substreams = 1,
  2244. .channels_min = 2,
  2245. .channels_max = 2,
  2246. .ops = {
  2247. .open = simple_playback_pcm_open,
  2248. .close = simple_playback_pcm_close,
  2249. .prepare = simple_playback_pcm_prepare
  2250. },
  2251. };
  2252. static const struct hda_codec_ops simple_hdmi_patch_ops = {
  2253. .build_controls = simple_playback_build_controls,
  2254. .build_pcms = simple_playback_build_pcms,
  2255. .init = simple_playback_init,
  2256. .free = simple_playback_free,
  2257. .unsol_event = simple_hdmi_unsol_event,
  2258. };
  2259. static int patch_simple_hdmi(struct hda_codec *codec,
  2260. hda_nid_t cvt_nid, hda_nid_t pin_nid)
  2261. {
  2262. struct hdmi_spec *spec;
  2263. struct hdmi_spec_per_cvt *per_cvt;
  2264. struct hdmi_spec_per_pin *per_pin;
  2265. spec = kzalloc(sizeof(*spec), GFP_KERNEL);
  2266. if (!spec)
  2267. return -ENOMEM;
  2268. codec->spec = spec;
  2269. hdmi_array_init(spec, 1);
  2270. spec->multiout.num_dacs = 0; /* no analog */
  2271. spec->multiout.max_channels = 2;
  2272. spec->multiout.dig_out_nid = cvt_nid;
  2273. spec->num_cvts = 1;
  2274. spec->num_pins = 1;
  2275. per_pin = snd_array_new(&spec->pins);
  2276. per_cvt = snd_array_new(&spec->cvts);
  2277. if (!per_pin || !per_cvt) {
  2278. simple_playback_free(codec);
  2279. return -ENOMEM;
  2280. }
  2281. per_cvt->cvt_nid = cvt_nid;
  2282. per_pin->pin_nid = pin_nid;
  2283. spec->pcm_playback = simple_pcm_playback;
  2284. codec->patch_ops = simple_hdmi_patch_ops;
  2285. return 0;
  2286. }
  2287. static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
  2288. int channels)
  2289. {
  2290. unsigned int chanmask;
  2291. int chan = channels ? (channels - 1) : 1;
  2292. switch (channels) {
  2293. default:
  2294. case 0:
  2295. case 2:
  2296. chanmask = 0x00;
  2297. break;
  2298. case 4:
  2299. chanmask = 0x08;
  2300. break;
  2301. case 6:
  2302. chanmask = 0x0b;
  2303. break;
  2304. case 8:
  2305. chanmask = 0x13;
  2306. break;
  2307. }
  2308. /* Set the audio infoframe channel allocation and checksum fields. The
  2309. * channel count is computed implicitly by the hardware. */
  2310. snd_hda_codec_write(codec, 0x1, 0,
  2311. Nv_VERB_SET_Channel_Allocation, chanmask);
  2312. snd_hda_codec_write(codec, 0x1, 0,
  2313. Nv_VERB_SET_Info_Frame_Checksum,
  2314. (0x71 - chan - chanmask));
  2315. }
  2316. static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
  2317. struct hda_codec *codec,
  2318. struct snd_pcm_substream *substream)
  2319. {
  2320. struct hdmi_spec *spec = codec->spec;
  2321. int i;
  2322. snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
  2323. 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
  2324. for (i = 0; i < 4; i++) {
  2325. /* set the stream id */
  2326. snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
  2327. AC_VERB_SET_CHANNEL_STREAMID, 0);
  2328. /* set the stream format */
  2329. snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
  2330. AC_VERB_SET_STREAM_FORMAT, 0);
  2331. }
  2332. /* The audio hardware sends a channel count of 0x7 (8ch) when all the
  2333. * streams are disabled. */
  2334. nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
  2335. return snd_hda_multi_out_dig_close(codec, &spec->multiout);
  2336. }
  2337. static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
  2338. struct hda_codec *codec,
  2339. unsigned int stream_tag,
  2340. unsigned int format,
  2341. struct snd_pcm_substream *substream)
  2342. {
  2343. int chs;
  2344. unsigned int dataDCC2, channel_id;
  2345. int i;
  2346. struct hdmi_spec *spec = codec->spec;
  2347. struct hda_spdif_out *spdif;
  2348. struct hdmi_spec_per_cvt *per_cvt;
  2349. mutex_lock(&codec->spdif_mutex);
  2350. per_cvt = get_cvt(spec, 0);
  2351. spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
  2352. chs = substream->runtime->channels;
  2353. dataDCC2 = 0x2;
  2354. /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
  2355. if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
  2356. snd_hda_codec_write(codec,
  2357. nvhdmi_master_con_nid_7x,
  2358. 0,
  2359. AC_VERB_SET_DIGI_CONVERT_1,
  2360. spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
  2361. /* set the stream id */
  2362. snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
  2363. AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
  2364. /* set the stream format */
  2365. snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
  2366. AC_VERB_SET_STREAM_FORMAT, format);
  2367. /* turn on again (if needed) */
  2368. /* enable and set the channel status audio/data flag */
  2369. if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
  2370. snd_hda_codec_write(codec,
  2371. nvhdmi_master_con_nid_7x,
  2372. 0,
  2373. AC_VERB_SET_DIGI_CONVERT_1,
  2374. spdif->ctls & 0xff);
  2375. snd_hda_codec_write(codec,
  2376. nvhdmi_master_con_nid_7x,
  2377. 0,
  2378. AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
  2379. }
  2380. for (i = 0; i < 4; i++) {
  2381. if (chs == 2)
  2382. channel_id = 0;
  2383. else
  2384. channel_id = i * 2;
  2385. /* turn off SPDIF once;
  2386. *otherwise the IEC958 bits won't be updated
  2387. */
  2388. if (codec->spdif_status_reset &&
  2389. (spdif->ctls & AC_DIG1_ENABLE))
  2390. snd_hda_codec_write(codec,
  2391. nvhdmi_con_nids_7x[i],
  2392. 0,
  2393. AC_VERB_SET_DIGI_CONVERT_1,
  2394. spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
  2395. /* set the stream id */
  2396. snd_hda_codec_write(codec,
  2397. nvhdmi_con_nids_7x[i],
  2398. 0,
  2399. AC_VERB_SET_CHANNEL_STREAMID,
  2400. (stream_tag << 4) | channel_id);
  2401. /* set the stream format */
  2402. snd_hda_codec_write(codec,
  2403. nvhdmi_con_nids_7x[i],
  2404. 0,
  2405. AC_VERB_SET_STREAM_FORMAT,
  2406. format);
  2407. /* turn on again (if needed) */
  2408. /* enable and set the channel status audio/data flag */
  2409. if (codec->spdif_status_reset &&
  2410. (spdif->ctls & AC_DIG1_ENABLE)) {
  2411. snd_hda_codec_write(codec,
  2412. nvhdmi_con_nids_7x[i],
  2413. 0,
  2414. AC_VERB_SET_DIGI_CONVERT_1,
  2415. spdif->ctls & 0xff);
  2416. snd_hda_codec_write(codec,
  2417. nvhdmi_con_nids_7x[i],
  2418. 0,
  2419. AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
  2420. }
  2421. }
  2422. nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
  2423. mutex_unlock(&codec->spdif_mutex);
  2424. return 0;
  2425. }
  2426. static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
  2427. .substreams = 1,
  2428. .channels_min = 2,
  2429. .channels_max = 8,
  2430. .nid = nvhdmi_master_con_nid_7x,
  2431. .rates = SUPPORTED_RATES,
  2432. .maxbps = SUPPORTED_MAXBPS,
  2433. .formats = SUPPORTED_FORMATS,
  2434. .ops = {
  2435. .open = simple_playback_pcm_open,
  2436. .close = nvhdmi_8ch_7x_pcm_close,
  2437. .prepare = nvhdmi_8ch_7x_pcm_prepare
  2438. },
  2439. };
  2440. static int patch_nvhdmi_2ch(struct hda_codec *codec)
  2441. {
  2442. struct hdmi_spec *spec;
  2443. int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
  2444. nvhdmi_master_pin_nid_7x);
  2445. if (err < 0)
  2446. return err;
  2447. codec->patch_ops.init = nvhdmi_7x_init_2ch;
  2448. /* override the PCM rates, etc, as the codec doesn't give full list */
  2449. spec = codec->spec;
  2450. spec->pcm_playback.rates = SUPPORTED_RATES;
  2451. spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
  2452. spec->pcm_playback.formats = SUPPORTED_FORMATS;
  2453. return 0;
  2454. }
  2455. static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
  2456. {
  2457. struct hdmi_spec *spec = codec->spec;
  2458. int err = simple_playback_build_pcms(codec);
  2459. if (!err) {
  2460. struct hda_pcm *info = get_pcm_rec(spec, 0);
  2461. info->own_chmap = true;
  2462. }
  2463. return err;
  2464. }
  2465. static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
  2466. {
  2467. struct hdmi_spec *spec = codec->spec;
  2468. struct hda_pcm *info;
  2469. struct snd_pcm_chmap *chmap;
  2470. int err;
  2471. err = simple_playback_build_controls(codec);
  2472. if (err < 0)
  2473. return err;
  2474. /* add channel maps */
  2475. info = get_pcm_rec(spec, 0);
  2476. err = snd_pcm_add_chmap_ctls(info->pcm,
  2477. SNDRV_PCM_STREAM_PLAYBACK,
  2478. snd_pcm_alt_chmaps, 8, 0, &chmap);
  2479. if (err < 0)
  2480. return err;
  2481. switch (codec->preset->vendor_id) {
  2482. case 0x10de0002:
  2483. case 0x10de0003:
  2484. case 0x10de0005:
  2485. case 0x10de0006:
  2486. chmap->channel_mask = (1U << 2) | (1U << 8);
  2487. break;
  2488. case 0x10de0007:
  2489. chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
  2490. }
  2491. return 0;
  2492. }
  2493. static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
  2494. {
  2495. struct hdmi_spec *spec;
  2496. int err = patch_nvhdmi_2ch(codec);
  2497. if (err < 0)
  2498. return err;
  2499. spec = codec->spec;
  2500. spec->multiout.max_channels = 8;
  2501. spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
  2502. codec->patch_ops.init = nvhdmi_7x_init_8ch;
  2503. codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
  2504. codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
  2505. /* Initialize the audio infoframe channel mask and checksum to something
  2506. * valid */
  2507. nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
  2508. return 0;
  2509. }
  2510. /*
  2511. * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
  2512. * - 0x10de0015
  2513. * - 0x10de0040
  2514. */
  2515. static int nvhdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
  2516. int channels)
  2517. {
  2518. if (cap->ca_index == 0x00 && channels == 2)
  2519. return SNDRV_CTL_TLVT_CHMAP_FIXED;
  2520. return hdmi_chmap_cea_alloc_validate_get_type(cap, channels);
  2521. }
  2522. static int nvhdmi_chmap_validate(int ca, int chs, unsigned char *map)
  2523. {
  2524. if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
  2525. return -EINVAL;
  2526. return 0;
  2527. }
  2528. static int patch_nvhdmi(struct hda_codec *codec)
  2529. {
  2530. struct hdmi_spec *spec;
  2531. int err;
  2532. err = patch_generic_hdmi(codec);
  2533. if (err)
  2534. return err;
  2535. spec = codec->spec;
  2536. spec->dyn_pin_out = true;
  2537. spec->ops.chmap_cea_alloc_validate_get_type =
  2538. nvhdmi_chmap_cea_alloc_validate_get_type;
  2539. spec->ops.chmap_validate = nvhdmi_chmap_validate;
  2540. return 0;
  2541. }
  2542. /*
  2543. * The HDA codec on NVIDIA Tegra contains two scratch registers that are
  2544. * accessed using vendor-defined verbs. These registers can be used for
  2545. * interoperability between the HDA and HDMI drivers.
  2546. */
  2547. /* Audio Function Group node */
  2548. #define NVIDIA_AFG_NID 0x01
  2549. /*
  2550. * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
  2551. * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
  2552. * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
  2553. * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
  2554. * additional bit (at position 30) to signal the validity of the format.
  2555. *
  2556. * | 31 | 30 | 29 16 | 15 0 |
  2557. * +---------+-------+--------+--------+
  2558. * | TRIGGER | VALID | UNUSED | FORMAT |
  2559. * +-----------------------------------|
  2560. *
  2561. * Note that for the trigger bit to take effect it needs to change value
  2562. * (i.e. it needs to be toggled).
  2563. */
  2564. #define NVIDIA_GET_SCRATCH0 0xfa6
  2565. #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7
  2566. #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8
  2567. #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9
  2568. #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa
  2569. #define NVIDIA_SCRATCH_TRIGGER (1 << 7)
  2570. #define NVIDIA_SCRATCH_VALID (1 << 6)
  2571. #define NVIDIA_GET_SCRATCH1 0xfab
  2572. #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac
  2573. #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad
  2574. #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae
  2575. #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf
  2576. /*
  2577. * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
  2578. * the format is invalidated so that the HDMI codec can be disabled.
  2579. */
  2580. static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
  2581. {
  2582. unsigned int value;
  2583. /* bits [31:30] contain the trigger and valid bits */
  2584. value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
  2585. NVIDIA_GET_SCRATCH0, 0);
  2586. value = (value >> 24) & 0xff;
  2587. /* bits [15:0] are used to store the HDA format */
  2588. snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
  2589. NVIDIA_SET_SCRATCH0_BYTE0,
  2590. (format >> 0) & 0xff);
  2591. snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
  2592. NVIDIA_SET_SCRATCH0_BYTE1,
  2593. (format >> 8) & 0xff);
  2594. /* bits [16:24] are unused */
  2595. snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
  2596. NVIDIA_SET_SCRATCH0_BYTE2, 0);
  2597. /*
  2598. * Bit 30 signals that the data is valid and hence that HDMI audio can
  2599. * be enabled.
  2600. */
  2601. if (format == 0)
  2602. value &= ~NVIDIA_SCRATCH_VALID;
  2603. else
  2604. value |= NVIDIA_SCRATCH_VALID;
  2605. /*
  2606. * Whenever the trigger bit is toggled, an interrupt is raised in the
  2607. * HDMI codec. The HDMI driver will use that as trigger to update its
  2608. * configuration.
  2609. */
  2610. value ^= NVIDIA_SCRATCH_TRIGGER;
  2611. snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
  2612. NVIDIA_SET_SCRATCH0_BYTE3, value);
  2613. }
  2614. static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
  2615. struct hda_codec *codec,
  2616. unsigned int stream_tag,
  2617. unsigned int format,
  2618. struct snd_pcm_substream *substream)
  2619. {
  2620. int err;
  2621. err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
  2622. format, substream);
  2623. if (err < 0)
  2624. return err;
  2625. /* notify the HDMI codec of the format change */
  2626. tegra_hdmi_set_format(codec, format);
  2627. return 0;
  2628. }
  2629. static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
  2630. struct hda_codec *codec,
  2631. struct snd_pcm_substream *substream)
  2632. {
  2633. /* invalidate the format in the HDMI codec */
  2634. tegra_hdmi_set_format(codec, 0);
  2635. return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
  2636. }
  2637. static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
  2638. {
  2639. struct hdmi_spec *spec = codec->spec;
  2640. unsigned int i;
  2641. for (i = 0; i < spec->num_pins; i++) {
  2642. struct hda_pcm *pcm = get_pcm_rec(spec, i);
  2643. if (pcm->pcm_type == type)
  2644. return pcm;
  2645. }
  2646. return NULL;
  2647. }
  2648. static int tegra_hdmi_build_pcms(struct hda_codec *codec)
  2649. {
  2650. struct hda_pcm_stream *stream;
  2651. struct hda_pcm *pcm;
  2652. int err;
  2653. err = generic_hdmi_build_pcms(codec);
  2654. if (err < 0)
  2655. return err;
  2656. pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
  2657. if (!pcm)
  2658. return -ENODEV;
  2659. /*
  2660. * Override ->prepare() and ->cleanup() operations to notify the HDMI
  2661. * codec about format changes.
  2662. */
  2663. stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
  2664. stream->ops.prepare = tegra_hdmi_pcm_prepare;
  2665. stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
  2666. return 0;
  2667. }
  2668. static int patch_tegra_hdmi(struct hda_codec *codec)
  2669. {
  2670. int err;
  2671. err = patch_generic_hdmi(codec);
  2672. if (err)
  2673. return err;
  2674. codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
  2675. return 0;
  2676. }
  2677. /*
  2678. * ATI/AMD-specific implementations
  2679. */
  2680. #define is_amdhdmi_rev3_or_later(codec) \
  2681. ((codec)->core.vendor_id == 0x1002aa01 && \
  2682. ((codec)->core.revision_id & 0xff00) >= 0x0300)
  2683. #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
  2684. /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
  2685. #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771
  2686. #define ATI_VERB_SET_DOWNMIX_INFO 0x772
  2687. #define ATI_VERB_SET_MULTICHANNEL_01 0x777
  2688. #define ATI_VERB_SET_MULTICHANNEL_23 0x778
  2689. #define ATI_VERB_SET_MULTICHANNEL_45 0x779
  2690. #define ATI_VERB_SET_MULTICHANNEL_67 0x77a
  2691. #define ATI_VERB_SET_HBR_CONTROL 0x77c
  2692. #define ATI_VERB_SET_MULTICHANNEL_1 0x785
  2693. #define ATI_VERB_SET_MULTICHANNEL_3 0x786
  2694. #define ATI_VERB_SET_MULTICHANNEL_5 0x787
  2695. #define ATI_VERB_SET_MULTICHANNEL_7 0x788
  2696. #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789
  2697. #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71
  2698. #define ATI_VERB_GET_DOWNMIX_INFO 0xf72
  2699. #define ATI_VERB_GET_MULTICHANNEL_01 0xf77
  2700. #define ATI_VERB_GET_MULTICHANNEL_23 0xf78
  2701. #define ATI_VERB_GET_MULTICHANNEL_45 0xf79
  2702. #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a
  2703. #define ATI_VERB_GET_HBR_CONTROL 0xf7c
  2704. #define ATI_VERB_GET_MULTICHANNEL_1 0xf85
  2705. #define ATI_VERB_GET_MULTICHANNEL_3 0xf86
  2706. #define ATI_VERB_GET_MULTICHANNEL_5 0xf87
  2707. #define ATI_VERB_GET_MULTICHANNEL_7 0xf88
  2708. #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89
  2709. /* AMD specific HDA cvt verbs */
  2710. #define ATI_VERB_SET_RAMP_RATE 0x770
  2711. #define ATI_VERB_GET_RAMP_RATE 0xf70
  2712. #define ATI_OUT_ENABLE 0x1
  2713. #define ATI_MULTICHANNEL_MODE_PAIRED 0
  2714. #define ATI_MULTICHANNEL_MODE_SINGLE 1
  2715. #define ATI_HBR_CAPABLE 0x01
  2716. #define ATI_HBR_ENABLE 0x10
  2717. static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
  2718. unsigned char *buf, int *eld_size)
  2719. {
  2720. /* call hda_eld.c ATI/AMD-specific function */
  2721. return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
  2722. is_amdhdmi_rev3_or_later(codec));
  2723. }
  2724. static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
  2725. int active_channels, int conn_type)
  2726. {
  2727. snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
  2728. }
  2729. static int atihdmi_paired_swap_fc_lfe(int pos)
  2730. {
  2731. /*
  2732. * ATI/AMD have automatic FC/LFE swap built-in
  2733. * when in pairwise mapping mode.
  2734. */
  2735. switch (pos) {
  2736. /* see channel_allocations[].speakers[] */
  2737. case 2: return 3;
  2738. case 3: return 2;
  2739. default: break;
  2740. }
  2741. return pos;
  2742. }
  2743. static int atihdmi_paired_chmap_validate(int ca, int chs, unsigned char *map)
  2744. {
  2745. struct cea_channel_speaker_allocation *cap;
  2746. int i, j;
  2747. /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
  2748. cap = &channel_allocations[get_channel_allocation_order(ca)];
  2749. for (i = 0; i < chs; ++i) {
  2750. int mask = to_spk_mask(map[i]);
  2751. bool ok = false;
  2752. bool companion_ok = false;
  2753. if (!mask)
  2754. continue;
  2755. for (j = 0 + i % 2; j < 8; j += 2) {
  2756. int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
  2757. if (cap->speakers[chan_idx] == mask) {
  2758. /* channel is in a supported position */
  2759. ok = true;
  2760. if (i % 2 == 0 && i + 1 < chs) {
  2761. /* even channel, check the odd companion */
  2762. int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
  2763. int comp_mask_req = to_spk_mask(map[i+1]);
  2764. int comp_mask_act = cap->speakers[comp_chan_idx];
  2765. if (comp_mask_req == comp_mask_act)
  2766. companion_ok = true;
  2767. else
  2768. return -EINVAL;
  2769. }
  2770. break;
  2771. }
  2772. }
  2773. if (!ok)
  2774. return -EINVAL;
  2775. if (companion_ok)
  2776. i++; /* companion channel already checked */
  2777. }
  2778. return 0;
  2779. }
  2780. static int atihdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
  2781. int hdmi_slot, int stream_channel)
  2782. {
  2783. int verb;
  2784. int ati_channel_setup = 0;
  2785. if (hdmi_slot > 7)
  2786. return -EINVAL;
  2787. if (!has_amd_full_remap_support(codec)) {
  2788. hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
  2789. /* In case this is an odd slot but without stream channel, do not
  2790. * disable the slot since the corresponding even slot could have a
  2791. * channel. In case neither have a channel, the slot pair will be
  2792. * disabled when this function is called for the even slot. */
  2793. if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
  2794. return 0;
  2795. hdmi_slot -= hdmi_slot % 2;
  2796. if (stream_channel != 0xf)
  2797. stream_channel -= stream_channel % 2;
  2798. }
  2799. verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
  2800. /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
  2801. if (stream_channel != 0xf)
  2802. ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
  2803. return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
  2804. }
  2805. static int atihdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
  2806. int asp_slot)
  2807. {
  2808. bool was_odd = false;
  2809. int ati_asp_slot = asp_slot;
  2810. int verb;
  2811. int ati_channel_setup;
  2812. if (asp_slot > 7)
  2813. return -EINVAL;
  2814. if (!has_amd_full_remap_support(codec)) {
  2815. ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
  2816. if (ati_asp_slot % 2 != 0) {
  2817. ati_asp_slot -= 1;
  2818. was_odd = true;
  2819. }
  2820. }
  2821. verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
  2822. ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
  2823. if (!(ati_channel_setup & ATI_OUT_ENABLE))
  2824. return 0xf;
  2825. return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
  2826. }
  2827. static int atihdmi_paired_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
  2828. int channels)
  2829. {
  2830. int c;
  2831. /*
  2832. * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
  2833. * we need to take that into account (a single channel may take 2
  2834. * channel slots if we need to carry a silent channel next to it).
  2835. * On Rev3+ AMD codecs this function is not used.
  2836. */
  2837. int chanpairs = 0;
  2838. /* We only produce even-numbered channel count TLVs */
  2839. if ((channels % 2) != 0)
  2840. return -1;
  2841. for (c = 0; c < 7; c += 2) {
  2842. if (cap->speakers[c] || cap->speakers[c+1])
  2843. chanpairs++;
  2844. }
  2845. if (chanpairs * 2 != channels)
  2846. return -1;
  2847. return SNDRV_CTL_TLVT_CHMAP_PAIRED;
  2848. }
  2849. static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
  2850. unsigned int *chmap, int channels)
  2851. {
  2852. /* produce paired maps for pre-rev3 ATI/AMD codecs */
  2853. int count = 0;
  2854. int c;
  2855. for (c = 7; c >= 0; c--) {
  2856. int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
  2857. int spk = cap->speakers[chan];
  2858. if (!spk) {
  2859. /* add N/A channel if the companion channel is occupied */
  2860. if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
  2861. chmap[count++] = SNDRV_CHMAP_NA;
  2862. continue;
  2863. }
  2864. chmap[count++] = spk_to_chmap(spk);
  2865. }
  2866. WARN_ON(count != channels);
  2867. }
  2868. static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
  2869. bool hbr)
  2870. {
  2871. int hbr_ctl, hbr_ctl_new;
  2872. hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
  2873. if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
  2874. if (hbr)
  2875. hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
  2876. else
  2877. hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
  2878. codec_dbg(codec,
  2879. "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
  2880. pin_nid,
  2881. hbr_ctl == hbr_ctl_new ? "" : "new-",
  2882. hbr_ctl_new);
  2883. if (hbr_ctl != hbr_ctl_new)
  2884. snd_hda_codec_write(codec, pin_nid, 0,
  2885. ATI_VERB_SET_HBR_CONTROL,
  2886. hbr_ctl_new);
  2887. } else if (hbr)
  2888. return -EINVAL;
  2889. return 0;
  2890. }
  2891. static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
  2892. hda_nid_t pin_nid, u32 stream_tag, int format)
  2893. {
  2894. if (is_amdhdmi_rev3_or_later(codec)) {
  2895. int ramp_rate = 180; /* default as per AMD spec */
  2896. /* disable ramp-up/down for non-pcm as per AMD spec */
  2897. if (format & AC_FMT_TYPE_NON_PCM)
  2898. ramp_rate = 0;
  2899. snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
  2900. }
  2901. return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
  2902. }
  2903. static int atihdmi_init(struct hda_codec *codec)
  2904. {
  2905. struct hdmi_spec *spec = codec->spec;
  2906. int pin_idx, err;
  2907. err = generic_hdmi_init(codec);
  2908. if (err)
  2909. return err;
  2910. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  2911. struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
  2912. /* make sure downmix information in infoframe is zero */
  2913. snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
  2914. /* enable channel-wise remap mode if supported */
  2915. if (has_amd_full_remap_support(codec))
  2916. snd_hda_codec_write(codec, per_pin->pin_nid, 0,
  2917. ATI_VERB_SET_MULTICHANNEL_MODE,
  2918. ATI_MULTICHANNEL_MODE_SINGLE);
  2919. }
  2920. return 0;
  2921. }
  2922. static int patch_atihdmi(struct hda_codec *codec)
  2923. {
  2924. struct hdmi_spec *spec;
  2925. struct hdmi_spec_per_cvt *per_cvt;
  2926. int err, cvt_idx;
  2927. err = patch_generic_hdmi(codec);
  2928. if (err)
  2929. return err;
  2930. codec->patch_ops.init = atihdmi_init;
  2931. spec = codec->spec;
  2932. spec->ops.pin_get_eld = atihdmi_pin_get_eld;
  2933. spec->ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
  2934. spec->ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
  2935. spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
  2936. spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
  2937. spec->ops.setup_stream = atihdmi_setup_stream;
  2938. if (!has_amd_full_remap_support(codec)) {
  2939. /* override to ATI/AMD-specific versions with pairwise mapping */
  2940. spec->ops.chmap_cea_alloc_validate_get_type =
  2941. atihdmi_paired_chmap_cea_alloc_validate_get_type;
  2942. spec->ops.cea_alloc_to_tlv_chmap = atihdmi_paired_cea_alloc_to_tlv_chmap;
  2943. spec->ops.chmap_validate = atihdmi_paired_chmap_validate;
  2944. }
  2945. /* ATI/AMD converters do not advertise all of their capabilities */
  2946. for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
  2947. per_cvt = get_cvt(spec, cvt_idx);
  2948. per_cvt->channels_max = max(per_cvt->channels_max, 8u);
  2949. per_cvt->rates |= SUPPORTED_RATES;
  2950. per_cvt->formats |= SUPPORTED_FORMATS;
  2951. per_cvt->maxbps = max(per_cvt->maxbps, 24u);
  2952. }
  2953. spec->channels_max = max(spec->channels_max, 8u);
  2954. return 0;
  2955. }
  2956. /* VIA HDMI Implementation */
  2957. #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */
  2958. #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */
  2959. static int patch_via_hdmi(struct hda_codec *codec)
  2960. {
  2961. return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
  2962. }
  2963. /*
  2964. * patch entries
  2965. */
  2966. static const struct hda_device_id snd_hda_id_hdmi[] = {
  2967. HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi),
  2968. HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi),
  2969. HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi),
  2970. HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi),
  2971. HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi),
  2972. HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi),
  2973. HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi),
  2974. HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
  2975. HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
  2976. HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
  2977. HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x),
  2978. HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x),
  2979. HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi),
  2980. HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi),
  2981. HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi),
  2982. HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi),
  2983. HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi),
  2984. HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi),
  2985. HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi),
  2986. HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi),
  2987. HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi),
  2988. HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi),
  2989. HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi),
  2990. /* 17 is known to be absent */
  2991. HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi),
  2992. HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi),
  2993. HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi),
  2994. HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi),
  2995. HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi),
  2996. HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi),
  2997. HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi),
  2998. HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi),
  2999. HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi),
  3000. HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi),
  3001. HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi),
  3002. HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi),
  3003. HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi),
  3004. HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi),
  3005. HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi),
  3006. HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi),
  3007. HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch),
  3008. HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi),
  3009. HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi),
  3010. HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi),
  3011. HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi),
  3012. HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch),
  3013. HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi),
  3014. HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi),
  3015. HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi),
  3016. HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi),
  3017. HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_generic_hdmi),
  3018. HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi),
  3019. HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi),
  3020. HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi),
  3021. HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_generic_hdmi),
  3022. HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_generic_hdmi),
  3023. HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_generic_hdmi),
  3024. HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_generic_hdmi),
  3025. HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_generic_hdmi),
  3026. HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_generic_hdmi),
  3027. HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_generic_hdmi),
  3028. HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_generic_hdmi),
  3029. HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi),
  3030. HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_generic_hdmi),
  3031. HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_generic_hdmi),
  3032. HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi),
  3033. /* special ID for generic HDMI */
  3034. HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi),
  3035. {} /* terminator */
  3036. };
  3037. MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi);
  3038. MODULE_LICENSE("GPL");
  3039. MODULE_DESCRIPTION("HDMI HD-audio codec");
  3040. MODULE_ALIAS("snd-hda-codec-intelhdmi");
  3041. MODULE_ALIAS("snd-hda-codec-nvhdmi");
  3042. MODULE_ALIAS("snd-hda-codec-atihdmi");
  3043. static struct hda_codec_driver hdmi_driver = {
  3044. .id = snd_hda_id_hdmi,
  3045. };
  3046. module_hda_codec_driver(hdmi_driver);