ice1712.c 83 KB

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  1. /*
  2. * ALSA driver for ICEnsemble ICE1712 (Envy24)
  3. *
  4. * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. *
  20. */
  21. /*
  22. NOTES:
  23. - spdif nonaudio consumer mode does not work (at least with my
  24. Sony STR-DB830)
  25. */
  26. /*
  27. * Changes:
  28. *
  29. * 2002.09.09 Takashi Iwai <tiwai@suse.de>
  30. * split the code to several files. each low-level routine
  31. * is stored in the local file and called from registration
  32. * function from card_info struct.
  33. *
  34. * 2002.11.26 James Stafford <jstafford@ampltd.com>
  35. * Added support for VT1724 (Envy24HT)
  36. * I have left out support for 176.4 and 192 KHz for the moment.
  37. * I also haven't done anything with the internal S/PDIF transmitter or the MPU-401
  38. *
  39. * 2003.02.20 Taksahi Iwai <tiwai@suse.de>
  40. * Split vt1724 part to an independent driver.
  41. * The GPIO is accessed through the callback functions now.
  42. *
  43. * 2004.03.31 Doug McLain <nostar@comcast.net>
  44. * Added support for Event Electronics EZ8 card to hoontech.c.
  45. */
  46. #include <linux/delay.h>
  47. #include <linux/interrupt.h>
  48. #include <linux/init.h>
  49. #include <linux/pci.h>
  50. #include <linux/dma-mapping.h>
  51. #include <linux/slab.h>
  52. #include <linux/module.h>
  53. #include <linux/mutex.h>
  54. #include <sound/core.h>
  55. #include <sound/cs8427.h>
  56. #include <sound/info.h>
  57. #include <sound/initval.h>
  58. #include <sound/tlv.h>
  59. #include <sound/asoundef.h>
  60. #include "ice1712.h"
  61. /* lowlevel routines */
  62. #include "delta.h"
  63. #include "ews.h"
  64. #include "hoontech.h"
  65. MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
  66. MODULE_DESCRIPTION("ICEnsemble ICE1712 (Envy24)");
  67. MODULE_LICENSE("GPL");
  68. MODULE_SUPPORTED_DEVICE("{"
  69. HOONTECH_DEVICE_DESC
  70. DELTA_DEVICE_DESC
  71. EWS_DEVICE_DESC
  72. "{ICEnsemble,Generic ICE1712},"
  73. "{ICEnsemble,Generic Envy24}}");
  74. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  75. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  76. static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
  77. static char *model[SNDRV_CARDS];
  78. static bool omni[SNDRV_CARDS]; /* Delta44 & 66 Omni I/O support */
  79. static int cs8427_timeout[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 500}; /* CS8427 S/PDIF transceiver reset timeout value in msec */
  80. static int dxr_enable[SNDRV_CARDS]; /* DXR enable for DMX6FIRE */
  81. module_param_array(index, int, NULL, 0444);
  82. MODULE_PARM_DESC(index, "Index value for ICE1712 soundcard.");
  83. module_param_array(id, charp, NULL, 0444);
  84. MODULE_PARM_DESC(id, "ID string for ICE1712 soundcard.");
  85. module_param_array(enable, bool, NULL, 0444);
  86. MODULE_PARM_DESC(enable, "Enable ICE1712 soundcard.");
  87. module_param_array(omni, bool, NULL, 0444);
  88. MODULE_PARM_DESC(omni, "Enable Midiman M-Audio Delta Omni I/O support.");
  89. module_param_array(cs8427_timeout, int, NULL, 0444);
  90. MODULE_PARM_DESC(cs8427_timeout, "Define reset timeout for cs8427 chip in msec resolution.");
  91. module_param_array(model, charp, NULL, 0444);
  92. MODULE_PARM_DESC(model, "Use the given board model.");
  93. module_param_array(dxr_enable, int, NULL, 0444);
  94. MODULE_PARM_DESC(dxr_enable, "Enable DXR support for Terratec DMX6FIRE.");
  95. static const struct pci_device_id snd_ice1712_ids[] = {
  96. { PCI_VDEVICE(ICE, PCI_DEVICE_ID_ICE_1712), 0 }, /* ICE1712 */
  97. { 0, }
  98. };
  99. MODULE_DEVICE_TABLE(pci, snd_ice1712_ids);
  100. static int snd_ice1712_build_pro_mixer(struct snd_ice1712 *ice);
  101. static int snd_ice1712_build_controls(struct snd_ice1712 *ice);
  102. static int PRO_RATE_LOCKED;
  103. static int PRO_RATE_RESET = 1;
  104. static unsigned int PRO_RATE_DEFAULT = 44100;
  105. /*
  106. * Basic I/O
  107. */
  108. /* check whether the clock mode is spdif-in */
  109. static inline int is_spdif_master(struct snd_ice1712 *ice)
  110. {
  111. return (inb(ICEMT(ice, RATE)) & ICE1712_SPDIF_MASTER) ? 1 : 0;
  112. }
  113. static inline int is_pro_rate_locked(struct snd_ice1712 *ice)
  114. {
  115. return is_spdif_master(ice) || PRO_RATE_LOCKED;
  116. }
  117. static inline void snd_ice1712_ds_write(struct snd_ice1712 *ice, u8 channel, u8 addr, u32 data)
  118. {
  119. outb((channel << 4) | addr, ICEDS(ice, INDEX));
  120. outl(data, ICEDS(ice, DATA));
  121. }
  122. static inline u32 snd_ice1712_ds_read(struct snd_ice1712 *ice, u8 channel, u8 addr)
  123. {
  124. outb((channel << 4) | addr, ICEDS(ice, INDEX));
  125. return inl(ICEDS(ice, DATA));
  126. }
  127. static void snd_ice1712_ac97_write(struct snd_ac97 *ac97,
  128. unsigned short reg,
  129. unsigned short val)
  130. {
  131. struct snd_ice1712 *ice = ac97->private_data;
  132. int tm;
  133. unsigned char old_cmd = 0;
  134. for (tm = 0; tm < 0x10000; tm++) {
  135. old_cmd = inb(ICEREG(ice, AC97_CMD));
  136. if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
  137. continue;
  138. if (!(old_cmd & ICE1712_AC97_READY))
  139. continue;
  140. break;
  141. }
  142. outb(reg, ICEREG(ice, AC97_INDEX));
  143. outw(val, ICEREG(ice, AC97_DATA));
  144. old_cmd &= ~(ICE1712_AC97_PBK_VSR | ICE1712_AC97_CAP_VSR);
  145. outb(old_cmd | ICE1712_AC97_WRITE, ICEREG(ice, AC97_CMD));
  146. for (tm = 0; tm < 0x10000; tm++)
  147. if ((inb(ICEREG(ice, AC97_CMD)) & ICE1712_AC97_WRITE) == 0)
  148. break;
  149. }
  150. static unsigned short snd_ice1712_ac97_read(struct snd_ac97 *ac97,
  151. unsigned short reg)
  152. {
  153. struct snd_ice1712 *ice = ac97->private_data;
  154. int tm;
  155. unsigned char old_cmd = 0;
  156. for (tm = 0; tm < 0x10000; tm++) {
  157. old_cmd = inb(ICEREG(ice, AC97_CMD));
  158. if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
  159. continue;
  160. if (!(old_cmd & ICE1712_AC97_READY))
  161. continue;
  162. break;
  163. }
  164. outb(reg, ICEREG(ice, AC97_INDEX));
  165. outb(old_cmd | ICE1712_AC97_READ, ICEREG(ice, AC97_CMD));
  166. for (tm = 0; tm < 0x10000; tm++)
  167. if ((inb(ICEREG(ice, AC97_CMD)) & ICE1712_AC97_READ) == 0)
  168. break;
  169. if (tm >= 0x10000) /* timeout */
  170. return ~0;
  171. return inw(ICEREG(ice, AC97_DATA));
  172. }
  173. /*
  174. * pro ac97 section
  175. */
  176. static void snd_ice1712_pro_ac97_write(struct snd_ac97 *ac97,
  177. unsigned short reg,
  178. unsigned short val)
  179. {
  180. struct snd_ice1712 *ice = ac97->private_data;
  181. int tm;
  182. unsigned char old_cmd = 0;
  183. for (tm = 0; tm < 0x10000; tm++) {
  184. old_cmd = inb(ICEMT(ice, AC97_CMD));
  185. if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
  186. continue;
  187. if (!(old_cmd & ICE1712_AC97_READY))
  188. continue;
  189. break;
  190. }
  191. outb(reg, ICEMT(ice, AC97_INDEX));
  192. outw(val, ICEMT(ice, AC97_DATA));
  193. old_cmd &= ~(ICE1712_AC97_PBK_VSR | ICE1712_AC97_CAP_VSR);
  194. outb(old_cmd | ICE1712_AC97_WRITE, ICEMT(ice, AC97_CMD));
  195. for (tm = 0; tm < 0x10000; tm++)
  196. if ((inb(ICEMT(ice, AC97_CMD)) & ICE1712_AC97_WRITE) == 0)
  197. break;
  198. }
  199. static unsigned short snd_ice1712_pro_ac97_read(struct snd_ac97 *ac97,
  200. unsigned short reg)
  201. {
  202. struct snd_ice1712 *ice = ac97->private_data;
  203. int tm;
  204. unsigned char old_cmd = 0;
  205. for (tm = 0; tm < 0x10000; tm++) {
  206. old_cmd = inb(ICEMT(ice, AC97_CMD));
  207. if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
  208. continue;
  209. if (!(old_cmd & ICE1712_AC97_READY))
  210. continue;
  211. break;
  212. }
  213. outb(reg, ICEMT(ice, AC97_INDEX));
  214. outb(old_cmd | ICE1712_AC97_READ, ICEMT(ice, AC97_CMD));
  215. for (tm = 0; tm < 0x10000; tm++)
  216. if ((inb(ICEMT(ice, AC97_CMD)) & ICE1712_AC97_READ) == 0)
  217. break;
  218. if (tm >= 0x10000) /* timeout */
  219. return ~0;
  220. return inw(ICEMT(ice, AC97_DATA));
  221. }
  222. /*
  223. * consumer ac97 digital mix
  224. */
  225. #define snd_ice1712_digmix_route_ac97_info snd_ctl_boolean_mono_info
  226. static int snd_ice1712_digmix_route_ac97_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  227. {
  228. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  229. ucontrol->value.integer.value[0] = inb(ICEMT(ice, MONITOR_ROUTECTRL)) & ICE1712_ROUTE_AC97 ? 1 : 0;
  230. return 0;
  231. }
  232. static int snd_ice1712_digmix_route_ac97_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  233. {
  234. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  235. unsigned char val, nval;
  236. spin_lock_irq(&ice->reg_lock);
  237. val = inb(ICEMT(ice, MONITOR_ROUTECTRL));
  238. nval = val & ~ICE1712_ROUTE_AC97;
  239. if (ucontrol->value.integer.value[0])
  240. nval |= ICE1712_ROUTE_AC97;
  241. outb(nval, ICEMT(ice, MONITOR_ROUTECTRL));
  242. spin_unlock_irq(&ice->reg_lock);
  243. return val != nval;
  244. }
  245. static struct snd_kcontrol_new snd_ice1712_mixer_digmix_route_ac97 = {
  246. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  247. .name = "Digital Mixer To AC97",
  248. .info = snd_ice1712_digmix_route_ac97_info,
  249. .get = snd_ice1712_digmix_route_ac97_get,
  250. .put = snd_ice1712_digmix_route_ac97_put,
  251. };
  252. /*
  253. * gpio operations
  254. */
  255. static void snd_ice1712_set_gpio_dir(struct snd_ice1712 *ice, unsigned int data)
  256. {
  257. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION, data);
  258. inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
  259. }
  260. static unsigned int snd_ice1712_get_gpio_dir(struct snd_ice1712 *ice)
  261. {
  262. return snd_ice1712_read(ice, ICE1712_IREG_GPIO_DIRECTION);
  263. }
  264. static unsigned int snd_ice1712_get_gpio_mask(struct snd_ice1712 *ice)
  265. {
  266. return snd_ice1712_read(ice, ICE1712_IREG_GPIO_WRITE_MASK);
  267. }
  268. static void snd_ice1712_set_gpio_mask(struct snd_ice1712 *ice, unsigned int data)
  269. {
  270. snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, data);
  271. inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
  272. }
  273. static unsigned int snd_ice1712_get_gpio_data(struct snd_ice1712 *ice)
  274. {
  275. return snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA);
  276. }
  277. static void snd_ice1712_set_gpio_data(struct snd_ice1712 *ice, unsigned int val)
  278. {
  279. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, val);
  280. inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
  281. }
  282. /*
  283. *
  284. * CS8427 interface
  285. *
  286. */
  287. /*
  288. * change the input clock selection
  289. * spdif_clock = 1 - IEC958 input, 0 - Envy24
  290. */
  291. static int snd_ice1712_cs8427_set_input_clock(struct snd_ice1712 *ice, int spdif_clock)
  292. {
  293. unsigned char reg[2] = { 0x80 | 4, 0 }; /* CS8427 auto increment | register number 4 + data */
  294. unsigned char val, nval;
  295. int res = 0;
  296. snd_i2c_lock(ice->i2c);
  297. if (snd_i2c_sendbytes(ice->cs8427, reg, 1) != 1) {
  298. snd_i2c_unlock(ice->i2c);
  299. return -EIO;
  300. }
  301. if (snd_i2c_readbytes(ice->cs8427, &val, 1) != 1) {
  302. snd_i2c_unlock(ice->i2c);
  303. return -EIO;
  304. }
  305. nval = val & 0xf0;
  306. if (spdif_clock)
  307. nval |= 0x01;
  308. else
  309. nval |= 0x04;
  310. if (val != nval) {
  311. reg[1] = nval;
  312. if (snd_i2c_sendbytes(ice->cs8427, reg, 2) != 2) {
  313. res = -EIO;
  314. } else {
  315. res++;
  316. }
  317. }
  318. snd_i2c_unlock(ice->i2c);
  319. return res;
  320. }
  321. /*
  322. * spdif callbacks
  323. */
  324. static void open_cs8427(struct snd_ice1712 *ice, struct snd_pcm_substream *substream)
  325. {
  326. snd_cs8427_iec958_active(ice->cs8427, 1);
  327. }
  328. static void close_cs8427(struct snd_ice1712 *ice, struct snd_pcm_substream *substream)
  329. {
  330. snd_cs8427_iec958_active(ice->cs8427, 0);
  331. }
  332. static void setup_cs8427(struct snd_ice1712 *ice, int rate)
  333. {
  334. snd_cs8427_iec958_pcm(ice->cs8427, rate);
  335. }
  336. /*
  337. * create and initialize callbacks for cs8427 interface
  338. */
  339. int snd_ice1712_init_cs8427(struct snd_ice1712 *ice, int addr)
  340. {
  341. int err;
  342. err = snd_cs8427_create(ice->i2c, addr,
  343. (ice->cs8427_timeout * HZ) / 1000, &ice->cs8427);
  344. if (err < 0) {
  345. dev_err(ice->card->dev, "CS8427 initialization failed\n");
  346. return err;
  347. }
  348. ice->spdif.ops.open = open_cs8427;
  349. ice->spdif.ops.close = close_cs8427;
  350. ice->spdif.ops.setup_rate = setup_cs8427;
  351. return 0;
  352. }
  353. static void snd_ice1712_set_input_clock_source(struct snd_ice1712 *ice, int spdif_is_master)
  354. {
  355. /* change CS8427 clock source too */
  356. if (ice->cs8427)
  357. snd_ice1712_cs8427_set_input_clock(ice, spdif_is_master);
  358. /* notify ak4524 chip as well */
  359. if (spdif_is_master) {
  360. unsigned int i;
  361. for (i = 0; i < ice->akm_codecs; i++) {
  362. if (ice->akm[i].ops.set_rate_val)
  363. ice->akm[i].ops.set_rate_val(&ice->akm[i], 0);
  364. }
  365. }
  366. }
  367. /*
  368. * Interrupt handler
  369. */
  370. static irqreturn_t snd_ice1712_interrupt(int irq, void *dev_id)
  371. {
  372. struct snd_ice1712 *ice = dev_id;
  373. unsigned char status;
  374. int handled = 0;
  375. while (1) {
  376. status = inb(ICEREG(ice, IRQSTAT));
  377. if (status == 0)
  378. break;
  379. handled = 1;
  380. if (status & ICE1712_IRQ_MPU1) {
  381. if (ice->rmidi[0])
  382. snd_mpu401_uart_interrupt(irq, ice->rmidi[0]->private_data);
  383. outb(ICE1712_IRQ_MPU1, ICEREG(ice, IRQSTAT));
  384. status &= ~ICE1712_IRQ_MPU1;
  385. }
  386. if (status & ICE1712_IRQ_TIMER)
  387. outb(ICE1712_IRQ_TIMER, ICEREG(ice, IRQSTAT));
  388. if (status & ICE1712_IRQ_MPU2) {
  389. if (ice->rmidi[1])
  390. snd_mpu401_uart_interrupt(irq, ice->rmidi[1]->private_data);
  391. outb(ICE1712_IRQ_MPU2, ICEREG(ice, IRQSTAT));
  392. status &= ~ICE1712_IRQ_MPU2;
  393. }
  394. if (status & ICE1712_IRQ_PROPCM) {
  395. unsigned char mtstat = inb(ICEMT(ice, IRQ));
  396. if (mtstat & ICE1712_MULTI_PBKSTATUS) {
  397. if (ice->playback_pro_substream)
  398. snd_pcm_period_elapsed(ice->playback_pro_substream);
  399. outb(ICE1712_MULTI_PBKSTATUS, ICEMT(ice, IRQ));
  400. }
  401. if (mtstat & ICE1712_MULTI_CAPSTATUS) {
  402. if (ice->capture_pro_substream)
  403. snd_pcm_period_elapsed(ice->capture_pro_substream);
  404. outb(ICE1712_MULTI_CAPSTATUS, ICEMT(ice, IRQ));
  405. }
  406. }
  407. if (status & ICE1712_IRQ_FM)
  408. outb(ICE1712_IRQ_FM, ICEREG(ice, IRQSTAT));
  409. if (status & ICE1712_IRQ_PBKDS) {
  410. u32 idx;
  411. u16 pbkstatus;
  412. struct snd_pcm_substream *substream;
  413. pbkstatus = inw(ICEDS(ice, INTSTAT));
  414. /* dev_dbg(ice->card->dev, "pbkstatus = 0x%x\n", pbkstatus); */
  415. for (idx = 0; idx < 6; idx++) {
  416. if ((pbkstatus & (3 << (idx * 2))) == 0)
  417. continue;
  418. substream = ice->playback_con_substream_ds[idx];
  419. if (substream != NULL)
  420. snd_pcm_period_elapsed(substream);
  421. outw(3 << (idx * 2), ICEDS(ice, INTSTAT));
  422. }
  423. outb(ICE1712_IRQ_PBKDS, ICEREG(ice, IRQSTAT));
  424. }
  425. if (status & ICE1712_IRQ_CONCAP) {
  426. if (ice->capture_con_substream)
  427. snd_pcm_period_elapsed(ice->capture_con_substream);
  428. outb(ICE1712_IRQ_CONCAP, ICEREG(ice, IRQSTAT));
  429. }
  430. if (status & ICE1712_IRQ_CONPBK) {
  431. if (ice->playback_con_substream)
  432. snd_pcm_period_elapsed(ice->playback_con_substream);
  433. outb(ICE1712_IRQ_CONPBK, ICEREG(ice, IRQSTAT));
  434. }
  435. }
  436. return IRQ_RETVAL(handled);
  437. }
  438. /*
  439. * PCM part - misc
  440. */
  441. static int snd_ice1712_hw_params(struct snd_pcm_substream *substream,
  442. struct snd_pcm_hw_params *hw_params)
  443. {
  444. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  445. }
  446. static int snd_ice1712_hw_free(struct snd_pcm_substream *substream)
  447. {
  448. return snd_pcm_lib_free_pages(substream);
  449. }
  450. /*
  451. * PCM part - consumer I/O
  452. */
  453. static int snd_ice1712_playback_trigger(struct snd_pcm_substream *substream,
  454. int cmd)
  455. {
  456. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  457. int result = 0;
  458. u32 tmp;
  459. spin_lock(&ice->reg_lock);
  460. tmp = snd_ice1712_read(ice, ICE1712_IREG_PBK_CTRL);
  461. if (cmd == SNDRV_PCM_TRIGGER_START) {
  462. tmp |= 1;
  463. } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
  464. tmp &= ~1;
  465. } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) {
  466. tmp |= 2;
  467. } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE) {
  468. tmp &= ~2;
  469. } else {
  470. result = -EINVAL;
  471. }
  472. snd_ice1712_write(ice, ICE1712_IREG_PBK_CTRL, tmp);
  473. spin_unlock(&ice->reg_lock);
  474. return result;
  475. }
  476. static int snd_ice1712_playback_ds_trigger(struct snd_pcm_substream *substream,
  477. int cmd)
  478. {
  479. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  480. int result = 0;
  481. u32 tmp;
  482. spin_lock(&ice->reg_lock);
  483. tmp = snd_ice1712_ds_read(ice, substream->number * 2, ICE1712_DSC_CONTROL);
  484. if (cmd == SNDRV_PCM_TRIGGER_START) {
  485. tmp |= 1;
  486. } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
  487. tmp &= ~1;
  488. } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) {
  489. tmp |= 2;
  490. } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE) {
  491. tmp &= ~2;
  492. } else {
  493. result = -EINVAL;
  494. }
  495. snd_ice1712_ds_write(ice, substream->number * 2, ICE1712_DSC_CONTROL, tmp);
  496. spin_unlock(&ice->reg_lock);
  497. return result;
  498. }
  499. static int snd_ice1712_capture_trigger(struct snd_pcm_substream *substream,
  500. int cmd)
  501. {
  502. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  503. int result = 0;
  504. u8 tmp;
  505. spin_lock(&ice->reg_lock);
  506. tmp = snd_ice1712_read(ice, ICE1712_IREG_CAP_CTRL);
  507. if (cmd == SNDRV_PCM_TRIGGER_START) {
  508. tmp |= 1;
  509. } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
  510. tmp &= ~1;
  511. } else {
  512. result = -EINVAL;
  513. }
  514. snd_ice1712_write(ice, ICE1712_IREG_CAP_CTRL, tmp);
  515. spin_unlock(&ice->reg_lock);
  516. return result;
  517. }
  518. static int snd_ice1712_playback_prepare(struct snd_pcm_substream *substream)
  519. {
  520. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  521. struct snd_pcm_runtime *runtime = substream->runtime;
  522. u32 period_size, buf_size, rate, tmp;
  523. period_size = (snd_pcm_lib_period_bytes(substream) >> 2) - 1;
  524. buf_size = snd_pcm_lib_buffer_bytes(substream) - 1;
  525. tmp = 0x0000;
  526. if (snd_pcm_format_width(runtime->format) == 16)
  527. tmp |= 0x10;
  528. if (runtime->channels == 2)
  529. tmp |= 0x08;
  530. rate = (runtime->rate * 8192) / 375;
  531. if (rate > 0x000fffff)
  532. rate = 0x000fffff;
  533. spin_lock_irq(&ice->reg_lock);
  534. outb(0, ice->ddma_port + 15);
  535. outb(ICE1712_DMA_MODE_WRITE | ICE1712_DMA_AUTOINIT, ice->ddma_port + 0x0b);
  536. outl(runtime->dma_addr, ice->ddma_port + 0);
  537. outw(buf_size, ice->ddma_port + 4);
  538. snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_LO, rate & 0xff);
  539. snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_MID, (rate >> 8) & 0xff);
  540. snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_HI, (rate >> 16) & 0xff);
  541. snd_ice1712_write(ice, ICE1712_IREG_PBK_CTRL, tmp);
  542. snd_ice1712_write(ice, ICE1712_IREG_PBK_COUNT_LO, period_size & 0xff);
  543. snd_ice1712_write(ice, ICE1712_IREG_PBK_COUNT_HI, period_size >> 8);
  544. snd_ice1712_write(ice, ICE1712_IREG_PBK_LEFT, 0);
  545. snd_ice1712_write(ice, ICE1712_IREG_PBK_RIGHT, 0);
  546. spin_unlock_irq(&ice->reg_lock);
  547. return 0;
  548. }
  549. static int snd_ice1712_playback_ds_prepare(struct snd_pcm_substream *substream)
  550. {
  551. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  552. struct snd_pcm_runtime *runtime = substream->runtime;
  553. u32 period_size, rate, tmp, chn;
  554. period_size = snd_pcm_lib_period_bytes(substream) - 1;
  555. tmp = 0x0064;
  556. if (snd_pcm_format_width(runtime->format) == 16)
  557. tmp &= ~0x04;
  558. if (runtime->channels == 2)
  559. tmp |= 0x08;
  560. rate = (runtime->rate * 8192) / 375;
  561. if (rate > 0x000fffff)
  562. rate = 0x000fffff;
  563. ice->playback_con_active_buf[substream->number] = 0;
  564. ice->playback_con_virt_addr[substream->number] = runtime->dma_addr;
  565. chn = substream->number * 2;
  566. spin_lock_irq(&ice->reg_lock);
  567. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_ADDR0, runtime->dma_addr);
  568. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_COUNT0, period_size);
  569. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_ADDR1, runtime->dma_addr + (runtime->periods > 1 ? period_size + 1 : 0));
  570. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_COUNT1, period_size);
  571. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_RATE, rate);
  572. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_VOLUME, 0);
  573. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_CONTROL, tmp);
  574. if (runtime->channels == 2) {
  575. snd_ice1712_ds_write(ice, chn + 1, ICE1712_DSC_RATE, rate);
  576. snd_ice1712_ds_write(ice, chn + 1, ICE1712_DSC_VOLUME, 0);
  577. }
  578. spin_unlock_irq(&ice->reg_lock);
  579. return 0;
  580. }
  581. static int snd_ice1712_capture_prepare(struct snd_pcm_substream *substream)
  582. {
  583. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  584. struct snd_pcm_runtime *runtime = substream->runtime;
  585. u32 period_size, buf_size;
  586. u8 tmp;
  587. period_size = (snd_pcm_lib_period_bytes(substream) >> 2) - 1;
  588. buf_size = snd_pcm_lib_buffer_bytes(substream) - 1;
  589. tmp = 0x06;
  590. if (snd_pcm_format_width(runtime->format) == 16)
  591. tmp &= ~0x04;
  592. if (runtime->channels == 2)
  593. tmp &= ~0x02;
  594. spin_lock_irq(&ice->reg_lock);
  595. outl(ice->capture_con_virt_addr = runtime->dma_addr, ICEREG(ice, CONCAP_ADDR));
  596. outw(buf_size, ICEREG(ice, CONCAP_COUNT));
  597. snd_ice1712_write(ice, ICE1712_IREG_CAP_COUNT_HI, period_size >> 8);
  598. snd_ice1712_write(ice, ICE1712_IREG_CAP_COUNT_LO, period_size & 0xff);
  599. snd_ice1712_write(ice, ICE1712_IREG_CAP_CTRL, tmp);
  600. spin_unlock_irq(&ice->reg_lock);
  601. snd_ac97_set_rate(ice->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate);
  602. return 0;
  603. }
  604. static snd_pcm_uframes_t snd_ice1712_playback_pointer(struct snd_pcm_substream *substream)
  605. {
  606. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  607. struct snd_pcm_runtime *runtime = substream->runtime;
  608. size_t ptr;
  609. if (!(snd_ice1712_read(ice, ICE1712_IREG_PBK_CTRL) & 1))
  610. return 0;
  611. ptr = runtime->buffer_size - inw(ice->ddma_port + 4);
  612. ptr = bytes_to_frames(substream->runtime, ptr);
  613. if (ptr == runtime->buffer_size)
  614. ptr = 0;
  615. return ptr;
  616. }
  617. static snd_pcm_uframes_t snd_ice1712_playback_ds_pointer(struct snd_pcm_substream *substream)
  618. {
  619. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  620. u8 addr;
  621. size_t ptr;
  622. if (!(snd_ice1712_ds_read(ice, substream->number * 2, ICE1712_DSC_CONTROL) & 1))
  623. return 0;
  624. if (ice->playback_con_active_buf[substream->number])
  625. addr = ICE1712_DSC_ADDR1;
  626. else
  627. addr = ICE1712_DSC_ADDR0;
  628. ptr = snd_ice1712_ds_read(ice, substream->number * 2, addr) -
  629. ice->playback_con_virt_addr[substream->number];
  630. ptr = bytes_to_frames(substream->runtime, ptr);
  631. if (ptr == substream->runtime->buffer_size)
  632. ptr = 0;
  633. return ptr;
  634. }
  635. static snd_pcm_uframes_t snd_ice1712_capture_pointer(struct snd_pcm_substream *substream)
  636. {
  637. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  638. size_t ptr;
  639. if (!(snd_ice1712_read(ice, ICE1712_IREG_CAP_CTRL) & 1))
  640. return 0;
  641. ptr = inl(ICEREG(ice, CONCAP_ADDR)) - ice->capture_con_virt_addr;
  642. ptr = bytes_to_frames(substream->runtime, ptr);
  643. if (ptr == substream->runtime->buffer_size)
  644. ptr = 0;
  645. return ptr;
  646. }
  647. static const struct snd_pcm_hardware snd_ice1712_playback = {
  648. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  649. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  650. SNDRV_PCM_INFO_MMAP_VALID |
  651. SNDRV_PCM_INFO_PAUSE),
  652. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  653. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  654. .rate_min = 4000,
  655. .rate_max = 48000,
  656. .channels_min = 1,
  657. .channels_max = 2,
  658. .buffer_bytes_max = (64*1024),
  659. .period_bytes_min = 64,
  660. .period_bytes_max = (64*1024),
  661. .periods_min = 1,
  662. .periods_max = 1024,
  663. .fifo_size = 0,
  664. };
  665. static const struct snd_pcm_hardware snd_ice1712_playback_ds = {
  666. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  667. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  668. SNDRV_PCM_INFO_MMAP_VALID |
  669. SNDRV_PCM_INFO_PAUSE),
  670. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  671. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  672. .rate_min = 4000,
  673. .rate_max = 48000,
  674. .channels_min = 1,
  675. .channels_max = 2,
  676. .buffer_bytes_max = (128*1024),
  677. .period_bytes_min = 64,
  678. .period_bytes_max = (128*1024),
  679. .periods_min = 2,
  680. .periods_max = 2,
  681. .fifo_size = 0,
  682. };
  683. static const struct snd_pcm_hardware snd_ice1712_capture = {
  684. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  685. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  686. SNDRV_PCM_INFO_MMAP_VALID),
  687. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  688. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  689. .rate_min = 4000,
  690. .rate_max = 48000,
  691. .channels_min = 1,
  692. .channels_max = 2,
  693. .buffer_bytes_max = (64*1024),
  694. .period_bytes_min = 64,
  695. .period_bytes_max = (64*1024),
  696. .periods_min = 1,
  697. .periods_max = 1024,
  698. .fifo_size = 0,
  699. };
  700. static int snd_ice1712_playback_open(struct snd_pcm_substream *substream)
  701. {
  702. struct snd_pcm_runtime *runtime = substream->runtime;
  703. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  704. ice->playback_con_substream = substream;
  705. runtime->hw = snd_ice1712_playback;
  706. return 0;
  707. }
  708. static int snd_ice1712_playback_ds_open(struct snd_pcm_substream *substream)
  709. {
  710. struct snd_pcm_runtime *runtime = substream->runtime;
  711. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  712. u32 tmp;
  713. ice->playback_con_substream_ds[substream->number] = substream;
  714. runtime->hw = snd_ice1712_playback_ds;
  715. spin_lock_irq(&ice->reg_lock);
  716. tmp = inw(ICEDS(ice, INTMASK)) & ~(1 << (substream->number * 2));
  717. outw(tmp, ICEDS(ice, INTMASK));
  718. spin_unlock_irq(&ice->reg_lock);
  719. return 0;
  720. }
  721. static int snd_ice1712_capture_open(struct snd_pcm_substream *substream)
  722. {
  723. struct snd_pcm_runtime *runtime = substream->runtime;
  724. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  725. ice->capture_con_substream = substream;
  726. runtime->hw = snd_ice1712_capture;
  727. runtime->hw.rates = ice->ac97->rates[AC97_RATES_ADC];
  728. if (!(runtime->hw.rates & SNDRV_PCM_RATE_8000))
  729. runtime->hw.rate_min = 48000;
  730. return 0;
  731. }
  732. static int snd_ice1712_playback_close(struct snd_pcm_substream *substream)
  733. {
  734. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  735. ice->playback_con_substream = NULL;
  736. return 0;
  737. }
  738. static int snd_ice1712_playback_ds_close(struct snd_pcm_substream *substream)
  739. {
  740. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  741. u32 tmp;
  742. spin_lock_irq(&ice->reg_lock);
  743. tmp = inw(ICEDS(ice, INTMASK)) | (3 << (substream->number * 2));
  744. outw(tmp, ICEDS(ice, INTMASK));
  745. spin_unlock_irq(&ice->reg_lock);
  746. ice->playback_con_substream_ds[substream->number] = NULL;
  747. return 0;
  748. }
  749. static int snd_ice1712_capture_close(struct snd_pcm_substream *substream)
  750. {
  751. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  752. ice->capture_con_substream = NULL;
  753. return 0;
  754. }
  755. static struct snd_pcm_ops snd_ice1712_playback_ops = {
  756. .open = snd_ice1712_playback_open,
  757. .close = snd_ice1712_playback_close,
  758. .ioctl = snd_pcm_lib_ioctl,
  759. .hw_params = snd_ice1712_hw_params,
  760. .hw_free = snd_ice1712_hw_free,
  761. .prepare = snd_ice1712_playback_prepare,
  762. .trigger = snd_ice1712_playback_trigger,
  763. .pointer = snd_ice1712_playback_pointer,
  764. };
  765. static struct snd_pcm_ops snd_ice1712_playback_ds_ops = {
  766. .open = snd_ice1712_playback_ds_open,
  767. .close = snd_ice1712_playback_ds_close,
  768. .ioctl = snd_pcm_lib_ioctl,
  769. .hw_params = snd_ice1712_hw_params,
  770. .hw_free = snd_ice1712_hw_free,
  771. .prepare = snd_ice1712_playback_ds_prepare,
  772. .trigger = snd_ice1712_playback_ds_trigger,
  773. .pointer = snd_ice1712_playback_ds_pointer,
  774. };
  775. static struct snd_pcm_ops snd_ice1712_capture_ops = {
  776. .open = snd_ice1712_capture_open,
  777. .close = snd_ice1712_capture_close,
  778. .ioctl = snd_pcm_lib_ioctl,
  779. .hw_params = snd_ice1712_hw_params,
  780. .hw_free = snd_ice1712_hw_free,
  781. .prepare = snd_ice1712_capture_prepare,
  782. .trigger = snd_ice1712_capture_trigger,
  783. .pointer = snd_ice1712_capture_pointer,
  784. };
  785. static int snd_ice1712_pcm(struct snd_ice1712 *ice, int device)
  786. {
  787. struct snd_pcm *pcm;
  788. int err;
  789. err = snd_pcm_new(ice->card, "ICE1712 consumer", device, 1, 1, &pcm);
  790. if (err < 0)
  791. return err;
  792. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_ops);
  793. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ice1712_capture_ops);
  794. pcm->private_data = ice;
  795. pcm->info_flags = 0;
  796. strcpy(pcm->name, "ICE1712 consumer");
  797. ice->pcm = pcm;
  798. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  799. snd_dma_pci_data(ice->pci), 64*1024, 64*1024);
  800. dev_warn(ice->card->dev,
  801. "Consumer PCM code does not work well at the moment --jk\n");
  802. return 0;
  803. }
  804. static int snd_ice1712_pcm_ds(struct snd_ice1712 *ice, int device)
  805. {
  806. struct snd_pcm *pcm;
  807. int err;
  808. err = snd_pcm_new(ice->card, "ICE1712 consumer (DS)", device, 6, 0, &pcm);
  809. if (err < 0)
  810. return err;
  811. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_ds_ops);
  812. pcm->private_data = ice;
  813. pcm->info_flags = 0;
  814. strcpy(pcm->name, "ICE1712 consumer (DS)");
  815. ice->pcm_ds = pcm;
  816. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  817. snd_dma_pci_data(ice->pci), 64*1024, 128*1024);
  818. return 0;
  819. }
  820. /*
  821. * PCM code - professional part (multitrack)
  822. */
  823. static unsigned int rates[] = { 8000, 9600, 11025, 12000, 16000, 22050, 24000,
  824. 32000, 44100, 48000, 64000, 88200, 96000 };
  825. static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
  826. .count = ARRAY_SIZE(rates),
  827. .list = rates,
  828. .mask = 0,
  829. };
  830. static int snd_ice1712_pro_trigger(struct snd_pcm_substream *substream,
  831. int cmd)
  832. {
  833. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  834. switch (cmd) {
  835. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  836. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  837. {
  838. unsigned int what;
  839. unsigned int old;
  840. if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
  841. return -EINVAL;
  842. what = ICE1712_PLAYBACK_PAUSE;
  843. snd_pcm_trigger_done(substream, substream);
  844. spin_lock(&ice->reg_lock);
  845. old = inl(ICEMT(ice, PLAYBACK_CONTROL));
  846. if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
  847. old |= what;
  848. else
  849. old &= ~what;
  850. outl(old, ICEMT(ice, PLAYBACK_CONTROL));
  851. spin_unlock(&ice->reg_lock);
  852. break;
  853. }
  854. case SNDRV_PCM_TRIGGER_START:
  855. case SNDRV_PCM_TRIGGER_STOP:
  856. {
  857. unsigned int what = 0;
  858. unsigned int old;
  859. struct snd_pcm_substream *s;
  860. snd_pcm_group_for_each_entry(s, substream) {
  861. if (s == ice->playback_pro_substream) {
  862. what |= ICE1712_PLAYBACK_START;
  863. snd_pcm_trigger_done(s, substream);
  864. } else if (s == ice->capture_pro_substream) {
  865. what |= ICE1712_CAPTURE_START_SHADOW;
  866. snd_pcm_trigger_done(s, substream);
  867. }
  868. }
  869. spin_lock(&ice->reg_lock);
  870. old = inl(ICEMT(ice, PLAYBACK_CONTROL));
  871. if (cmd == SNDRV_PCM_TRIGGER_START)
  872. old |= what;
  873. else
  874. old &= ~what;
  875. outl(old, ICEMT(ice, PLAYBACK_CONTROL));
  876. spin_unlock(&ice->reg_lock);
  877. break;
  878. }
  879. default:
  880. return -EINVAL;
  881. }
  882. return 0;
  883. }
  884. /*
  885. */
  886. static void snd_ice1712_set_pro_rate(struct snd_ice1712 *ice, unsigned int rate, int force)
  887. {
  888. unsigned long flags;
  889. unsigned char val, old;
  890. unsigned int i;
  891. switch (rate) {
  892. case 8000: val = 6; break;
  893. case 9600: val = 3; break;
  894. case 11025: val = 10; break;
  895. case 12000: val = 2; break;
  896. case 16000: val = 5; break;
  897. case 22050: val = 9; break;
  898. case 24000: val = 1; break;
  899. case 32000: val = 4; break;
  900. case 44100: val = 8; break;
  901. case 48000: val = 0; break;
  902. case 64000: val = 15; break;
  903. case 88200: val = 11; break;
  904. case 96000: val = 7; break;
  905. default:
  906. snd_BUG();
  907. val = 0;
  908. rate = 48000;
  909. break;
  910. }
  911. spin_lock_irqsave(&ice->reg_lock, flags);
  912. if (inb(ICEMT(ice, PLAYBACK_CONTROL)) & (ICE1712_CAPTURE_START_SHADOW|
  913. ICE1712_PLAYBACK_PAUSE|
  914. ICE1712_PLAYBACK_START)) {
  915. __out:
  916. spin_unlock_irqrestore(&ice->reg_lock, flags);
  917. return;
  918. }
  919. if (!force && is_pro_rate_locked(ice))
  920. goto __out;
  921. old = inb(ICEMT(ice, RATE));
  922. if (!force && old == val)
  923. goto __out;
  924. ice->cur_rate = rate;
  925. outb(val, ICEMT(ice, RATE));
  926. spin_unlock_irqrestore(&ice->reg_lock, flags);
  927. if (ice->gpio.set_pro_rate)
  928. ice->gpio.set_pro_rate(ice, rate);
  929. for (i = 0; i < ice->akm_codecs; i++) {
  930. if (ice->akm[i].ops.set_rate_val)
  931. ice->akm[i].ops.set_rate_val(&ice->akm[i], rate);
  932. }
  933. if (ice->spdif.ops.setup_rate)
  934. ice->spdif.ops.setup_rate(ice, rate);
  935. }
  936. static int snd_ice1712_playback_pro_prepare(struct snd_pcm_substream *substream)
  937. {
  938. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  939. ice->playback_pro_size = snd_pcm_lib_buffer_bytes(substream);
  940. spin_lock_irq(&ice->reg_lock);
  941. outl(substream->runtime->dma_addr, ICEMT(ice, PLAYBACK_ADDR));
  942. outw((ice->playback_pro_size >> 2) - 1, ICEMT(ice, PLAYBACK_SIZE));
  943. outw((snd_pcm_lib_period_bytes(substream) >> 2) - 1, ICEMT(ice, PLAYBACK_COUNT));
  944. spin_unlock_irq(&ice->reg_lock);
  945. return 0;
  946. }
  947. static int snd_ice1712_playback_pro_hw_params(struct snd_pcm_substream *substream,
  948. struct snd_pcm_hw_params *hw_params)
  949. {
  950. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  951. snd_ice1712_set_pro_rate(ice, params_rate(hw_params), 0);
  952. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  953. }
  954. static int snd_ice1712_capture_pro_prepare(struct snd_pcm_substream *substream)
  955. {
  956. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  957. ice->capture_pro_size = snd_pcm_lib_buffer_bytes(substream);
  958. spin_lock_irq(&ice->reg_lock);
  959. outl(substream->runtime->dma_addr, ICEMT(ice, CAPTURE_ADDR));
  960. outw((ice->capture_pro_size >> 2) - 1, ICEMT(ice, CAPTURE_SIZE));
  961. outw((snd_pcm_lib_period_bytes(substream) >> 2) - 1, ICEMT(ice, CAPTURE_COUNT));
  962. spin_unlock_irq(&ice->reg_lock);
  963. return 0;
  964. }
  965. static int snd_ice1712_capture_pro_hw_params(struct snd_pcm_substream *substream,
  966. struct snd_pcm_hw_params *hw_params)
  967. {
  968. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  969. snd_ice1712_set_pro_rate(ice, params_rate(hw_params), 0);
  970. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  971. }
  972. static snd_pcm_uframes_t snd_ice1712_playback_pro_pointer(struct snd_pcm_substream *substream)
  973. {
  974. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  975. size_t ptr;
  976. if (!(inl(ICEMT(ice, PLAYBACK_CONTROL)) & ICE1712_PLAYBACK_START))
  977. return 0;
  978. ptr = ice->playback_pro_size - (inw(ICEMT(ice, PLAYBACK_SIZE)) << 2);
  979. ptr = bytes_to_frames(substream->runtime, ptr);
  980. if (ptr == substream->runtime->buffer_size)
  981. ptr = 0;
  982. return ptr;
  983. }
  984. static snd_pcm_uframes_t snd_ice1712_capture_pro_pointer(struct snd_pcm_substream *substream)
  985. {
  986. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  987. size_t ptr;
  988. if (!(inl(ICEMT(ice, PLAYBACK_CONTROL)) & ICE1712_CAPTURE_START_SHADOW))
  989. return 0;
  990. ptr = ice->capture_pro_size - (inw(ICEMT(ice, CAPTURE_SIZE)) << 2);
  991. ptr = bytes_to_frames(substream->runtime, ptr);
  992. if (ptr == substream->runtime->buffer_size)
  993. ptr = 0;
  994. return ptr;
  995. }
  996. static const struct snd_pcm_hardware snd_ice1712_playback_pro = {
  997. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  998. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  999. SNDRV_PCM_INFO_MMAP_VALID |
  1000. SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
  1001. .formats = SNDRV_PCM_FMTBIT_S32_LE,
  1002. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_96000,
  1003. .rate_min = 4000,
  1004. .rate_max = 96000,
  1005. .channels_min = 10,
  1006. .channels_max = 10,
  1007. .buffer_bytes_max = (256*1024),
  1008. .period_bytes_min = 10 * 4 * 2,
  1009. .period_bytes_max = 131040,
  1010. .periods_min = 1,
  1011. .periods_max = 1024,
  1012. .fifo_size = 0,
  1013. };
  1014. static const struct snd_pcm_hardware snd_ice1712_capture_pro = {
  1015. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  1016. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  1017. SNDRV_PCM_INFO_MMAP_VALID |
  1018. SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
  1019. .formats = SNDRV_PCM_FMTBIT_S32_LE,
  1020. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_96000,
  1021. .rate_min = 4000,
  1022. .rate_max = 96000,
  1023. .channels_min = 12,
  1024. .channels_max = 12,
  1025. .buffer_bytes_max = (256*1024),
  1026. .period_bytes_min = 12 * 4 * 2,
  1027. .period_bytes_max = 131040,
  1028. .periods_min = 1,
  1029. .periods_max = 1024,
  1030. .fifo_size = 0,
  1031. };
  1032. static int snd_ice1712_playback_pro_open(struct snd_pcm_substream *substream)
  1033. {
  1034. struct snd_pcm_runtime *runtime = substream->runtime;
  1035. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1036. ice->playback_pro_substream = substream;
  1037. runtime->hw = snd_ice1712_playback_pro;
  1038. snd_pcm_set_sync(substream);
  1039. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  1040. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
  1041. if (is_pro_rate_locked(ice)) {
  1042. runtime->hw.rate_min = PRO_RATE_DEFAULT;
  1043. runtime->hw.rate_max = PRO_RATE_DEFAULT;
  1044. }
  1045. if (ice->spdif.ops.open)
  1046. ice->spdif.ops.open(ice, substream);
  1047. return 0;
  1048. }
  1049. static int snd_ice1712_capture_pro_open(struct snd_pcm_substream *substream)
  1050. {
  1051. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1052. struct snd_pcm_runtime *runtime = substream->runtime;
  1053. ice->capture_pro_substream = substream;
  1054. runtime->hw = snd_ice1712_capture_pro;
  1055. snd_pcm_set_sync(substream);
  1056. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  1057. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
  1058. if (is_pro_rate_locked(ice)) {
  1059. runtime->hw.rate_min = PRO_RATE_DEFAULT;
  1060. runtime->hw.rate_max = PRO_RATE_DEFAULT;
  1061. }
  1062. return 0;
  1063. }
  1064. static int snd_ice1712_playback_pro_close(struct snd_pcm_substream *substream)
  1065. {
  1066. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1067. if (PRO_RATE_RESET)
  1068. snd_ice1712_set_pro_rate(ice, PRO_RATE_DEFAULT, 0);
  1069. ice->playback_pro_substream = NULL;
  1070. if (ice->spdif.ops.close)
  1071. ice->spdif.ops.close(ice, substream);
  1072. return 0;
  1073. }
  1074. static int snd_ice1712_capture_pro_close(struct snd_pcm_substream *substream)
  1075. {
  1076. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1077. if (PRO_RATE_RESET)
  1078. snd_ice1712_set_pro_rate(ice, PRO_RATE_DEFAULT, 0);
  1079. ice->capture_pro_substream = NULL;
  1080. return 0;
  1081. }
  1082. static struct snd_pcm_ops snd_ice1712_playback_pro_ops = {
  1083. .open = snd_ice1712_playback_pro_open,
  1084. .close = snd_ice1712_playback_pro_close,
  1085. .ioctl = snd_pcm_lib_ioctl,
  1086. .hw_params = snd_ice1712_playback_pro_hw_params,
  1087. .hw_free = snd_ice1712_hw_free,
  1088. .prepare = snd_ice1712_playback_pro_prepare,
  1089. .trigger = snd_ice1712_pro_trigger,
  1090. .pointer = snd_ice1712_playback_pro_pointer,
  1091. };
  1092. static struct snd_pcm_ops snd_ice1712_capture_pro_ops = {
  1093. .open = snd_ice1712_capture_pro_open,
  1094. .close = snd_ice1712_capture_pro_close,
  1095. .ioctl = snd_pcm_lib_ioctl,
  1096. .hw_params = snd_ice1712_capture_pro_hw_params,
  1097. .hw_free = snd_ice1712_hw_free,
  1098. .prepare = snd_ice1712_capture_pro_prepare,
  1099. .trigger = snd_ice1712_pro_trigger,
  1100. .pointer = snd_ice1712_capture_pro_pointer,
  1101. };
  1102. static int snd_ice1712_pcm_profi(struct snd_ice1712 *ice, int device)
  1103. {
  1104. struct snd_pcm *pcm;
  1105. int err;
  1106. err = snd_pcm_new(ice->card, "ICE1712 multi", device, 1, 1, &pcm);
  1107. if (err < 0)
  1108. return err;
  1109. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_pro_ops);
  1110. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ice1712_capture_pro_ops);
  1111. pcm->private_data = ice;
  1112. pcm->info_flags = 0;
  1113. strcpy(pcm->name, "ICE1712 multi");
  1114. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1115. snd_dma_pci_data(ice->pci), 256*1024, 256*1024);
  1116. ice->pcm_pro = pcm;
  1117. if (ice->cs8427) {
  1118. /* assign channels to iec958 */
  1119. err = snd_cs8427_iec958_build(ice->cs8427,
  1120. pcm->streams[0].substream,
  1121. pcm->streams[1].substream);
  1122. if (err < 0)
  1123. return err;
  1124. }
  1125. return snd_ice1712_build_pro_mixer(ice);
  1126. }
  1127. /*
  1128. * Mixer section
  1129. */
  1130. static void snd_ice1712_update_volume(struct snd_ice1712 *ice, int index)
  1131. {
  1132. unsigned int vol = ice->pro_volumes[index];
  1133. unsigned short val = 0;
  1134. val |= (vol & 0x8000) == 0 ? (96 - (vol & 0x7f)) : 0x7f;
  1135. val |= ((vol & 0x80000000) == 0 ? (96 - ((vol >> 16) & 0x7f)) : 0x7f) << 8;
  1136. outb(index, ICEMT(ice, MONITOR_INDEX));
  1137. outw(val, ICEMT(ice, MONITOR_VOLUME));
  1138. }
  1139. #define snd_ice1712_pro_mixer_switch_info snd_ctl_boolean_stereo_info
  1140. static int snd_ice1712_pro_mixer_switch_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1141. {
  1142. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1143. int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
  1144. kcontrol->private_value;
  1145. spin_lock_irq(&ice->reg_lock);
  1146. ucontrol->value.integer.value[0] =
  1147. !((ice->pro_volumes[priv_idx] >> 15) & 1);
  1148. ucontrol->value.integer.value[1] =
  1149. !((ice->pro_volumes[priv_idx] >> 31) & 1);
  1150. spin_unlock_irq(&ice->reg_lock);
  1151. return 0;
  1152. }
  1153. static int snd_ice1712_pro_mixer_switch_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1154. {
  1155. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1156. int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
  1157. kcontrol->private_value;
  1158. unsigned int nval, change;
  1159. nval = (ucontrol->value.integer.value[0] ? 0 : 0x00008000) |
  1160. (ucontrol->value.integer.value[1] ? 0 : 0x80000000);
  1161. spin_lock_irq(&ice->reg_lock);
  1162. nval |= ice->pro_volumes[priv_idx] & ~0x80008000;
  1163. change = nval != ice->pro_volumes[priv_idx];
  1164. ice->pro_volumes[priv_idx] = nval;
  1165. snd_ice1712_update_volume(ice, priv_idx);
  1166. spin_unlock_irq(&ice->reg_lock);
  1167. return change;
  1168. }
  1169. static int snd_ice1712_pro_mixer_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1170. {
  1171. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1172. uinfo->count = 2;
  1173. uinfo->value.integer.min = 0;
  1174. uinfo->value.integer.max = 96;
  1175. return 0;
  1176. }
  1177. static int snd_ice1712_pro_mixer_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1178. {
  1179. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1180. int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
  1181. kcontrol->private_value;
  1182. spin_lock_irq(&ice->reg_lock);
  1183. ucontrol->value.integer.value[0] =
  1184. (ice->pro_volumes[priv_idx] >> 0) & 127;
  1185. ucontrol->value.integer.value[1] =
  1186. (ice->pro_volumes[priv_idx] >> 16) & 127;
  1187. spin_unlock_irq(&ice->reg_lock);
  1188. return 0;
  1189. }
  1190. static int snd_ice1712_pro_mixer_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1191. {
  1192. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1193. int priv_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) +
  1194. kcontrol->private_value;
  1195. unsigned int nval, change;
  1196. nval = (ucontrol->value.integer.value[0] & 127) |
  1197. ((ucontrol->value.integer.value[1] & 127) << 16);
  1198. spin_lock_irq(&ice->reg_lock);
  1199. nval |= ice->pro_volumes[priv_idx] & ~0x007f007f;
  1200. change = nval != ice->pro_volumes[priv_idx];
  1201. ice->pro_volumes[priv_idx] = nval;
  1202. snd_ice1712_update_volume(ice, priv_idx);
  1203. spin_unlock_irq(&ice->reg_lock);
  1204. return change;
  1205. }
  1206. static const DECLARE_TLV_DB_SCALE(db_scale_playback, -14400, 150, 0);
  1207. static struct snd_kcontrol_new snd_ice1712_multi_playback_ctrls[] = {
  1208. {
  1209. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1210. .name = "Multi Playback Switch",
  1211. .info = snd_ice1712_pro_mixer_switch_info,
  1212. .get = snd_ice1712_pro_mixer_switch_get,
  1213. .put = snd_ice1712_pro_mixer_switch_put,
  1214. .private_value = 0,
  1215. .count = 10,
  1216. },
  1217. {
  1218. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1219. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1220. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  1221. .name = "Multi Playback Volume",
  1222. .info = snd_ice1712_pro_mixer_volume_info,
  1223. .get = snd_ice1712_pro_mixer_volume_get,
  1224. .put = snd_ice1712_pro_mixer_volume_put,
  1225. .private_value = 0,
  1226. .count = 10,
  1227. .tlv = { .p = db_scale_playback }
  1228. },
  1229. };
  1230. static struct snd_kcontrol_new snd_ice1712_multi_capture_analog_switch = {
  1231. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1232. .name = "H/W Multi Capture Switch",
  1233. .info = snd_ice1712_pro_mixer_switch_info,
  1234. .get = snd_ice1712_pro_mixer_switch_get,
  1235. .put = snd_ice1712_pro_mixer_switch_put,
  1236. .private_value = 10,
  1237. };
  1238. static struct snd_kcontrol_new snd_ice1712_multi_capture_spdif_switch = {
  1239. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1240. .name = SNDRV_CTL_NAME_IEC958("Multi ", CAPTURE, SWITCH),
  1241. .info = snd_ice1712_pro_mixer_switch_info,
  1242. .get = snd_ice1712_pro_mixer_switch_get,
  1243. .put = snd_ice1712_pro_mixer_switch_put,
  1244. .private_value = 18,
  1245. .count = 2,
  1246. };
  1247. static struct snd_kcontrol_new snd_ice1712_multi_capture_analog_volume = {
  1248. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1249. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1250. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  1251. .name = "H/W Multi Capture Volume",
  1252. .info = snd_ice1712_pro_mixer_volume_info,
  1253. .get = snd_ice1712_pro_mixer_volume_get,
  1254. .put = snd_ice1712_pro_mixer_volume_put,
  1255. .private_value = 10,
  1256. .tlv = { .p = db_scale_playback }
  1257. };
  1258. static struct snd_kcontrol_new snd_ice1712_multi_capture_spdif_volume = {
  1259. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1260. .name = SNDRV_CTL_NAME_IEC958("Multi ", CAPTURE, VOLUME),
  1261. .info = snd_ice1712_pro_mixer_volume_info,
  1262. .get = snd_ice1712_pro_mixer_volume_get,
  1263. .put = snd_ice1712_pro_mixer_volume_put,
  1264. .private_value = 18,
  1265. .count = 2,
  1266. };
  1267. static int snd_ice1712_build_pro_mixer(struct snd_ice1712 *ice)
  1268. {
  1269. struct snd_card *card = ice->card;
  1270. unsigned int idx;
  1271. int err;
  1272. /* multi-channel mixer */
  1273. for (idx = 0; idx < ARRAY_SIZE(snd_ice1712_multi_playback_ctrls); idx++) {
  1274. err = snd_ctl_add(card, snd_ctl_new1(&snd_ice1712_multi_playback_ctrls[idx], ice));
  1275. if (err < 0)
  1276. return err;
  1277. }
  1278. if (ice->num_total_adcs > 0) {
  1279. struct snd_kcontrol_new tmp = snd_ice1712_multi_capture_analog_switch;
  1280. tmp.count = ice->num_total_adcs;
  1281. err = snd_ctl_add(card, snd_ctl_new1(&tmp, ice));
  1282. if (err < 0)
  1283. return err;
  1284. }
  1285. err = snd_ctl_add(card, snd_ctl_new1(&snd_ice1712_multi_capture_spdif_switch, ice));
  1286. if (err < 0)
  1287. return err;
  1288. if (ice->num_total_adcs > 0) {
  1289. struct snd_kcontrol_new tmp = snd_ice1712_multi_capture_analog_volume;
  1290. tmp.count = ice->num_total_adcs;
  1291. err = snd_ctl_add(card, snd_ctl_new1(&tmp, ice));
  1292. if (err < 0)
  1293. return err;
  1294. }
  1295. err = snd_ctl_add(card, snd_ctl_new1(&snd_ice1712_multi_capture_spdif_volume, ice));
  1296. if (err < 0)
  1297. return err;
  1298. /* initialize volumes */
  1299. for (idx = 0; idx < 10; idx++) {
  1300. ice->pro_volumes[idx] = 0x80008000; /* mute */
  1301. snd_ice1712_update_volume(ice, idx);
  1302. }
  1303. for (idx = 10; idx < 10 + ice->num_total_adcs; idx++) {
  1304. ice->pro_volumes[idx] = 0x80008000; /* mute */
  1305. snd_ice1712_update_volume(ice, idx);
  1306. }
  1307. for (idx = 18; idx < 20; idx++) {
  1308. ice->pro_volumes[idx] = 0x80008000; /* mute */
  1309. snd_ice1712_update_volume(ice, idx);
  1310. }
  1311. return 0;
  1312. }
  1313. static void snd_ice1712_mixer_free_ac97(struct snd_ac97 *ac97)
  1314. {
  1315. struct snd_ice1712 *ice = ac97->private_data;
  1316. ice->ac97 = NULL;
  1317. }
  1318. static int snd_ice1712_ac97_mixer(struct snd_ice1712 *ice)
  1319. {
  1320. int err, bus_num = 0;
  1321. struct snd_ac97_template ac97;
  1322. struct snd_ac97_bus *pbus;
  1323. static struct snd_ac97_bus_ops con_ops = {
  1324. .write = snd_ice1712_ac97_write,
  1325. .read = snd_ice1712_ac97_read,
  1326. };
  1327. static struct snd_ac97_bus_ops pro_ops = {
  1328. .write = snd_ice1712_pro_ac97_write,
  1329. .read = snd_ice1712_pro_ac97_read,
  1330. };
  1331. if (ice_has_con_ac97(ice)) {
  1332. err = snd_ac97_bus(ice->card, bus_num++, &con_ops, NULL, &pbus);
  1333. if (err < 0)
  1334. return err;
  1335. memset(&ac97, 0, sizeof(ac97));
  1336. ac97.private_data = ice;
  1337. ac97.private_free = snd_ice1712_mixer_free_ac97;
  1338. err = snd_ac97_mixer(pbus, &ac97, &ice->ac97);
  1339. if (err < 0)
  1340. dev_warn(ice->card->dev,
  1341. "cannot initialize ac97 for consumer, skipped\n");
  1342. else {
  1343. return snd_ctl_add(ice->card,
  1344. snd_ctl_new1(&snd_ice1712_mixer_digmix_route_ac97,
  1345. ice));
  1346. }
  1347. }
  1348. if (!(ice->eeprom.data[ICE_EEP1_ACLINK] & ICE1712_CFG_PRO_I2S)) {
  1349. err = snd_ac97_bus(ice->card, bus_num, &pro_ops, NULL, &pbus);
  1350. if (err < 0)
  1351. return err;
  1352. memset(&ac97, 0, sizeof(ac97));
  1353. ac97.private_data = ice;
  1354. ac97.private_free = snd_ice1712_mixer_free_ac97;
  1355. err = snd_ac97_mixer(pbus, &ac97, &ice->ac97);
  1356. if (err < 0)
  1357. dev_warn(ice->card->dev,
  1358. "cannot initialize pro ac97, skipped\n");
  1359. else
  1360. return 0;
  1361. }
  1362. /* I2S mixer only */
  1363. strcat(ice->card->mixername, "ICE1712 - multitrack");
  1364. return 0;
  1365. }
  1366. /*
  1367. *
  1368. */
  1369. static inline unsigned int eeprom_double(struct snd_ice1712 *ice, int idx)
  1370. {
  1371. return (unsigned int)ice->eeprom.data[idx] | ((unsigned int)ice->eeprom.data[idx + 1] << 8);
  1372. }
  1373. static void snd_ice1712_proc_read(struct snd_info_entry *entry,
  1374. struct snd_info_buffer *buffer)
  1375. {
  1376. struct snd_ice1712 *ice = entry->private_data;
  1377. unsigned int idx;
  1378. snd_iprintf(buffer, "%s\n\n", ice->card->longname);
  1379. snd_iprintf(buffer, "EEPROM:\n");
  1380. snd_iprintf(buffer, " Subvendor : 0x%x\n", ice->eeprom.subvendor);
  1381. snd_iprintf(buffer, " Size : %i bytes\n", ice->eeprom.size);
  1382. snd_iprintf(buffer, " Version : %i\n", ice->eeprom.version);
  1383. snd_iprintf(buffer, " Codec : 0x%x\n", ice->eeprom.data[ICE_EEP1_CODEC]);
  1384. snd_iprintf(buffer, " ACLink : 0x%x\n", ice->eeprom.data[ICE_EEP1_ACLINK]);
  1385. snd_iprintf(buffer, " I2S ID : 0x%x\n", ice->eeprom.data[ICE_EEP1_I2SID]);
  1386. snd_iprintf(buffer, " S/PDIF : 0x%x\n", ice->eeprom.data[ICE_EEP1_SPDIF]);
  1387. snd_iprintf(buffer, " GPIO mask : 0x%x\n", ice->eeprom.gpiomask);
  1388. snd_iprintf(buffer, " GPIO state : 0x%x\n", ice->eeprom.gpiostate);
  1389. snd_iprintf(buffer, " GPIO direction : 0x%x\n", ice->eeprom.gpiodir);
  1390. snd_iprintf(buffer, " AC'97 main : 0x%x\n", eeprom_double(ice, ICE_EEP1_AC97_MAIN_LO));
  1391. snd_iprintf(buffer, " AC'97 pcm : 0x%x\n", eeprom_double(ice, ICE_EEP1_AC97_PCM_LO));
  1392. snd_iprintf(buffer, " AC'97 record : 0x%x\n", eeprom_double(ice, ICE_EEP1_AC97_REC_LO));
  1393. snd_iprintf(buffer, " AC'97 record src : 0x%x\n", ice->eeprom.data[ICE_EEP1_AC97_RECSRC]);
  1394. for (idx = 0; idx < 4; idx++)
  1395. snd_iprintf(buffer, " DAC ID #%i : 0x%x\n", idx, ice->eeprom.data[ICE_EEP1_DAC_ID + idx]);
  1396. for (idx = 0; idx < 4; idx++)
  1397. snd_iprintf(buffer, " ADC ID #%i : 0x%x\n", idx, ice->eeprom.data[ICE_EEP1_ADC_ID + idx]);
  1398. for (idx = 0x1c; idx < ice->eeprom.size; idx++)
  1399. snd_iprintf(buffer, " Extra #%02i : 0x%x\n", idx, ice->eeprom.data[idx]);
  1400. snd_iprintf(buffer, "\nRegisters:\n");
  1401. snd_iprintf(buffer, " PSDOUT03 : 0x%04x\n", (unsigned)inw(ICEMT(ice, ROUTE_PSDOUT03)));
  1402. snd_iprintf(buffer, " CAPTURE : 0x%08x\n", inl(ICEMT(ice, ROUTE_CAPTURE)));
  1403. snd_iprintf(buffer, " SPDOUT : 0x%04x\n", (unsigned)inw(ICEMT(ice, ROUTE_SPDOUT)));
  1404. snd_iprintf(buffer, " RATE : 0x%02x\n", (unsigned)inb(ICEMT(ice, RATE)));
  1405. snd_iprintf(buffer, " GPIO_DATA : 0x%02x\n", (unsigned)snd_ice1712_get_gpio_data(ice));
  1406. snd_iprintf(buffer, " GPIO_WRITE_MASK : 0x%02x\n", (unsigned)snd_ice1712_read(ice, ICE1712_IREG_GPIO_WRITE_MASK));
  1407. snd_iprintf(buffer, " GPIO_DIRECTION : 0x%02x\n", (unsigned)snd_ice1712_read(ice, ICE1712_IREG_GPIO_DIRECTION));
  1408. }
  1409. static void snd_ice1712_proc_init(struct snd_ice1712 *ice)
  1410. {
  1411. struct snd_info_entry *entry;
  1412. if (!snd_card_proc_new(ice->card, "ice1712", &entry))
  1413. snd_info_set_text_ops(entry, ice, snd_ice1712_proc_read);
  1414. }
  1415. /*
  1416. *
  1417. */
  1418. static int snd_ice1712_eeprom_info(struct snd_kcontrol *kcontrol,
  1419. struct snd_ctl_elem_info *uinfo)
  1420. {
  1421. uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
  1422. uinfo->count = sizeof(struct snd_ice1712_eeprom);
  1423. return 0;
  1424. }
  1425. static int snd_ice1712_eeprom_get(struct snd_kcontrol *kcontrol,
  1426. struct snd_ctl_elem_value *ucontrol)
  1427. {
  1428. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1429. memcpy(ucontrol->value.bytes.data, &ice->eeprom, sizeof(ice->eeprom));
  1430. return 0;
  1431. }
  1432. static struct snd_kcontrol_new snd_ice1712_eeprom = {
  1433. .iface = SNDRV_CTL_ELEM_IFACE_CARD,
  1434. .name = "ICE1712 EEPROM",
  1435. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1436. .info = snd_ice1712_eeprom_info,
  1437. .get = snd_ice1712_eeprom_get
  1438. };
  1439. /*
  1440. */
  1441. static int snd_ice1712_spdif_info(struct snd_kcontrol *kcontrol,
  1442. struct snd_ctl_elem_info *uinfo)
  1443. {
  1444. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1445. uinfo->count = 1;
  1446. return 0;
  1447. }
  1448. static int snd_ice1712_spdif_default_get(struct snd_kcontrol *kcontrol,
  1449. struct snd_ctl_elem_value *ucontrol)
  1450. {
  1451. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1452. if (ice->spdif.ops.default_get)
  1453. ice->spdif.ops.default_get(ice, ucontrol);
  1454. return 0;
  1455. }
  1456. static int snd_ice1712_spdif_default_put(struct snd_kcontrol *kcontrol,
  1457. struct snd_ctl_elem_value *ucontrol)
  1458. {
  1459. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1460. if (ice->spdif.ops.default_put)
  1461. return ice->spdif.ops.default_put(ice, ucontrol);
  1462. return 0;
  1463. }
  1464. static struct snd_kcontrol_new snd_ice1712_spdif_default =
  1465. {
  1466. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1467. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
  1468. .info = snd_ice1712_spdif_info,
  1469. .get = snd_ice1712_spdif_default_get,
  1470. .put = snd_ice1712_spdif_default_put
  1471. };
  1472. static int snd_ice1712_spdif_maskc_get(struct snd_kcontrol *kcontrol,
  1473. struct snd_ctl_elem_value *ucontrol)
  1474. {
  1475. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1476. if (ice->spdif.ops.default_get) {
  1477. ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
  1478. IEC958_AES0_PROFESSIONAL |
  1479. IEC958_AES0_CON_NOT_COPYRIGHT |
  1480. IEC958_AES0_CON_EMPHASIS;
  1481. ucontrol->value.iec958.status[1] = IEC958_AES1_CON_ORIGINAL |
  1482. IEC958_AES1_CON_CATEGORY;
  1483. ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS;
  1484. } else {
  1485. ucontrol->value.iec958.status[0] = 0xff;
  1486. ucontrol->value.iec958.status[1] = 0xff;
  1487. ucontrol->value.iec958.status[2] = 0xff;
  1488. ucontrol->value.iec958.status[3] = 0xff;
  1489. ucontrol->value.iec958.status[4] = 0xff;
  1490. }
  1491. return 0;
  1492. }
  1493. static int snd_ice1712_spdif_maskp_get(struct snd_kcontrol *kcontrol,
  1494. struct snd_ctl_elem_value *ucontrol)
  1495. {
  1496. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1497. if (ice->spdif.ops.default_get) {
  1498. ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
  1499. IEC958_AES0_PROFESSIONAL |
  1500. IEC958_AES0_PRO_FS |
  1501. IEC958_AES0_PRO_EMPHASIS;
  1502. ucontrol->value.iec958.status[1] = IEC958_AES1_PRO_MODE;
  1503. } else {
  1504. ucontrol->value.iec958.status[0] = 0xff;
  1505. ucontrol->value.iec958.status[1] = 0xff;
  1506. ucontrol->value.iec958.status[2] = 0xff;
  1507. ucontrol->value.iec958.status[3] = 0xff;
  1508. ucontrol->value.iec958.status[4] = 0xff;
  1509. }
  1510. return 0;
  1511. }
  1512. static struct snd_kcontrol_new snd_ice1712_spdif_maskc =
  1513. {
  1514. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1515. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1516. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
  1517. .info = snd_ice1712_spdif_info,
  1518. .get = snd_ice1712_spdif_maskc_get,
  1519. };
  1520. static struct snd_kcontrol_new snd_ice1712_spdif_maskp =
  1521. {
  1522. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1523. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1524. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK),
  1525. .info = snd_ice1712_spdif_info,
  1526. .get = snd_ice1712_spdif_maskp_get,
  1527. };
  1528. static int snd_ice1712_spdif_stream_get(struct snd_kcontrol *kcontrol,
  1529. struct snd_ctl_elem_value *ucontrol)
  1530. {
  1531. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1532. if (ice->spdif.ops.stream_get)
  1533. ice->spdif.ops.stream_get(ice, ucontrol);
  1534. return 0;
  1535. }
  1536. static int snd_ice1712_spdif_stream_put(struct snd_kcontrol *kcontrol,
  1537. struct snd_ctl_elem_value *ucontrol)
  1538. {
  1539. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1540. if (ice->spdif.ops.stream_put)
  1541. return ice->spdif.ops.stream_put(ice, ucontrol);
  1542. return 0;
  1543. }
  1544. static struct snd_kcontrol_new snd_ice1712_spdif_stream =
  1545. {
  1546. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1547. SNDRV_CTL_ELEM_ACCESS_INACTIVE),
  1548. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1549. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM),
  1550. .info = snd_ice1712_spdif_info,
  1551. .get = snd_ice1712_spdif_stream_get,
  1552. .put = snd_ice1712_spdif_stream_put
  1553. };
  1554. int snd_ice1712_gpio_get(struct snd_kcontrol *kcontrol,
  1555. struct snd_ctl_elem_value *ucontrol)
  1556. {
  1557. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1558. unsigned char mask = kcontrol->private_value & 0xff;
  1559. int invert = (kcontrol->private_value & (1<<24)) ? 1 : 0;
  1560. snd_ice1712_save_gpio_status(ice);
  1561. ucontrol->value.integer.value[0] =
  1562. (snd_ice1712_gpio_read(ice) & mask ? 1 : 0) ^ invert;
  1563. snd_ice1712_restore_gpio_status(ice);
  1564. return 0;
  1565. }
  1566. int snd_ice1712_gpio_put(struct snd_kcontrol *kcontrol,
  1567. struct snd_ctl_elem_value *ucontrol)
  1568. {
  1569. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1570. unsigned char mask = kcontrol->private_value & 0xff;
  1571. int invert = (kcontrol->private_value & (1<<24)) ? mask : 0;
  1572. unsigned int val, nval;
  1573. if (kcontrol->private_value & (1 << 31))
  1574. return -EPERM;
  1575. nval = (ucontrol->value.integer.value[0] ? mask : 0) ^ invert;
  1576. snd_ice1712_save_gpio_status(ice);
  1577. val = snd_ice1712_gpio_read(ice);
  1578. nval |= val & ~mask;
  1579. if (val != nval)
  1580. snd_ice1712_gpio_write(ice, nval);
  1581. snd_ice1712_restore_gpio_status(ice);
  1582. return val != nval;
  1583. }
  1584. /*
  1585. * rate
  1586. */
  1587. static int snd_ice1712_pro_internal_clock_info(struct snd_kcontrol *kcontrol,
  1588. struct snd_ctl_elem_info *uinfo)
  1589. {
  1590. static const char * const texts[] = {
  1591. "8000", /* 0: 6 */
  1592. "9600", /* 1: 3 */
  1593. "11025", /* 2: 10 */
  1594. "12000", /* 3: 2 */
  1595. "16000", /* 4: 5 */
  1596. "22050", /* 5: 9 */
  1597. "24000", /* 6: 1 */
  1598. "32000", /* 7: 4 */
  1599. "44100", /* 8: 8 */
  1600. "48000", /* 9: 0 */
  1601. "64000", /* 10: 15 */
  1602. "88200", /* 11: 11 */
  1603. "96000", /* 12: 7 */
  1604. "IEC958 Input", /* 13: -- */
  1605. };
  1606. return snd_ctl_enum_info(uinfo, 1, 14, texts);
  1607. }
  1608. static int snd_ice1712_pro_internal_clock_get(struct snd_kcontrol *kcontrol,
  1609. struct snd_ctl_elem_value *ucontrol)
  1610. {
  1611. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1612. static const unsigned char xlate[16] = {
  1613. 9, 6, 3, 1, 7, 4, 0, 12, 8, 5, 2, 11, 255, 255, 255, 10
  1614. };
  1615. unsigned char val;
  1616. spin_lock_irq(&ice->reg_lock);
  1617. if (is_spdif_master(ice)) {
  1618. ucontrol->value.enumerated.item[0] = 13;
  1619. } else {
  1620. val = xlate[inb(ICEMT(ice, RATE)) & 15];
  1621. if (val == 255) {
  1622. snd_BUG();
  1623. val = 0;
  1624. }
  1625. ucontrol->value.enumerated.item[0] = val;
  1626. }
  1627. spin_unlock_irq(&ice->reg_lock);
  1628. return 0;
  1629. }
  1630. static int snd_ice1712_pro_internal_clock_put(struct snd_kcontrol *kcontrol,
  1631. struct snd_ctl_elem_value *ucontrol)
  1632. {
  1633. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1634. static const unsigned int xrate[13] = {
  1635. 8000, 9600, 11025, 12000, 16000, 22050, 24000,
  1636. 32000, 44100, 48000, 64000, 88200, 96000
  1637. };
  1638. unsigned char oval;
  1639. int change = 0;
  1640. spin_lock_irq(&ice->reg_lock);
  1641. oval = inb(ICEMT(ice, RATE));
  1642. if (ucontrol->value.enumerated.item[0] == 13) {
  1643. outb(oval | ICE1712_SPDIF_MASTER, ICEMT(ice, RATE));
  1644. } else {
  1645. PRO_RATE_DEFAULT = xrate[ucontrol->value.integer.value[0] % 13];
  1646. spin_unlock_irq(&ice->reg_lock);
  1647. snd_ice1712_set_pro_rate(ice, PRO_RATE_DEFAULT, 1);
  1648. spin_lock_irq(&ice->reg_lock);
  1649. }
  1650. change = inb(ICEMT(ice, RATE)) != oval;
  1651. spin_unlock_irq(&ice->reg_lock);
  1652. if ((oval & ICE1712_SPDIF_MASTER) !=
  1653. (inb(ICEMT(ice, RATE)) & ICE1712_SPDIF_MASTER))
  1654. snd_ice1712_set_input_clock_source(ice, is_spdif_master(ice));
  1655. return change;
  1656. }
  1657. static struct snd_kcontrol_new snd_ice1712_pro_internal_clock = {
  1658. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1659. .name = "Multi Track Internal Clock",
  1660. .info = snd_ice1712_pro_internal_clock_info,
  1661. .get = snd_ice1712_pro_internal_clock_get,
  1662. .put = snd_ice1712_pro_internal_clock_put
  1663. };
  1664. static int snd_ice1712_pro_internal_clock_default_info(struct snd_kcontrol *kcontrol,
  1665. struct snd_ctl_elem_info *uinfo)
  1666. {
  1667. static const char * const texts[] = {
  1668. "8000", /* 0: 6 */
  1669. "9600", /* 1: 3 */
  1670. "11025", /* 2: 10 */
  1671. "12000", /* 3: 2 */
  1672. "16000", /* 4: 5 */
  1673. "22050", /* 5: 9 */
  1674. "24000", /* 6: 1 */
  1675. "32000", /* 7: 4 */
  1676. "44100", /* 8: 8 */
  1677. "48000", /* 9: 0 */
  1678. "64000", /* 10: 15 */
  1679. "88200", /* 11: 11 */
  1680. "96000", /* 12: 7 */
  1681. /* "IEC958 Input", 13: -- */
  1682. };
  1683. return snd_ctl_enum_info(uinfo, 1, 13, texts);
  1684. }
  1685. static int snd_ice1712_pro_internal_clock_default_get(struct snd_kcontrol *kcontrol,
  1686. struct snd_ctl_elem_value *ucontrol)
  1687. {
  1688. int val;
  1689. static const unsigned int xrate[13] = {
  1690. 8000, 9600, 11025, 12000, 16000, 22050, 24000,
  1691. 32000, 44100, 48000, 64000, 88200, 96000
  1692. };
  1693. for (val = 0; val < 13; val++) {
  1694. if (xrate[val] == PRO_RATE_DEFAULT)
  1695. break;
  1696. }
  1697. ucontrol->value.enumerated.item[0] = val;
  1698. return 0;
  1699. }
  1700. static int snd_ice1712_pro_internal_clock_default_put(struct snd_kcontrol *kcontrol,
  1701. struct snd_ctl_elem_value *ucontrol)
  1702. {
  1703. static const unsigned int xrate[13] = {
  1704. 8000, 9600, 11025, 12000, 16000, 22050, 24000,
  1705. 32000, 44100, 48000, 64000, 88200, 96000
  1706. };
  1707. unsigned char oval;
  1708. int change = 0;
  1709. oval = PRO_RATE_DEFAULT;
  1710. PRO_RATE_DEFAULT = xrate[ucontrol->value.integer.value[0] % 13];
  1711. change = PRO_RATE_DEFAULT != oval;
  1712. return change;
  1713. }
  1714. static struct snd_kcontrol_new snd_ice1712_pro_internal_clock_default = {
  1715. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1716. .name = "Multi Track Internal Clock Default",
  1717. .info = snd_ice1712_pro_internal_clock_default_info,
  1718. .get = snd_ice1712_pro_internal_clock_default_get,
  1719. .put = snd_ice1712_pro_internal_clock_default_put
  1720. };
  1721. #define snd_ice1712_pro_rate_locking_info snd_ctl_boolean_mono_info
  1722. static int snd_ice1712_pro_rate_locking_get(struct snd_kcontrol *kcontrol,
  1723. struct snd_ctl_elem_value *ucontrol)
  1724. {
  1725. ucontrol->value.integer.value[0] = PRO_RATE_LOCKED;
  1726. return 0;
  1727. }
  1728. static int snd_ice1712_pro_rate_locking_put(struct snd_kcontrol *kcontrol,
  1729. struct snd_ctl_elem_value *ucontrol)
  1730. {
  1731. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1732. int change = 0, nval;
  1733. nval = ucontrol->value.integer.value[0] ? 1 : 0;
  1734. spin_lock_irq(&ice->reg_lock);
  1735. change = PRO_RATE_LOCKED != nval;
  1736. PRO_RATE_LOCKED = nval;
  1737. spin_unlock_irq(&ice->reg_lock);
  1738. return change;
  1739. }
  1740. static struct snd_kcontrol_new snd_ice1712_pro_rate_locking = {
  1741. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1742. .name = "Multi Track Rate Locking",
  1743. .info = snd_ice1712_pro_rate_locking_info,
  1744. .get = snd_ice1712_pro_rate_locking_get,
  1745. .put = snd_ice1712_pro_rate_locking_put
  1746. };
  1747. #define snd_ice1712_pro_rate_reset_info snd_ctl_boolean_mono_info
  1748. static int snd_ice1712_pro_rate_reset_get(struct snd_kcontrol *kcontrol,
  1749. struct snd_ctl_elem_value *ucontrol)
  1750. {
  1751. ucontrol->value.integer.value[0] = PRO_RATE_RESET;
  1752. return 0;
  1753. }
  1754. static int snd_ice1712_pro_rate_reset_put(struct snd_kcontrol *kcontrol,
  1755. struct snd_ctl_elem_value *ucontrol)
  1756. {
  1757. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1758. int change = 0, nval;
  1759. nval = ucontrol->value.integer.value[0] ? 1 : 0;
  1760. spin_lock_irq(&ice->reg_lock);
  1761. change = PRO_RATE_RESET != nval;
  1762. PRO_RATE_RESET = nval;
  1763. spin_unlock_irq(&ice->reg_lock);
  1764. return change;
  1765. }
  1766. static struct snd_kcontrol_new snd_ice1712_pro_rate_reset = {
  1767. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1768. .name = "Multi Track Rate Reset",
  1769. .info = snd_ice1712_pro_rate_reset_info,
  1770. .get = snd_ice1712_pro_rate_reset_get,
  1771. .put = snd_ice1712_pro_rate_reset_put
  1772. };
  1773. /*
  1774. * routing
  1775. */
  1776. static int snd_ice1712_pro_route_info(struct snd_kcontrol *kcontrol,
  1777. struct snd_ctl_elem_info *uinfo)
  1778. {
  1779. static const char * const texts[] = {
  1780. "PCM Out", /* 0 */
  1781. "H/W In 0", "H/W In 1", "H/W In 2", "H/W In 3", /* 1-4 */
  1782. "H/W In 4", "H/W In 5", "H/W In 6", "H/W In 7", /* 5-8 */
  1783. "IEC958 In L", "IEC958 In R", /* 9-10 */
  1784. "Digital Mixer", /* 11 - optional */
  1785. };
  1786. int num_items = snd_ctl_get_ioffidx(kcontrol, &uinfo->id) < 2 ? 12 : 11;
  1787. return snd_ctl_enum_info(uinfo, 1, num_items, texts);
  1788. }
  1789. static int snd_ice1712_pro_route_analog_get(struct snd_kcontrol *kcontrol,
  1790. struct snd_ctl_elem_value *ucontrol)
  1791. {
  1792. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1793. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1794. unsigned int val, cval;
  1795. spin_lock_irq(&ice->reg_lock);
  1796. val = inw(ICEMT(ice, ROUTE_PSDOUT03));
  1797. cval = inl(ICEMT(ice, ROUTE_CAPTURE));
  1798. spin_unlock_irq(&ice->reg_lock);
  1799. val >>= ((idx % 2) * 8) + ((idx / 2) * 2);
  1800. val &= 3;
  1801. cval >>= ((idx / 2) * 8) + ((idx % 2) * 4);
  1802. if (val == 1 && idx < 2)
  1803. ucontrol->value.enumerated.item[0] = 11;
  1804. else if (val == 2)
  1805. ucontrol->value.enumerated.item[0] = (cval & 7) + 1;
  1806. else if (val == 3)
  1807. ucontrol->value.enumerated.item[0] = ((cval >> 3) & 1) + 9;
  1808. else
  1809. ucontrol->value.enumerated.item[0] = 0;
  1810. return 0;
  1811. }
  1812. static int snd_ice1712_pro_route_analog_put(struct snd_kcontrol *kcontrol,
  1813. struct snd_ctl_elem_value *ucontrol)
  1814. {
  1815. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1816. int change, shift;
  1817. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1818. unsigned int val, old_val, nval;
  1819. /* update PSDOUT */
  1820. if (ucontrol->value.enumerated.item[0] >= 11)
  1821. nval = idx < 2 ? 1 : 0; /* dig mixer (or pcm) */
  1822. else if (ucontrol->value.enumerated.item[0] >= 9)
  1823. nval = 3; /* spdif in */
  1824. else if (ucontrol->value.enumerated.item[0] >= 1)
  1825. nval = 2; /* analog in */
  1826. else
  1827. nval = 0; /* pcm */
  1828. shift = ((idx % 2) * 8) + ((idx / 2) * 2);
  1829. spin_lock_irq(&ice->reg_lock);
  1830. val = old_val = inw(ICEMT(ice, ROUTE_PSDOUT03));
  1831. val &= ~(0x03 << shift);
  1832. val |= nval << shift;
  1833. change = val != old_val;
  1834. if (change)
  1835. outw(val, ICEMT(ice, ROUTE_PSDOUT03));
  1836. spin_unlock_irq(&ice->reg_lock);
  1837. if (nval < 2) /* dig mixer of pcm */
  1838. return change;
  1839. /* update CAPTURE */
  1840. spin_lock_irq(&ice->reg_lock);
  1841. val = old_val = inl(ICEMT(ice, ROUTE_CAPTURE));
  1842. shift = ((idx / 2) * 8) + ((idx % 2) * 4);
  1843. if (nval == 2) { /* analog in */
  1844. nval = ucontrol->value.enumerated.item[0] - 1;
  1845. val &= ~(0x07 << shift);
  1846. val |= nval << shift;
  1847. } else { /* spdif in */
  1848. nval = (ucontrol->value.enumerated.item[0] - 9) << 3;
  1849. val &= ~(0x08 << shift);
  1850. val |= nval << shift;
  1851. }
  1852. if (val != old_val) {
  1853. change = 1;
  1854. outl(val, ICEMT(ice, ROUTE_CAPTURE));
  1855. }
  1856. spin_unlock_irq(&ice->reg_lock);
  1857. return change;
  1858. }
  1859. static int snd_ice1712_pro_route_spdif_get(struct snd_kcontrol *kcontrol,
  1860. struct snd_ctl_elem_value *ucontrol)
  1861. {
  1862. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1863. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1864. unsigned int val, cval;
  1865. val = inw(ICEMT(ice, ROUTE_SPDOUT));
  1866. cval = (val >> (idx * 4 + 8)) & 0x0f;
  1867. val = (val >> (idx * 2)) & 0x03;
  1868. if (val == 1)
  1869. ucontrol->value.enumerated.item[0] = 11;
  1870. else if (val == 2)
  1871. ucontrol->value.enumerated.item[0] = (cval & 7) + 1;
  1872. else if (val == 3)
  1873. ucontrol->value.enumerated.item[0] = ((cval >> 3) & 1) + 9;
  1874. else
  1875. ucontrol->value.enumerated.item[0] = 0;
  1876. return 0;
  1877. }
  1878. static int snd_ice1712_pro_route_spdif_put(struct snd_kcontrol *kcontrol,
  1879. struct snd_ctl_elem_value *ucontrol)
  1880. {
  1881. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1882. int change, shift;
  1883. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1884. unsigned int val, old_val, nval;
  1885. /* update SPDOUT */
  1886. spin_lock_irq(&ice->reg_lock);
  1887. val = old_val = inw(ICEMT(ice, ROUTE_SPDOUT));
  1888. if (ucontrol->value.enumerated.item[0] >= 11)
  1889. nval = 1;
  1890. else if (ucontrol->value.enumerated.item[0] >= 9)
  1891. nval = 3;
  1892. else if (ucontrol->value.enumerated.item[0] >= 1)
  1893. nval = 2;
  1894. else
  1895. nval = 0;
  1896. shift = idx * 2;
  1897. val &= ~(0x03 << shift);
  1898. val |= nval << shift;
  1899. shift = idx * 4 + 8;
  1900. if (nval == 2) {
  1901. nval = ucontrol->value.enumerated.item[0] - 1;
  1902. val &= ~(0x07 << shift);
  1903. val |= nval << shift;
  1904. } else if (nval == 3) {
  1905. nval = (ucontrol->value.enumerated.item[0] - 9) << 3;
  1906. val &= ~(0x08 << shift);
  1907. val |= nval << shift;
  1908. }
  1909. change = val != old_val;
  1910. if (change)
  1911. outw(val, ICEMT(ice, ROUTE_SPDOUT));
  1912. spin_unlock_irq(&ice->reg_lock);
  1913. return change;
  1914. }
  1915. static struct snd_kcontrol_new snd_ice1712_mixer_pro_analog_route = {
  1916. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1917. .name = "H/W Playback Route",
  1918. .info = snd_ice1712_pro_route_info,
  1919. .get = snd_ice1712_pro_route_analog_get,
  1920. .put = snd_ice1712_pro_route_analog_put,
  1921. };
  1922. static struct snd_kcontrol_new snd_ice1712_mixer_pro_spdif_route = {
  1923. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1924. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, NONE) "Route",
  1925. .info = snd_ice1712_pro_route_info,
  1926. .get = snd_ice1712_pro_route_spdif_get,
  1927. .put = snd_ice1712_pro_route_spdif_put,
  1928. .count = 2,
  1929. };
  1930. static int snd_ice1712_pro_volume_rate_info(struct snd_kcontrol *kcontrol,
  1931. struct snd_ctl_elem_info *uinfo)
  1932. {
  1933. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1934. uinfo->count = 1;
  1935. uinfo->value.integer.min = 0;
  1936. uinfo->value.integer.max = 255;
  1937. return 0;
  1938. }
  1939. static int snd_ice1712_pro_volume_rate_get(struct snd_kcontrol *kcontrol,
  1940. struct snd_ctl_elem_value *ucontrol)
  1941. {
  1942. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1943. ucontrol->value.integer.value[0] = inb(ICEMT(ice, MONITOR_RATE));
  1944. return 0;
  1945. }
  1946. static int snd_ice1712_pro_volume_rate_put(struct snd_kcontrol *kcontrol,
  1947. struct snd_ctl_elem_value *ucontrol)
  1948. {
  1949. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1950. int change;
  1951. spin_lock_irq(&ice->reg_lock);
  1952. change = inb(ICEMT(ice, MONITOR_RATE)) != ucontrol->value.integer.value[0];
  1953. outb(ucontrol->value.integer.value[0], ICEMT(ice, MONITOR_RATE));
  1954. spin_unlock_irq(&ice->reg_lock);
  1955. return change;
  1956. }
  1957. static struct snd_kcontrol_new snd_ice1712_mixer_pro_volume_rate = {
  1958. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1959. .name = "Multi Track Volume Rate",
  1960. .info = snd_ice1712_pro_volume_rate_info,
  1961. .get = snd_ice1712_pro_volume_rate_get,
  1962. .put = snd_ice1712_pro_volume_rate_put
  1963. };
  1964. static int snd_ice1712_pro_peak_info(struct snd_kcontrol *kcontrol,
  1965. struct snd_ctl_elem_info *uinfo)
  1966. {
  1967. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1968. uinfo->count = 22;
  1969. uinfo->value.integer.min = 0;
  1970. uinfo->value.integer.max = 255;
  1971. return 0;
  1972. }
  1973. static int snd_ice1712_pro_peak_get(struct snd_kcontrol *kcontrol,
  1974. struct snd_ctl_elem_value *ucontrol)
  1975. {
  1976. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1977. int idx;
  1978. spin_lock_irq(&ice->reg_lock);
  1979. for (idx = 0; idx < 22; idx++) {
  1980. outb(idx, ICEMT(ice, MONITOR_PEAKINDEX));
  1981. ucontrol->value.integer.value[idx] = inb(ICEMT(ice, MONITOR_PEAKDATA));
  1982. }
  1983. spin_unlock_irq(&ice->reg_lock);
  1984. return 0;
  1985. }
  1986. static struct snd_kcontrol_new snd_ice1712_mixer_pro_peak = {
  1987. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1988. .name = "Multi Track Peak",
  1989. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  1990. .info = snd_ice1712_pro_peak_info,
  1991. .get = snd_ice1712_pro_peak_get
  1992. };
  1993. /*
  1994. *
  1995. */
  1996. /*
  1997. * list of available boards
  1998. */
  1999. static struct snd_ice1712_card_info *card_tables[] = {
  2000. snd_ice1712_hoontech_cards,
  2001. snd_ice1712_delta_cards,
  2002. snd_ice1712_ews_cards,
  2003. NULL,
  2004. };
  2005. static unsigned char snd_ice1712_read_i2c(struct snd_ice1712 *ice,
  2006. unsigned char dev,
  2007. unsigned char addr)
  2008. {
  2009. long t = 0x10000;
  2010. outb(addr, ICEREG(ice, I2C_BYTE_ADDR));
  2011. outb(dev & ~ICE1712_I2C_WRITE, ICEREG(ice, I2C_DEV_ADDR));
  2012. while (t-- > 0 && (inb(ICEREG(ice, I2C_CTRL)) & ICE1712_I2C_BUSY)) ;
  2013. return inb(ICEREG(ice, I2C_DATA));
  2014. }
  2015. static int snd_ice1712_read_eeprom(struct snd_ice1712 *ice,
  2016. const char *modelname)
  2017. {
  2018. int dev = 0xa0; /* EEPROM device address */
  2019. unsigned int i, size;
  2020. struct snd_ice1712_card_info * const *tbl, *c;
  2021. if (!modelname || !*modelname) {
  2022. ice->eeprom.subvendor = 0;
  2023. if ((inb(ICEREG(ice, I2C_CTRL)) & ICE1712_I2C_EEPROM) != 0)
  2024. ice->eeprom.subvendor = (snd_ice1712_read_i2c(ice, dev, 0x00) << 0) |
  2025. (snd_ice1712_read_i2c(ice, dev, 0x01) << 8) |
  2026. (snd_ice1712_read_i2c(ice, dev, 0x02) << 16) |
  2027. (snd_ice1712_read_i2c(ice, dev, 0x03) << 24);
  2028. if (ice->eeprom.subvendor == 0 ||
  2029. ice->eeprom.subvendor == (unsigned int)-1) {
  2030. /* invalid subvendor from EEPROM, try the PCI subststem ID instead */
  2031. u16 vendor, device;
  2032. pci_read_config_word(ice->pci, PCI_SUBSYSTEM_VENDOR_ID, &vendor);
  2033. pci_read_config_word(ice->pci, PCI_SUBSYSTEM_ID, &device);
  2034. ice->eeprom.subvendor = ((unsigned int)swab16(vendor) << 16) | swab16(device);
  2035. if (ice->eeprom.subvendor == 0 || ice->eeprom.subvendor == (unsigned int)-1) {
  2036. dev_err(ice->card->dev,
  2037. "No valid ID is found\n");
  2038. return -ENXIO;
  2039. }
  2040. }
  2041. }
  2042. for (tbl = card_tables; *tbl; tbl++) {
  2043. for (c = *tbl; c->subvendor; c++) {
  2044. if (modelname && c->model && !strcmp(modelname, c->model)) {
  2045. dev_info(ice->card->dev,
  2046. "Using board model %s\n", c->name);
  2047. ice->eeprom.subvendor = c->subvendor;
  2048. } else if (c->subvendor != ice->eeprom.subvendor)
  2049. continue;
  2050. if (!c->eeprom_size || !c->eeprom_data)
  2051. goto found;
  2052. /* if the EEPROM is given by the driver, use it */
  2053. dev_dbg(ice->card->dev, "using the defined eeprom..\n");
  2054. ice->eeprom.version = 1;
  2055. ice->eeprom.size = c->eeprom_size + 6;
  2056. memcpy(ice->eeprom.data, c->eeprom_data, c->eeprom_size);
  2057. goto read_skipped;
  2058. }
  2059. }
  2060. dev_warn(ice->card->dev, "No matching model found for ID 0x%x\n",
  2061. ice->eeprom.subvendor);
  2062. found:
  2063. ice->eeprom.size = snd_ice1712_read_i2c(ice, dev, 0x04);
  2064. if (ice->eeprom.size < 6)
  2065. ice->eeprom.size = 32; /* FIXME: any cards without the correct size? */
  2066. else if (ice->eeprom.size > 32) {
  2067. dev_err(ice->card->dev,
  2068. "invalid EEPROM (size = %i)\n", ice->eeprom.size);
  2069. return -EIO;
  2070. }
  2071. ice->eeprom.version = snd_ice1712_read_i2c(ice, dev, 0x05);
  2072. if (ice->eeprom.version != 1) {
  2073. dev_err(ice->card->dev, "invalid EEPROM version %i\n",
  2074. ice->eeprom.version);
  2075. /* return -EIO; */
  2076. }
  2077. size = ice->eeprom.size - 6;
  2078. for (i = 0; i < size; i++)
  2079. ice->eeprom.data[i] = snd_ice1712_read_i2c(ice, dev, i + 6);
  2080. read_skipped:
  2081. ice->eeprom.gpiomask = ice->eeprom.data[ICE_EEP1_GPIO_MASK];
  2082. ice->eeprom.gpiostate = ice->eeprom.data[ICE_EEP1_GPIO_STATE];
  2083. ice->eeprom.gpiodir = ice->eeprom.data[ICE_EEP1_GPIO_DIR];
  2084. return 0;
  2085. }
  2086. static int snd_ice1712_chip_init(struct snd_ice1712 *ice)
  2087. {
  2088. outb(ICE1712_RESET | ICE1712_NATIVE, ICEREG(ice, CONTROL));
  2089. udelay(200);
  2090. outb(ICE1712_NATIVE, ICEREG(ice, CONTROL));
  2091. udelay(200);
  2092. if (ice->eeprom.subvendor == ICE1712_SUBDEVICE_DMX6FIRE &&
  2093. !ice->dxr_enable)
  2094. /* Set eeprom value to limit active ADCs and DACs to 6;
  2095. * Also disable AC97 as no hardware in standard 6fire card/box
  2096. * Note: DXR extensions are not currently supported
  2097. */
  2098. ice->eeprom.data[ICE_EEP1_CODEC] = 0x3a;
  2099. pci_write_config_byte(ice->pci, 0x60, ice->eeprom.data[ICE_EEP1_CODEC]);
  2100. pci_write_config_byte(ice->pci, 0x61, ice->eeprom.data[ICE_EEP1_ACLINK]);
  2101. pci_write_config_byte(ice->pci, 0x62, ice->eeprom.data[ICE_EEP1_I2SID]);
  2102. pci_write_config_byte(ice->pci, 0x63, ice->eeprom.data[ICE_EEP1_SPDIF]);
  2103. if (ice->eeprom.subvendor != ICE1712_SUBDEVICE_STDSP24) {
  2104. ice->gpio.write_mask = ice->eeprom.gpiomask;
  2105. ice->gpio.direction = ice->eeprom.gpiodir;
  2106. snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK,
  2107. ice->eeprom.gpiomask);
  2108. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION,
  2109. ice->eeprom.gpiodir);
  2110. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA,
  2111. ice->eeprom.gpiostate);
  2112. } else {
  2113. ice->gpio.write_mask = 0xc0;
  2114. ice->gpio.direction = 0xff;
  2115. snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, 0xc0);
  2116. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION, 0xff);
  2117. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA,
  2118. ICE1712_STDSP24_CLOCK_BIT);
  2119. }
  2120. snd_ice1712_write(ice, ICE1712_IREG_PRO_POWERDOWN, 0);
  2121. if (!(ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_NO_CON_AC97)) {
  2122. outb(ICE1712_AC97_WARM, ICEREG(ice, AC97_CMD));
  2123. udelay(100);
  2124. outb(0, ICEREG(ice, AC97_CMD));
  2125. udelay(200);
  2126. snd_ice1712_write(ice, ICE1712_IREG_CONSUMER_POWERDOWN, 0);
  2127. }
  2128. snd_ice1712_set_pro_rate(ice, 48000, 1);
  2129. /* unmask used interrupts */
  2130. outb(((ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_2xMPU401) == 0 ?
  2131. ICE1712_IRQ_MPU2 : 0) |
  2132. ((ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_NO_CON_AC97) ?
  2133. ICE1712_IRQ_PBKDS | ICE1712_IRQ_CONCAP | ICE1712_IRQ_CONPBK : 0),
  2134. ICEREG(ice, IRQMASK));
  2135. outb(0x00, ICEMT(ice, IRQ));
  2136. return 0;
  2137. }
  2138. int snd_ice1712_spdif_build_controls(struct snd_ice1712 *ice)
  2139. {
  2140. int err;
  2141. struct snd_kcontrol *kctl;
  2142. if (snd_BUG_ON(!ice->pcm_pro))
  2143. return -EIO;
  2144. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_default, ice));
  2145. if (err < 0)
  2146. return err;
  2147. kctl->id.device = ice->pcm_pro->device;
  2148. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_maskc, ice));
  2149. if (err < 0)
  2150. return err;
  2151. kctl->id.device = ice->pcm_pro->device;
  2152. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_maskp, ice));
  2153. if (err < 0)
  2154. return err;
  2155. kctl->id.device = ice->pcm_pro->device;
  2156. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_stream, ice));
  2157. if (err < 0)
  2158. return err;
  2159. kctl->id.device = ice->pcm_pro->device;
  2160. ice->spdif.stream_ctl = kctl;
  2161. return 0;
  2162. }
  2163. static int snd_ice1712_build_controls(struct snd_ice1712 *ice)
  2164. {
  2165. int err;
  2166. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_eeprom, ice));
  2167. if (err < 0)
  2168. return err;
  2169. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_internal_clock, ice));
  2170. if (err < 0)
  2171. return err;
  2172. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_internal_clock_default, ice));
  2173. if (err < 0)
  2174. return err;
  2175. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_rate_locking, ice));
  2176. if (err < 0)
  2177. return err;
  2178. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_rate_reset, ice));
  2179. if (err < 0)
  2180. return err;
  2181. if (ice->num_total_dacs > 0) {
  2182. struct snd_kcontrol_new tmp = snd_ice1712_mixer_pro_analog_route;
  2183. tmp.count = ice->num_total_dacs;
  2184. err = snd_ctl_add(ice->card, snd_ctl_new1(&tmp, ice));
  2185. if (err < 0)
  2186. return err;
  2187. }
  2188. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_pro_spdif_route, ice));
  2189. if (err < 0)
  2190. return err;
  2191. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_pro_volume_rate, ice));
  2192. if (err < 0)
  2193. return err;
  2194. return snd_ctl_add(ice->card,
  2195. snd_ctl_new1(&snd_ice1712_mixer_pro_peak, ice));
  2196. }
  2197. static int snd_ice1712_free(struct snd_ice1712 *ice)
  2198. {
  2199. if (!ice->port)
  2200. goto __hw_end;
  2201. /* mask all interrupts */
  2202. outb(ICE1712_MULTI_CAPTURE | ICE1712_MULTI_PLAYBACK, ICEMT(ice, IRQ));
  2203. outb(0xff, ICEREG(ice, IRQMASK));
  2204. /* --- */
  2205. __hw_end:
  2206. if (ice->irq >= 0)
  2207. free_irq(ice->irq, ice);
  2208. if (ice->port)
  2209. pci_release_regions(ice->pci);
  2210. snd_ice1712_akm4xxx_free(ice);
  2211. pci_disable_device(ice->pci);
  2212. kfree(ice->spec);
  2213. kfree(ice);
  2214. return 0;
  2215. }
  2216. static int snd_ice1712_dev_free(struct snd_device *device)
  2217. {
  2218. struct snd_ice1712 *ice = device->device_data;
  2219. return snd_ice1712_free(ice);
  2220. }
  2221. static int snd_ice1712_create(struct snd_card *card,
  2222. struct pci_dev *pci,
  2223. const char *modelname,
  2224. int omni,
  2225. int cs8427_timeout,
  2226. int dxr_enable,
  2227. struct snd_ice1712 **r_ice1712)
  2228. {
  2229. struct snd_ice1712 *ice;
  2230. int err;
  2231. static struct snd_device_ops ops = {
  2232. .dev_free = snd_ice1712_dev_free,
  2233. };
  2234. *r_ice1712 = NULL;
  2235. /* enable PCI device */
  2236. err = pci_enable_device(pci);
  2237. if (err < 0)
  2238. return err;
  2239. /* check, if we can restrict PCI DMA transfers to 28 bits */
  2240. if (dma_set_mask(&pci->dev, DMA_BIT_MASK(28)) < 0 ||
  2241. dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(28)) < 0) {
  2242. dev_err(card->dev,
  2243. "architecture does not support 28bit PCI busmaster DMA\n");
  2244. pci_disable_device(pci);
  2245. return -ENXIO;
  2246. }
  2247. ice = kzalloc(sizeof(*ice), GFP_KERNEL);
  2248. if (ice == NULL) {
  2249. pci_disable_device(pci);
  2250. return -ENOMEM;
  2251. }
  2252. ice->omni = omni ? 1 : 0;
  2253. if (cs8427_timeout < 1)
  2254. cs8427_timeout = 1;
  2255. else if (cs8427_timeout > 1000)
  2256. cs8427_timeout = 1000;
  2257. ice->cs8427_timeout = cs8427_timeout;
  2258. ice->dxr_enable = dxr_enable;
  2259. spin_lock_init(&ice->reg_lock);
  2260. mutex_init(&ice->gpio_mutex);
  2261. mutex_init(&ice->i2c_mutex);
  2262. mutex_init(&ice->open_mutex);
  2263. ice->gpio.set_mask = snd_ice1712_set_gpio_mask;
  2264. ice->gpio.get_mask = snd_ice1712_get_gpio_mask;
  2265. ice->gpio.set_dir = snd_ice1712_set_gpio_dir;
  2266. ice->gpio.get_dir = snd_ice1712_get_gpio_dir;
  2267. ice->gpio.set_data = snd_ice1712_set_gpio_data;
  2268. ice->gpio.get_data = snd_ice1712_get_gpio_data;
  2269. ice->spdif.cs8403_bits =
  2270. ice->spdif.cs8403_stream_bits = (0x01 | /* consumer format */
  2271. 0x10 | /* no emphasis */
  2272. 0x20); /* PCM encoder/decoder */
  2273. ice->card = card;
  2274. ice->pci = pci;
  2275. ice->irq = -1;
  2276. pci_set_master(pci);
  2277. /* disable legacy emulation */
  2278. pci_write_config_word(ice->pci, 0x40, 0x807f);
  2279. pci_write_config_word(ice->pci, 0x42, 0x0006);
  2280. snd_ice1712_proc_init(ice);
  2281. synchronize_irq(pci->irq);
  2282. card->private_data = ice;
  2283. err = pci_request_regions(pci, "ICE1712");
  2284. if (err < 0) {
  2285. kfree(ice);
  2286. pci_disable_device(pci);
  2287. return err;
  2288. }
  2289. ice->port = pci_resource_start(pci, 0);
  2290. ice->ddma_port = pci_resource_start(pci, 1);
  2291. ice->dmapath_port = pci_resource_start(pci, 2);
  2292. ice->profi_port = pci_resource_start(pci, 3);
  2293. if (request_irq(pci->irq, snd_ice1712_interrupt, IRQF_SHARED,
  2294. KBUILD_MODNAME, ice)) {
  2295. dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
  2296. snd_ice1712_free(ice);
  2297. return -EIO;
  2298. }
  2299. ice->irq = pci->irq;
  2300. if (snd_ice1712_read_eeprom(ice, modelname) < 0) {
  2301. snd_ice1712_free(ice);
  2302. return -EIO;
  2303. }
  2304. if (snd_ice1712_chip_init(ice) < 0) {
  2305. snd_ice1712_free(ice);
  2306. return -EIO;
  2307. }
  2308. err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ice, &ops);
  2309. if (err < 0) {
  2310. snd_ice1712_free(ice);
  2311. return err;
  2312. }
  2313. *r_ice1712 = ice;
  2314. return 0;
  2315. }
  2316. /*
  2317. *
  2318. * Registration
  2319. *
  2320. */
  2321. static struct snd_ice1712_card_info no_matched;
  2322. static int snd_ice1712_probe(struct pci_dev *pci,
  2323. const struct pci_device_id *pci_id)
  2324. {
  2325. static int dev;
  2326. struct snd_card *card;
  2327. struct snd_ice1712 *ice;
  2328. int pcm_dev = 0, err;
  2329. struct snd_ice1712_card_info * const *tbl, *c;
  2330. if (dev >= SNDRV_CARDS)
  2331. return -ENODEV;
  2332. if (!enable[dev]) {
  2333. dev++;
  2334. return -ENOENT;
  2335. }
  2336. err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
  2337. 0, &card);
  2338. if (err < 0)
  2339. return err;
  2340. strcpy(card->driver, "ICE1712");
  2341. strcpy(card->shortname, "ICEnsemble ICE1712");
  2342. err = snd_ice1712_create(card, pci, model[dev], omni[dev],
  2343. cs8427_timeout[dev], dxr_enable[dev], &ice);
  2344. if (err < 0) {
  2345. snd_card_free(card);
  2346. return err;
  2347. }
  2348. for (tbl = card_tables; *tbl; tbl++) {
  2349. for (c = *tbl; c->subvendor; c++) {
  2350. if (c->subvendor == ice->eeprom.subvendor) {
  2351. ice->card_info = c;
  2352. strcpy(card->shortname, c->name);
  2353. if (c->driver) /* specific driver? */
  2354. strcpy(card->driver, c->driver);
  2355. if (c->chip_init) {
  2356. err = c->chip_init(ice);
  2357. if (err < 0) {
  2358. snd_card_free(card);
  2359. return err;
  2360. }
  2361. }
  2362. goto __found;
  2363. }
  2364. }
  2365. }
  2366. c = &no_matched;
  2367. __found:
  2368. err = snd_ice1712_pcm_profi(ice, pcm_dev++);
  2369. if (err < 0) {
  2370. snd_card_free(card);
  2371. return err;
  2372. }
  2373. if (ice_has_con_ac97(ice)) {
  2374. err = snd_ice1712_pcm(ice, pcm_dev++);
  2375. if (err < 0) {
  2376. snd_card_free(card);
  2377. return err;
  2378. }
  2379. }
  2380. err = snd_ice1712_ac97_mixer(ice);
  2381. if (err < 0) {
  2382. snd_card_free(card);
  2383. return err;
  2384. }
  2385. err = snd_ice1712_build_controls(ice);
  2386. if (err < 0) {
  2387. snd_card_free(card);
  2388. return err;
  2389. }
  2390. if (c->build_controls) {
  2391. err = c->build_controls(ice);
  2392. if (err < 0) {
  2393. snd_card_free(card);
  2394. return err;
  2395. }
  2396. }
  2397. if (ice_has_con_ac97(ice)) {
  2398. err = snd_ice1712_pcm_ds(ice, pcm_dev++);
  2399. if (err < 0) {
  2400. snd_card_free(card);
  2401. return err;
  2402. }
  2403. }
  2404. if (!c->no_mpu401) {
  2405. err = snd_mpu401_uart_new(card, 0, MPU401_HW_ICE1712,
  2406. ICEREG(ice, MPU1_CTRL),
  2407. c->mpu401_1_info_flags |
  2408. MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK,
  2409. -1, &ice->rmidi[0]);
  2410. if (err < 0) {
  2411. snd_card_free(card);
  2412. return err;
  2413. }
  2414. if (c->mpu401_1_name)
  2415. /* Preferred name available in card_info */
  2416. snprintf(ice->rmidi[0]->name,
  2417. sizeof(ice->rmidi[0]->name),
  2418. "%s %d", c->mpu401_1_name, card->number);
  2419. if (ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_2xMPU401) {
  2420. /* 2nd port used */
  2421. err = snd_mpu401_uart_new(card, 1, MPU401_HW_ICE1712,
  2422. ICEREG(ice, MPU2_CTRL),
  2423. c->mpu401_2_info_flags |
  2424. MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK,
  2425. -1, &ice->rmidi[1]);
  2426. if (err < 0) {
  2427. snd_card_free(card);
  2428. return err;
  2429. }
  2430. if (c->mpu401_2_name)
  2431. /* Preferred name available in card_info */
  2432. snprintf(ice->rmidi[1]->name,
  2433. sizeof(ice->rmidi[1]->name),
  2434. "%s %d", c->mpu401_2_name,
  2435. card->number);
  2436. }
  2437. }
  2438. snd_ice1712_set_input_clock_source(ice, 0);
  2439. sprintf(card->longname, "%s at 0x%lx, irq %i",
  2440. card->shortname, ice->port, ice->irq);
  2441. err = snd_card_register(card);
  2442. if (err < 0) {
  2443. snd_card_free(card);
  2444. return err;
  2445. }
  2446. pci_set_drvdata(pci, card);
  2447. dev++;
  2448. return 0;
  2449. }
  2450. static void snd_ice1712_remove(struct pci_dev *pci)
  2451. {
  2452. struct snd_card *card = pci_get_drvdata(pci);
  2453. struct snd_ice1712 *ice = card->private_data;
  2454. if (ice->card_info && ice->card_info->chip_exit)
  2455. ice->card_info->chip_exit(ice);
  2456. snd_card_free(card);
  2457. }
  2458. #ifdef CONFIG_PM_SLEEP
  2459. static int snd_ice1712_suspend(struct device *dev)
  2460. {
  2461. struct snd_card *card = dev_get_drvdata(dev);
  2462. struct snd_ice1712 *ice = card->private_data;
  2463. if (!ice->pm_suspend_enabled)
  2464. return 0;
  2465. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  2466. snd_pcm_suspend_all(ice->pcm);
  2467. snd_pcm_suspend_all(ice->pcm_pro);
  2468. snd_pcm_suspend_all(ice->pcm_ds);
  2469. snd_ac97_suspend(ice->ac97);
  2470. spin_lock_irq(&ice->reg_lock);
  2471. ice->pm_saved_is_spdif_master = is_spdif_master(ice);
  2472. ice->pm_saved_spdif_ctrl = inw(ICEMT(ice, ROUTE_SPDOUT));
  2473. ice->pm_saved_route = inw(ICEMT(ice, ROUTE_PSDOUT03));
  2474. spin_unlock_irq(&ice->reg_lock);
  2475. if (ice->pm_suspend)
  2476. ice->pm_suspend(ice);
  2477. return 0;
  2478. }
  2479. static int snd_ice1712_resume(struct device *dev)
  2480. {
  2481. struct snd_card *card = dev_get_drvdata(dev);
  2482. struct snd_ice1712 *ice = card->private_data;
  2483. int rate;
  2484. if (!ice->pm_suspend_enabled)
  2485. return 0;
  2486. if (ice->cur_rate)
  2487. rate = ice->cur_rate;
  2488. else
  2489. rate = PRO_RATE_DEFAULT;
  2490. if (snd_ice1712_chip_init(ice) < 0) {
  2491. snd_card_disconnect(card);
  2492. return -EIO;
  2493. }
  2494. ice->cur_rate = rate;
  2495. if (ice->pm_resume)
  2496. ice->pm_resume(ice);
  2497. if (ice->pm_saved_is_spdif_master) {
  2498. /* switching to external clock via SPDIF */
  2499. spin_lock_irq(&ice->reg_lock);
  2500. outb(inb(ICEMT(ice, RATE)) | ICE1712_SPDIF_MASTER,
  2501. ICEMT(ice, RATE));
  2502. spin_unlock_irq(&ice->reg_lock);
  2503. snd_ice1712_set_input_clock_source(ice, 1);
  2504. } else {
  2505. /* internal on-card clock */
  2506. snd_ice1712_set_pro_rate(ice, rate, 1);
  2507. snd_ice1712_set_input_clock_source(ice, 0);
  2508. }
  2509. outw(ice->pm_saved_spdif_ctrl, ICEMT(ice, ROUTE_SPDOUT));
  2510. outw(ice->pm_saved_route, ICEMT(ice, ROUTE_PSDOUT03));
  2511. snd_ac97_resume(ice->ac97);
  2512. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  2513. return 0;
  2514. }
  2515. static SIMPLE_DEV_PM_OPS(snd_ice1712_pm, snd_ice1712_suspend, snd_ice1712_resume);
  2516. #define SND_VT1712_PM_OPS &snd_ice1712_pm
  2517. #else
  2518. #define SND_VT1712_PM_OPS NULL
  2519. #endif /* CONFIG_PM_SLEEP */
  2520. static struct pci_driver ice1712_driver = {
  2521. .name = KBUILD_MODNAME,
  2522. .id_table = snd_ice1712_ids,
  2523. .probe = snd_ice1712_probe,
  2524. .remove = snd_ice1712_remove,
  2525. .driver = {
  2526. .pm = SND_VT1712_PM_OPS,
  2527. },
  2528. };
  2529. module_pci_driver(ice1712_driver);