ice1724.c 78 KB

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  1. /*
  2. * ALSA driver for VT1724 ICEnsemble ICE1724 / VIA VT1724 (Envy24HT)
  3. * VIA VT1720 (Envy24PT)
  4. *
  5. * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
  6. * 2002 James Stafford <jstafford@ampltd.com>
  7. * 2003 Takashi Iwai <tiwai@suse.de>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22. *
  23. */
  24. #include <linux/delay.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/init.h>
  27. #include <linux/pci.h>
  28. #include <linux/slab.h>
  29. #include <linux/module.h>
  30. #include <linux/mutex.h>
  31. #include <sound/core.h>
  32. #include <sound/info.h>
  33. #include <sound/rawmidi.h>
  34. #include <sound/initval.h>
  35. #include <sound/asoundef.h>
  36. #include "ice1712.h"
  37. #include "envy24ht.h"
  38. /* lowlevel routines */
  39. #include "amp.h"
  40. #include "revo.h"
  41. #include "aureon.h"
  42. #include "vt1720_mobo.h"
  43. #include "pontis.h"
  44. #include "prodigy192.h"
  45. #include "prodigy_hifi.h"
  46. #include "juli.h"
  47. #include "maya44.h"
  48. #include "phase.h"
  49. #include "wtm.h"
  50. #include "se.h"
  51. #include "quartet.h"
  52. #include "psc724.h"
  53. MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
  54. MODULE_DESCRIPTION("VIA ICEnsemble ICE1724/1720 (Envy24HT/PT)");
  55. MODULE_LICENSE("GPL");
  56. MODULE_SUPPORTED_DEVICE("{"
  57. REVO_DEVICE_DESC
  58. AMP_AUDIO2000_DEVICE_DESC
  59. AUREON_DEVICE_DESC
  60. VT1720_MOBO_DEVICE_DESC
  61. PONTIS_DEVICE_DESC
  62. PRODIGY192_DEVICE_DESC
  63. PRODIGY_HIFI_DEVICE_DESC
  64. JULI_DEVICE_DESC
  65. MAYA44_DEVICE_DESC
  66. PHASE_DEVICE_DESC
  67. WTM_DEVICE_DESC
  68. SE_DEVICE_DESC
  69. QTET_DEVICE_DESC
  70. "{VIA,VT1720},"
  71. "{VIA,VT1724},"
  72. "{ICEnsemble,Generic ICE1724},"
  73. "{ICEnsemble,Generic Envy24HT}"
  74. "{ICEnsemble,Generic Envy24PT}}");
  75. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  76. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  77. static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
  78. static char *model[SNDRV_CARDS];
  79. module_param_array(index, int, NULL, 0444);
  80. MODULE_PARM_DESC(index, "Index value for ICE1724 soundcard.");
  81. module_param_array(id, charp, NULL, 0444);
  82. MODULE_PARM_DESC(id, "ID string for ICE1724 soundcard.");
  83. module_param_array(enable, bool, NULL, 0444);
  84. MODULE_PARM_DESC(enable, "Enable ICE1724 soundcard.");
  85. module_param_array(model, charp, NULL, 0444);
  86. MODULE_PARM_DESC(model, "Use the given board model.");
  87. /* Both VT1720 and VT1724 have the same PCI IDs */
  88. static const struct pci_device_id snd_vt1724_ids[] = {
  89. { PCI_VDEVICE(ICE, PCI_DEVICE_ID_VT1724), 0 },
  90. { 0, }
  91. };
  92. MODULE_DEVICE_TABLE(pci, snd_vt1724_ids);
  93. static int PRO_RATE_LOCKED;
  94. static int PRO_RATE_RESET = 1;
  95. static unsigned int PRO_RATE_DEFAULT = 44100;
  96. static const char * const ext_clock_names[1] = { "IEC958 In" };
  97. /*
  98. * Basic I/O
  99. */
  100. /*
  101. * default rates, default clock routines
  102. */
  103. /* check whether the clock mode is spdif-in */
  104. static inline int stdclock_is_spdif_master(struct snd_ice1712 *ice)
  105. {
  106. return (inb(ICEMT1724(ice, RATE)) & VT1724_SPDIF_MASTER) ? 1 : 0;
  107. }
  108. /*
  109. * locking rate makes sense only for internal clock mode
  110. */
  111. static inline int is_pro_rate_locked(struct snd_ice1712 *ice)
  112. {
  113. return (!ice->is_spdif_master(ice)) && PRO_RATE_LOCKED;
  114. }
  115. /*
  116. * ac97 section
  117. */
  118. static unsigned char snd_vt1724_ac97_ready(struct snd_ice1712 *ice)
  119. {
  120. unsigned char old_cmd;
  121. int tm;
  122. for (tm = 0; tm < 0x10000; tm++) {
  123. old_cmd = inb(ICEMT1724(ice, AC97_CMD));
  124. if (old_cmd & (VT1724_AC97_WRITE | VT1724_AC97_READ))
  125. continue;
  126. if (!(old_cmd & VT1724_AC97_READY))
  127. continue;
  128. return old_cmd;
  129. }
  130. dev_dbg(ice->card->dev, "snd_vt1724_ac97_ready: timeout\n");
  131. return old_cmd;
  132. }
  133. static int snd_vt1724_ac97_wait_bit(struct snd_ice1712 *ice, unsigned char bit)
  134. {
  135. int tm;
  136. for (tm = 0; tm < 0x10000; tm++)
  137. if ((inb(ICEMT1724(ice, AC97_CMD)) & bit) == 0)
  138. return 0;
  139. dev_dbg(ice->card->dev, "snd_vt1724_ac97_wait_bit: timeout\n");
  140. return -EIO;
  141. }
  142. static void snd_vt1724_ac97_write(struct snd_ac97 *ac97,
  143. unsigned short reg,
  144. unsigned short val)
  145. {
  146. struct snd_ice1712 *ice = ac97->private_data;
  147. unsigned char old_cmd;
  148. old_cmd = snd_vt1724_ac97_ready(ice);
  149. old_cmd &= ~VT1724_AC97_ID_MASK;
  150. old_cmd |= ac97->num;
  151. outb(reg, ICEMT1724(ice, AC97_INDEX));
  152. outw(val, ICEMT1724(ice, AC97_DATA));
  153. outb(old_cmd | VT1724_AC97_WRITE, ICEMT1724(ice, AC97_CMD));
  154. snd_vt1724_ac97_wait_bit(ice, VT1724_AC97_WRITE);
  155. }
  156. static unsigned short snd_vt1724_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
  157. {
  158. struct snd_ice1712 *ice = ac97->private_data;
  159. unsigned char old_cmd;
  160. old_cmd = snd_vt1724_ac97_ready(ice);
  161. old_cmd &= ~VT1724_AC97_ID_MASK;
  162. old_cmd |= ac97->num;
  163. outb(reg, ICEMT1724(ice, AC97_INDEX));
  164. outb(old_cmd | VT1724_AC97_READ, ICEMT1724(ice, AC97_CMD));
  165. if (snd_vt1724_ac97_wait_bit(ice, VT1724_AC97_READ) < 0)
  166. return ~0;
  167. return inw(ICEMT1724(ice, AC97_DATA));
  168. }
  169. /*
  170. * GPIO operations
  171. */
  172. /* set gpio direction 0 = read, 1 = write */
  173. static void snd_vt1724_set_gpio_dir(struct snd_ice1712 *ice, unsigned int data)
  174. {
  175. outl(data, ICEREG1724(ice, GPIO_DIRECTION));
  176. inw(ICEREG1724(ice, GPIO_DIRECTION)); /* dummy read for pci-posting */
  177. }
  178. /* get gpio direction 0 = read, 1 = write */
  179. static unsigned int snd_vt1724_get_gpio_dir(struct snd_ice1712 *ice)
  180. {
  181. return inl(ICEREG1724(ice, GPIO_DIRECTION));
  182. }
  183. /* set the gpio mask (0 = writable) */
  184. static void snd_vt1724_set_gpio_mask(struct snd_ice1712 *ice, unsigned int data)
  185. {
  186. outw(data, ICEREG1724(ice, GPIO_WRITE_MASK));
  187. if (!ice->vt1720) /* VT1720 supports only 16 GPIO bits */
  188. outb((data >> 16) & 0xff, ICEREG1724(ice, GPIO_WRITE_MASK_22));
  189. inw(ICEREG1724(ice, GPIO_WRITE_MASK)); /* dummy read for pci-posting */
  190. }
  191. static unsigned int snd_vt1724_get_gpio_mask(struct snd_ice1712 *ice)
  192. {
  193. unsigned int mask;
  194. if (!ice->vt1720)
  195. mask = (unsigned int)inb(ICEREG1724(ice, GPIO_WRITE_MASK_22));
  196. else
  197. mask = 0;
  198. mask = (mask << 16) | inw(ICEREG1724(ice, GPIO_WRITE_MASK));
  199. return mask;
  200. }
  201. static void snd_vt1724_set_gpio_data(struct snd_ice1712 *ice, unsigned int data)
  202. {
  203. outw(data, ICEREG1724(ice, GPIO_DATA));
  204. if (!ice->vt1720)
  205. outb(data >> 16, ICEREG1724(ice, GPIO_DATA_22));
  206. inw(ICEREG1724(ice, GPIO_DATA)); /* dummy read for pci-posting */
  207. }
  208. static unsigned int snd_vt1724_get_gpio_data(struct snd_ice1712 *ice)
  209. {
  210. unsigned int data;
  211. if (!ice->vt1720)
  212. data = (unsigned int)inb(ICEREG1724(ice, GPIO_DATA_22));
  213. else
  214. data = 0;
  215. data = (data << 16) | inw(ICEREG1724(ice, GPIO_DATA));
  216. return data;
  217. }
  218. /*
  219. * MIDI
  220. */
  221. static void vt1724_midi_clear_rx(struct snd_ice1712 *ice)
  222. {
  223. unsigned int count;
  224. for (count = inb(ICEREG1724(ice, MPU_RXFIFO)); count > 0; --count)
  225. inb(ICEREG1724(ice, MPU_DATA));
  226. }
  227. static inline struct snd_rawmidi_substream *
  228. get_rawmidi_substream(struct snd_ice1712 *ice, unsigned int stream)
  229. {
  230. return list_first_entry(&ice->rmidi[0]->streams[stream].substreams,
  231. struct snd_rawmidi_substream, list);
  232. }
  233. static void enable_midi_irq(struct snd_ice1712 *ice, u8 flag, int enable);
  234. static void vt1724_midi_write(struct snd_ice1712 *ice)
  235. {
  236. struct snd_rawmidi_substream *s;
  237. int count, i;
  238. u8 buffer[32];
  239. s = get_rawmidi_substream(ice, SNDRV_RAWMIDI_STREAM_OUTPUT);
  240. count = 31 - inb(ICEREG1724(ice, MPU_TXFIFO));
  241. if (count > 0) {
  242. count = snd_rawmidi_transmit(s, buffer, count);
  243. for (i = 0; i < count; ++i)
  244. outb(buffer[i], ICEREG1724(ice, MPU_DATA));
  245. }
  246. /* mask irq when all bytes have been transmitted.
  247. * enabled again in output_trigger when the new data comes in.
  248. */
  249. enable_midi_irq(ice, VT1724_IRQ_MPU_TX,
  250. !snd_rawmidi_transmit_empty(s));
  251. }
  252. static void vt1724_midi_read(struct snd_ice1712 *ice)
  253. {
  254. struct snd_rawmidi_substream *s;
  255. int count, i;
  256. u8 buffer[32];
  257. s = get_rawmidi_substream(ice, SNDRV_RAWMIDI_STREAM_INPUT);
  258. count = inb(ICEREG1724(ice, MPU_RXFIFO));
  259. if (count > 0) {
  260. count = min(count, 32);
  261. for (i = 0; i < count; ++i)
  262. buffer[i] = inb(ICEREG1724(ice, MPU_DATA));
  263. snd_rawmidi_receive(s, buffer, count);
  264. }
  265. }
  266. /* call with ice->reg_lock */
  267. static void enable_midi_irq(struct snd_ice1712 *ice, u8 flag, int enable)
  268. {
  269. u8 mask = inb(ICEREG1724(ice, IRQMASK));
  270. if (enable)
  271. mask &= ~flag;
  272. else
  273. mask |= flag;
  274. outb(mask, ICEREG1724(ice, IRQMASK));
  275. }
  276. static void vt1724_enable_midi_irq(struct snd_rawmidi_substream *substream,
  277. u8 flag, int enable)
  278. {
  279. struct snd_ice1712 *ice = substream->rmidi->private_data;
  280. spin_lock_irq(&ice->reg_lock);
  281. enable_midi_irq(ice, flag, enable);
  282. spin_unlock_irq(&ice->reg_lock);
  283. }
  284. static int vt1724_midi_output_open(struct snd_rawmidi_substream *s)
  285. {
  286. return 0;
  287. }
  288. static int vt1724_midi_output_close(struct snd_rawmidi_substream *s)
  289. {
  290. return 0;
  291. }
  292. static void vt1724_midi_output_trigger(struct snd_rawmidi_substream *s, int up)
  293. {
  294. struct snd_ice1712 *ice = s->rmidi->private_data;
  295. unsigned long flags;
  296. spin_lock_irqsave(&ice->reg_lock, flags);
  297. if (up) {
  298. ice->midi_output = 1;
  299. vt1724_midi_write(ice);
  300. } else {
  301. ice->midi_output = 0;
  302. enable_midi_irq(ice, VT1724_IRQ_MPU_TX, 0);
  303. }
  304. spin_unlock_irqrestore(&ice->reg_lock, flags);
  305. }
  306. static void vt1724_midi_output_drain(struct snd_rawmidi_substream *s)
  307. {
  308. struct snd_ice1712 *ice = s->rmidi->private_data;
  309. unsigned long timeout;
  310. vt1724_enable_midi_irq(s, VT1724_IRQ_MPU_TX, 0);
  311. /* 32 bytes should be transmitted in less than about 12 ms */
  312. timeout = jiffies + msecs_to_jiffies(15);
  313. do {
  314. if (inb(ICEREG1724(ice, MPU_CTRL)) & VT1724_MPU_TX_EMPTY)
  315. break;
  316. schedule_timeout_uninterruptible(1);
  317. } while (time_after(timeout, jiffies));
  318. }
  319. static struct snd_rawmidi_ops vt1724_midi_output_ops = {
  320. .open = vt1724_midi_output_open,
  321. .close = vt1724_midi_output_close,
  322. .trigger = vt1724_midi_output_trigger,
  323. .drain = vt1724_midi_output_drain,
  324. };
  325. static int vt1724_midi_input_open(struct snd_rawmidi_substream *s)
  326. {
  327. vt1724_midi_clear_rx(s->rmidi->private_data);
  328. vt1724_enable_midi_irq(s, VT1724_IRQ_MPU_RX, 1);
  329. return 0;
  330. }
  331. static int vt1724_midi_input_close(struct snd_rawmidi_substream *s)
  332. {
  333. vt1724_enable_midi_irq(s, VT1724_IRQ_MPU_RX, 0);
  334. return 0;
  335. }
  336. static void vt1724_midi_input_trigger(struct snd_rawmidi_substream *s, int up)
  337. {
  338. struct snd_ice1712 *ice = s->rmidi->private_data;
  339. unsigned long flags;
  340. spin_lock_irqsave(&ice->reg_lock, flags);
  341. if (up) {
  342. ice->midi_input = 1;
  343. vt1724_midi_read(ice);
  344. } else {
  345. ice->midi_input = 0;
  346. }
  347. spin_unlock_irqrestore(&ice->reg_lock, flags);
  348. }
  349. static struct snd_rawmidi_ops vt1724_midi_input_ops = {
  350. .open = vt1724_midi_input_open,
  351. .close = vt1724_midi_input_close,
  352. .trigger = vt1724_midi_input_trigger,
  353. };
  354. /*
  355. * Interrupt handler
  356. */
  357. static irqreturn_t snd_vt1724_interrupt(int irq, void *dev_id)
  358. {
  359. struct snd_ice1712 *ice = dev_id;
  360. unsigned char status;
  361. unsigned char status_mask =
  362. VT1724_IRQ_MPU_RX | VT1724_IRQ_MPU_TX | VT1724_IRQ_MTPCM;
  363. int handled = 0;
  364. int timeout = 0;
  365. while (1) {
  366. status = inb(ICEREG1724(ice, IRQSTAT));
  367. status &= status_mask;
  368. if (status == 0)
  369. break;
  370. spin_lock(&ice->reg_lock);
  371. if (++timeout > 10) {
  372. status = inb(ICEREG1724(ice, IRQSTAT));
  373. dev_err(ice->card->dev,
  374. "Too long irq loop, status = 0x%x\n", status);
  375. if (status & VT1724_IRQ_MPU_TX) {
  376. dev_err(ice->card->dev, "Disabling MPU_TX\n");
  377. enable_midi_irq(ice, VT1724_IRQ_MPU_TX, 0);
  378. }
  379. spin_unlock(&ice->reg_lock);
  380. break;
  381. }
  382. handled = 1;
  383. if (status & VT1724_IRQ_MPU_TX) {
  384. if (ice->midi_output)
  385. vt1724_midi_write(ice);
  386. else
  387. enable_midi_irq(ice, VT1724_IRQ_MPU_TX, 0);
  388. /* Due to mysterical reasons, MPU_TX is always
  389. * generated (and can't be cleared) when a PCM
  390. * playback is going. So let's ignore at the
  391. * next loop.
  392. */
  393. status_mask &= ~VT1724_IRQ_MPU_TX;
  394. }
  395. if (status & VT1724_IRQ_MPU_RX) {
  396. if (ice->midi_input)
  397. vt1724_midi_read(ice);
  398. else
  399. vt1724_midi_clear_rx(ice);
  400. }
  401. /* ack MPU irq */
  402. outb(status, ICEREG1724(ice, IRQSTAT));
  403. spin_unlock(&ice->reg_lock);
  404. if (status & VT1724_IRQ_MTPCM) {
  405. /*
  406. * Multi-track PCM
  407. * PCM assignment are:
  408. * Playback DMA0 (M/C) = playback_pro_substream
  409. * Playback DMA1 = playback_con_substream_ds[0]
  410. * Playback DMA2 = playback_con_substream_ds[1]
  411. * Playback DMA3 = playback_con_substream_ds[2]
  412. * Playback DMA4 (SPDIF) = playback_con_substream
  413. * Record DMA0 = capture_pro_substream
  414. * Record DMA1 = capture_con_substream
  415. */
  416. unsigned char mtstat = inb(ICEMT1724(ice, IRQ));
  417. if (mtstat & VT1724_MULTI_PDMA0) {
  418. if (ice->playback_pro_substream)
  419. snd_pcm_period_elapsed(ice->playback_pro_substream);
  420. }
  421. if (mtstat & VT1724_MULTI_RDMA0) {
  422. if (ice->capture_pro_substream)
  423. snd_pcm_period_elapsed(ice->capture_pro_substream);
  424. }
  425. if (mtstat & VT1724_MULTI_PDMA1) {
  426. if (ice->playback_con_substream_ds[0])
  427. snd_pcm_period_elapsed(ice->playback_con_substream_ds[0]);
  428. }
  429. if (mtstat & VT1724_MULTI_PDMA2) {
  430. if (ice->playback_con_substream_ds[1])
  431. snd_pcm_period_elapsed(ice->playback_con_substream_ds[1]);
  432. }
  433. if (mtstat & VT1724_MULTI_PDMA3) {
  434. if (ice->playback_con_substream_ds[2])
  435. snd_pcm_period_elapsed(ice->playback_con_substream_ds[2]);
  436. }
  437. if (mtstat & VT1724_MULTI_PDMA4) {
  438. if (ice->playback_con_substream)
  439. snd_pcm_period_elapsed(ice->playback_con_substream);
  440. }
  441. if (mtstat & VT1724_MULTI_RDMA1) {
  442. if (ice->capture_con_substream)
  443. snd_pcm_period_elapsed(ice->capture_con_substream);
  444. }
  445. /* ack anyway to avoid freeze */
  446. outb(mtstat, ICEMT1724(ice, IRQ));
  447. /* ought to really handle this properly */
  448. if (mtstat & VT1724_MULTI_FIFO_ERR) {
  449. unsigned char fstat = inb(ICEMT1724(ice, DMA_FIFO_ERR));
  450. outb(fstat, ICEMT1724(ice, DMA_FIFO_ERR));
  451. outb(VT1724_MULTI_FIFO_ERR | inb(ICEMT1724(ice, DMA_INT_MASK)), ICEMT1724(ice, DMA_INT_MASK));
  452. /* If I don't do this, I get machine lockup due to continual interrupts */
  453. }
  454. }
  455. }
  456. return IRQ_RETVAL(handled);
  457. }
  458. /*
  459. * PCM code - professional part (multitrack)
  460. */
  461. static unsigned int rates[] = {
  462. 8000, 9600, 11025, 12000, 16000, 22050, 24000,
  463. 32000, 44100, 48000, 64000, 88200, 96000,
  464. 176400, 192000,
  465. };
  466. static struct snd_pcm_hw_constraint_list hw_constraints_rates_96 = {
  467. .count = ARRAY_SIZE(rates) - 2, /* up to 96000 */
  468. .list = rates,
  469. .mask = 0,
  470. };
  471. static struct snd_pcm_hw_constraint_list hw_constraints_rates_48 = {
  472. .count = ARRAY_SIZE(rates) - 5, /* up to 48000 */
  473. .list = rates,
  474. .mask = 0,
  475. };
  476. static struct snd_pcm_hw_constraint_list hw_constraints_rates_192 = {
  477. .count = ARRAY_SIZE(rates),
  478. .list = rates,
  479. .mask = 0,
  480. };
  481. struct vt1724_pcm_reg {
  482. unsigned int addr; /* ADDR register offset */
  483. unsigned int size; /* SIZE register offset */
  484. unsigned int count; /* COUNT register offset */
  485. unsigned int start; /* start & pause bit */
  486. };
  487. static int snd_vt1724_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
  488. {
  489. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  490. unsigned char what;
  491. unsigned char old;
  492. struct snd_pcm_substream *s;
  493. what = 0;
  494. snd_pcm_group_for_each_entry(s, substream) {
  495. if (snd_pcm_substream_chip(s) == ice) {
  496. const struct vt1724_pcm_reg *reg;
  497. reg = s->runtime->private_data;
  498. what |= reg->start;
  499. snd_pcm_trigger_done(s, substream);
  500. }
  501. }
  502. switch (cmd) {
  503. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  504. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  505. spin_lock(&ice->reg_lock);
  506. old = inb(ICEMT1724(ice, DMA_PAUSE));
  507. if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
  508. old |= what;
  509. else
  510. old &= ~what;
  511. outb(old, ICEMT1724(ice, DMA_PAUSE));
  512. spin_unlock(&ice->reg_lock);
  513. break;
  514. case SNDRV_PCM_TRIGGER_START:
  515. case SNDRV_PCM_TRIGGER_STOP:
  516. case SNDRV_PCM_TRIGGER_SUSPEND:
  517. spin_lock(&ice->reg_lock);
  518. old = inb(ICEMT1724(ice, DMA_CONTROL));
  519. if (cmd == SNDRV_PCM_TRIGGER_START)
  520. old |= what;
  521. else
  522. old &= ~what;
  523. outb(old, ICEMT1724(ice, DMA_CONTROL));
  524. spin_unlock(&ice->reg_lock);
  525. break;
  526. case SNDRV_PCM_TRIGGER_RESUME:
  527. /* apps will have to restart stream */
  528. break;
  529. default:
  530. return -EINVAL;
  531. }
  532. return 0;
  533. }
  534. /*
  535. */
  536. #define DMA_STARTS (VT1724_RDMA0_START|VT1724_PDMA0_START|VT1724_RDMA1_START|\
  537. VT1724_PDMA1_START|VT1724_PDMA2_START|VT1724_PDMA3_START|VT1724_PDMA4_START)
  538. #define DMA_PAUSES (VT1724_RDMA0_PAUSE|VT1724_PDMA0_PAUSE|VT1724_RDMA1_PAUSE|\
  539. VT1724_PDMA1_PAUSE|VT1724_PDMA2_PAUSE|VT1724_PDMA3_PAUSE|VT1724_PDMA4_PAUSE)
  540. static const unsigned int stdclock_rate_list[16] = {
  541. 48000, 24000, 12000, 9600, 32000, 16000, 8000, 96000, 44100,
  542. 22050, 11025, 88200, 176400, 0, 192000, 64000
  543. };
  544. static unsigned int stdclock_get_rate(struct snd_ice1712 *ice)
  545. {
  546. unsigned int rate;
  547. rate = stdclock_rate_list[inb(ICEMT1724(ice, RATE)) & 15];
  548. return rate;
  549. }
  550. static void stdclock_set_rate(struct snd_ice1712 *ice, unsigned int rate)
  551. {
  552. int i;
  553. for (i = 0; i < ARRAY_SIZE(stdclock_rate_list); i++) {
  554. if (stdclock_rate_list[i] == rate) {
  555. outb(i, ICEMT1724(ice, RATE));
  556. return;
  557. }
  558. }
  559. }
  560. static unsigned char stdclock_set_mclk(struct snd_ice1712 *ice,
  561. unsigned int rate)
  562. {
  563. unsigned char val, old;
  564. /* check MT02 */
  565. if (ice->eeprom.data[ICE_EEP2_ACLINK] & VT1724_CFG_PRO_I2S) {
  566. val = old = inb(ICEMT1724(ice, I2S_FORMAT));
  567. if (rate > 96000)
  568. val |= VT1724_MT_I2S_MCLK_128X; /* 128x MCLK */
  569. else
  570. val &= ~VT1724_MT_I2S_MCLK_128X; /* 256x MCLK */
  571. if (val != old) {
  572. outb(val, ICEMT1724(ice, I2S_FORMAT));
  573. /* master clock changed */
  574. return 1;
  575. }
  576. }
  577. /* no change in master clock */
  578. return 0;
  579. }
  580. static int snd_vt1724_set_pro_rate(struct snd_ice1712 *ice, unsigned int rate,
  581. int force)
  582. {
  583. unsigned long flags;
  584. unsigned char mclk_change;
  585. unsigned int i, old_rate;
  586. if (rate > ice->hw_rates->list[ice->hw_rates->count - 1])
  587. return -EINVAL;
  588. spin_lock_irqsave(&ice->reg_lock, flags);
  589. if ((inb(ICEMT1724(ice, DMA_CONTROL)) & DMA_STARTS) ||
  590. (inb(ICEMT1724(ice, DMA_PAUSE)) & DMA_PAUSES)) {
  591. /* running? we cannot change the rate now... */
  592. spin_unlock_irqrestore(&ice->reg_lock, flags);
  593. return ((rate == ice->cur_rate) && !force) ? 0 : -EBUSY;
  594. }
  595. if (!force && is_pro_rate_locked(ice)) {
  596. /* comparing required and current rate - makes sense for
  597. * internal clock only */
  598. spin_unlock_irqrestore(&ice->reg_lock, flags);
  599. return (rate == ice->cur_rate) ? 0 : -EBUSY;
  600. }
  601. if (force || !ice->is_spdif_master(ice)) {
  602. /* force means the rate was switched by ucontrol, otherwise
  603. * setting clock rate for internal clock mode */
  604. old_rate = ice->get_rate(ice);
  605. if (force || (old_rate != rate))
  606. ice->set_rate(ice, rate);
  607. else if (rate == ice->cur_rate) {
  608. spin_unlock_irqrestore(&ice->reg_lock, flags);
  609. return 0;
  610. }
  611. }
  612. ice->cur_rate = rate;
  613. /* setting master clock */
  614. mclk_change = ice->set_mclk(ice, rate);
  615. spin_unlock_irqrestore(&ice->reg_lock, flags);
  616. if (mclk_change && ice->gpio.i2s_mclk_changed)
  617. ice->gpio.i2s_mclk_changed(ice);
  618. if (ice->gpio.set_pro_rate)
  619. ice->gpio.set_pro_rate(ice, rate);
  620. /* set up codecs */
  621. for (i = 0; i < ice->akm_codecs; i++) {
  622. if (ice->akm[i].ops.set_rate_val)
  623. ice->akm[i].ops.set_rate_val(&ice->akm[i], rate);
  624. }
  625. if (ice->spdif.ops.setup_rate)
  626. ice->spdif.ops.setup_rate(ice, rate);
  627. return 0;
  628. }
  629. static int snd_vt1724_pcm_hw_params(struct snd_pcm_substream *substream,
  630. struct snd_pcm_hw_params *hw_params)
  631. {
  632. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  633. int i, chs, err;
  634. chs = params_channels(hw_params);
  635. mutex_lock(&ice->open_mutex);
  636. /* mark surround channels */
  637. if (substream == ice->playback_pro_substream) {
  638. /* PDMA0 can be multi-channel up to 8 */
  639. chs = chs / 2 - 1;
  640. for (i = 0; i < chs; i++) {
  641. if (ice->pcm_reserved[i] &&
  642. ice->pcm_reserved[i] != substream) {
  643. mutex_unlock(&ice->open_mutex);
  644. return -EBUSY;
  645. }
  646. ice->pcm_reserved[i] = substream;
  647. }
  648. for (; i < 3; i++) {
  649. if (ice->pcm_reserved[i] == substream)
  650. ice->pcm_reserved[i] = NULL;
  651. }
  652. } else {
  653. for (i = 0; i < 3; i++) {
  654. /* check individual playback stream */
  655. if (ice->playback_con_substream_ds[i] == substream) {
  656. if (ice->pcm_reserved[i] &&
  657. ice->pcm_reserved[i] != substream) {
  658. mutex_unlock(&ice->open_mutex);
  659. return -EBUSY;
  660. }
  661. ice->pcm_reserved[i] = substream;
  662. break;
  663. }
  664. }
  665. }
  666. mutex_unlock(&ice->open_mutex);
  667. err = snd_vt1724_set_pro_rate(ice, params_rate(hw_params), 0);
  668. if (err < 0)
  669. return err;
  670. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  671. }
  672. static int snd_vt1724_pcm_hw_free(struct snd_pcm_substream *substream)
  673. {
  674. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  675. int i;
  676. mutex_lock(&ice->open_mutex);
  677. /* unmark surround channels */
  678. for (i = 0; i < 3; i++)
  679. if (ice->pcm_reserved[i] == substream)
  680. ice->pcm_reserved[i] = NULL;
  681. mutex_unlock(&ice->open_mutex);
  682. return snd_pcm_lib_free_pages(substream);
  683. }
  684. static int snd_vt1724_playback_pro_prepare(struct snd_pcm_substream *substream)
  685. {
  686. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  687. unsigned char val;
  688. unsigned int size;
  689. spin_lock_irq(&ice->reg_lock);
  690. val = (8 - substream->runtime->channels) >> 1;
  691. outb(val, ICEMT1724(ice, BURST));
  692. outl(substream->runtime->dma_addr, ICEMT1724(ice, PLAYBACK_ADDR));
  693. size = (snd_pcm_lib_buffer_bytes(substream) >> 2) - 1;
  694. /* outl(size, ICEMT1724(ice, PLAYBACK_SIZE)); */
  695. outw(size, ICEMT1724(ice, PLAYBACK_SIZE));
  696. outb(size >> 16, ICEMT1724(ice, PLAYBACK_SIZE) + 2);
  697. size = (snd_pcm_lib_period_bytes(substream) >> 2) - 1;
  698. /* outl(size, ICEMT1724(ice, PLAYBACK_COUNT)); */
  699. outw(size, ICEMT1724(ice, PLAYBACK_COUNT));
  700. outb(size >> 16, ICEMT1724(ice, PLAYBACK_COUNT) + 2);
  701. spin_unlock_irq(&ice->reg_lock);
  702. /*
  703. dev_dbg(ice->card->dev, "pro prepare: ch = %d, addr = 0x%x, "
  704. "buffer = 0x%x, period = 0x%x\n",
  705. substream->runtime->channels,
  706. (unsigned int)substream->runtime->dma_addr,
  707. snd_pcm_lib_buffer_bytes(substream),
  708. snd_pcm_lib_period_bytes(substream));
  709. */
  710. return 0;
  711. }
  712. static snd_pcm_uframes_t snd_vt1724_playback_pro_pointer(struct snd_pcm_substream *substream)
  713. {
  714. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  715. size_t ptr;
  716. if (!(inl(ICEMT1724(ice, DMA_CONTROL)) & VT1724_PDMA0_START))
  717. return 0;
  718. #if 0 /* read PLAYBACK_ADDR */
  719. ptr = inl(ICEMT1724(ice, PLAYBACK_ADDR));
  720. if (ptr < substream->runtime->dma_addr) {
  721. dev_dbg(ice->card->dev, "invalid negative ptr\n");
  722. return 0;
  723. }
  724. ptr -= substream->runtime->dma_addr;
  725. ptr = bytes_to_frames(substream->runtime, ptr);
  726. if (ptr >= substream->runtime->buffer_size) {
  727. dev_dbg(ice->card->dev, "invalid ptr %d (size=%d)\n",
  728. (int)ptr, (int)substream->runtime->period_size);
  729. return 0;
  730. }
  731. #else /* read PLAYBACK_SIZE */
  732. ptr = inl(ICEMT1724(ice, PLAYBACK_SIZE)) & 0xffffff;
  733. ptr = (ptr + 1) << 2;
  734. ptr = bytes_to_frames(substream->runtime, ptr);
  735. if (!ptr)
  736. ;
  737. else if (ptr <= substream->runtime->buffer_size)
  738. ptr = substream->runtime->buffer_size - ptr;
  739. else {
  740. dev_dbg(ice->card->dev, "invalid ptr %d (size=%d)\n",
  741. (int)ptr, (int)substream->runtime->buffer_size);
  742. ptr = 0;
  743. }
  744. #endif
  745. return ptr;
  746. }
  747. static int snd_vt1724_pcm_prepare(struct snd_pcm_substream *substream)
  748. {
  749. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  750. const struct vt1724_pcm_reg *reg = substream->runtime->private_data;
  751. spin_lock_irq(&ice->reg_lock);
  752. outl(substream->runtime->dma_addr, ice->profi_port + reg->addr);
  753. outw((snd_pcm_lib_buffer_bytes(substream) >> 2) - 1,
  754. ice->profi_port + reg->size);
  755. outw((snd_pcm_lib_period_bytes(substream) >> 2) - 1,
  756. ice->profi_port + reg->count);
  757. spin_unlock_irq(&ice->reg_lock);
  758. return 0;
  759. }
  760. static snd_pcm_uframes_t snd_vt1724_pcm_pointer(struct snd_pcm_substream *substream)
  761. {
  762. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  763. const struct vt1724_pcm_reg *reg = substream->runtime->private_data;
  764. size_t ptr;
  765. if (!(inl(ICEMT1724(ice, DMA_CONTROL)) & reg->start))
  766. return 0;
  767. #if 0 /* use ADDR register */
  768. ptr = inl(ice->profi_port + reg->addr);
  769. ptr -= substream->runtime->dma_addr;
  770. return bytes_to_frames(substream->runtime, ptr);
  771. #else /* use SIZE register */
  772. ptr = inw(ice->profi_port + reg->size);
  773. ptr = (ptr + 1) << 2;
  774. ptr = bytes_to_frames(substream->runtime, ptr);
  775. if (!ptr)
  776. ;
  777. else if (ptr <= substream->runtime->buffer_size)
  778. ptr = substream->runtime->buffer_size - ptr;
  779. else {
  780. dev_dbg(ice->card->dev, "invalid ptr %d (size=%d)\n",
  781. (int)ptr, (int)substream->runtime->buffer_size);
  782. ptr = 0;
  783. }
  784. return ptr;
  785. #endif
  786. }
  787. static const struct vt1724_pcm_reg vt1724_pdma0_reg = {
  788. .addr = VT1724_MT_PLAYBACK_ADDR,
  789. .size = VT1724_MT_PLAYBACK_SIZE,
  790. .count = VT1724_MT_PLAYBACK_COUNT,
  791. .start = VT1724_PDMA0_START,
  792. };
  793. static const struct vt1724_pcm_reg vt1724_pdma4_reg = {
  794. .addr = VT1724_MT_PDMA4_ADDR,
  795. .size = VT1724_MT_PDMA4_SIZE,
  796. .count = VT1724_MT_PDMA4_COUNT,
  797. .start = VT1724_PDMA4_START,
  798. };
  799. static const struct vt1724_pcm_reg vt1724_rdma0_reg = {
  800. .addr = VT1724_MT_CAPTURE_ADDR,
  801. .size = VT1724_MT_CAPTURE_SIZE,
  802. .count = VT1724_MT_CAPTURE_COUNT,
  803. .start = VT1724_RDMA0_START,
  804. };
  805. static const struct vt1724_pcm_reg vt1724_rdma1_reg = {
  806. .addr = VT1724_MT_RDMA1_ADDR,
  807. .size = VT1724_MT_RDMA1_SIZE,
  808. .count = VT1724_MT_RDMA1_COUNT,
  809. .start = VT1724_RDMA1_START,
  810. };
  811. #define vt1724_playback_pro_reg vt1724_pdma0_reg
  812. #define vt1724_playback_spdif_reg vt1724_pdma4_reg
  813. #define vt1724_capture_pro_reg vt1724_rdma0_reg
  814. #define vt1724_capture_spdif_reg vt1724_rdma1_reg
  815. static const struct snd_pcm_hardware snd_vt1724_playback_pro = {
  816. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  817. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  818. SNDRV_PCM_INFO_MMAP_VALID |
  819. SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
  820. .formats = SNDRV_PCM_FMTBIT_S32_LE,
  821. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_192000,
  822. .rate_min = 8000,
  823. .rate_max = 192000,
  824. .channels_min = 2,
  825. .channels_max = 8,
  826. .buffer_bytes_max = (1UL << 21), /* 19bits dword */
  827. .period_bytes_min = 8 * 4 * 2, /* FIXME: constraints needed */
  828. .period_bytes_max = (1UL << 21),
  829. .periods_min = 2,
  830. .periods_max = 1024,
  831. };
  832. static const struct snd_pcm_hardware snd_vt1724_spdif = {
  833. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  834. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  835. SNDRV_PCM_INFO_MMAP_VALID |
  836. SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
  837. .formats = SNDRV_PCM_FMTBIT_S32_LE,
  838. .rates = (SNDRV_PCM_RATE_32000|SNDRV_PCM_RATE_44100|
  839. SNDRV_PCM_RATE_48000|SNDRV_PCM_RATE_88200|
  840. SNDRV_PCM_RATE_96000|SNDRV_PCM_RATE_176400|
  841. SNDRV_PCM_RATE_192000),
  842. .rate_min = 32000,
  843. .rate_max = 192000,
  844. .channels_min = 2,
  845. .channels_max = 2,
  846. .buffer_bytes_max = (1UL << 18), /* 16bits dword */
  847. .period_bytes_min = 2 * 4 * 2,
  848. .period_bytes_max = (1UL << 18),
  849. .periods_min = 2,
  850. .periods_max = 1024,
  851. };
  852. static const struct snd_pcm_hardware snd_vt1724_2ch_stereo = {
  853. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  854. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  855. SNDRV_PCM_INFO_MMAP_VALID |
  856. SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
  857. .formats = SNDRV_PCM_FMTBIT_S32_LE,
  858. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_192000,
  859. .rate_min = 8000,
  860. .rate_max = 192000,
  861. .channels_min = 2,
  862. .channels_max = 2,
  863. .buffer_bytes_max = (1UL << 18), /* 16bits dword */
  864. .period_bytes_min = 2 * 4 * 2,
  865. .period_bytes_max = (1UL << 18),
  866. .periods_min = 2,
  867. .periods_max = 1024,
  868. };
  869. /*
  870. * set rate constraints
  871. */
  872. static void set_std_hw_rates(struct snd_ice1712 *ice)
  873. {
  874. if (ice->eeprom.data[ICE_EEP2_ACLINK] & VT1724_CFG_PRO_I2S) {
  875. /* I2S */
  876. /* VT1720 doesn't support more than 96kHz */
  877. if ((ice->eeprom.data[ICE_EEP2_I2S] & 0x08) && !ice->vt1720)
  878. ice->hw_rates = &hw_constraints_rates_192;
  879. else
  880. ice->hw_rates = &hw_constraints_rates_96;
  881. } else {
  882. /* ACLINK */
  883. ice->hw_rates = &hw_constraints_rates_48;
  884. }
  885. }
  886. static int set_rate_constraints(struct snd_ice1712 *ice,
  887. struct snd_pcm_substream *substream)
  888. {
  889. struct snd_pcm_runtime *runtime = substream->runtime;
  890. runtime->hw.rate_min = ice->hw_rates->list[0];
  891. runtime->hw.rate_max = ice->hw_rates->list[ice->hw_rates->count - 1];
  892. runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
  893. return snd_pcm_hw_constraint_list(runtime, 0,
  894. SNDRV_PCM_HW_PARAM_RATE,
  895. ice->hw_rates);
  896. }
  897. /* if the card has the internal rate locked (is_pro_locked), limit runtime
  898. hw rates to the current internal rate only.
  899. */
  900. static void constrain_rate_if_locked(struct snd_pcm_substream *substream)
  901. {
  902. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  903. struct snd_pcm_runtime *runtime = substream->runtime;
  904. unsigned int rate;
  905. if (is_pro_rate_locked(ice)) {
  906. rate = ice->get_rate(ice);
  907. if (rate >= runtime->hw.rate_min
  908. && rate <= runtime->hw.rate_max) {
  909. runtime->hw.rate_min = rate;
  910. runtime->hw.rate_max = rate;
  911. }
  912. }
  913. }
  914. /* multi-channel playback needs alignment 8x32bit regardless of the channels
  915. * actually used
  916. */
  917. #define VT1724_BUFFER_ALIGN 0x20
  918. static int snd_vt1724_playback_pro_open(struct snd_pcm_substream *substream)
  919. {
  920. struct snd_pcm_runtime *runtime = substream->runtime;
  921. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  922. int chs, num_indeps;
  923. runtime->private_data = (void *)&vt1724_playback_pro_reg;
  924. ice->playback_pro_substream = substream;
  925. runtime->hw = snd_vt1724_playback_pro;
  926. snd_pcm_set_sync(substream);
  927. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  928. set_rate_constraints(ice, substream);
  929. mutex_lock(&ice->open_mutex);
  930. /* calculate the currently available channels */
  931. num_indeps = ice->num_total_dacs / 2 - 1;
  932. for (chs = 0; chs < num_indeps; chs++) {
  933. if (ice->pcm_reserved[chs])
  934. break;
  935. }
  936. chs = (chs + 1) * 2;
  937. runtime->hw.channels_max = chs;
  938. if (chs > 2) /* channels must be even */
  939. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 2);
  940. mutex_unlock(&ice->open_mutex);
  941. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
  942. VT1724_BUFFER_ALIGN);
  943. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
  944. VT1724_BUFFER_ALIGN);
  945. constrain_rate_if_locked(substream);
  946. if (ice->pro_open)
  947. ice->pro_open(ice, substream);
  948. return 0;
  949. }
  950. static int snd_vt1724_capture_pro_open(struct snd_pcm_substream *substream)
  951. {
  952. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  953. struct snd_pcm_runtime *runtime = substream->runtime;
  954. runtime->private_data = (void *)&vt1724_capture_pro_reg;
  955. ice->capture_pro_substream = substream;
  956. runtime->hw = snd_vt1724_2ch_stereo;
  957. snd_pcm_set_sync(substream);
  958. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  959. set_rate_constraints(ice, substream);
  960. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
  961. VT1724_BUFFER_ALIGN);
  962. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
  963. VT1724_BUFFER_ALIGN);
  964. constrain_rate_if_locked(substream);
  965. if (ice->pro_open)
  966. ice->pro_open(ice, substream);
  967. return 0;
  968. }
  969. static int snd_vt1724_playback_pro_close(struct snd_pcm_substream *substream)
  970. {
  971. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  972. if (PRO_RATE_RESET)
  973. snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
  974. ice->playback_pro_substream = NULL;
  975. return 0;
  976. }
  977. static int snd_vt1724_capture_pro_close(struct snd_pcm_substream *substream)
  978. {
  979. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  980. if (PRO_RATE_RESET)
  981. snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
  982. ice->capture_pro_substream = NULL;
  983. return 0;
  984. }
  985. static struct snd_pcm_ops snd_vt1724_playback_pro_ops = {
  986. .open = snd_vt1724_playback_pro_open,
  987. .close = snd_vt1724_playback_pro_close,
  988. .ioctl = snd_pcm_lib_ioctl,
  989. .hw_params = snd_vt1724_pcm_hw_params,
  990. .hw_free = snd_vt1724_pcm_hw_free,
  991. .prepare = snd_vt1724_playback_pro_prepare,
  992. .trigger = snd_vt1724_pcm_trigger,
  993. .pointer = snd_vt1724_playback_pro_pointer,
  994. };
  995. static struct snd_pcm_ops snd_vt1724_capture_pro_ops = {
  996. .open = snd_vt1724_capture_pro_open,
  997. .close = snd_vt1724_capture_pro_close,
  998. .ioctl = snd_pcm_lib_ioctl,
  999. .hw_params = snd_vt1724_pcm_hw_params,
  1000. .hw_free = snd_vt1724_pcm_hw_free,
  1001. .prepare = snd_vt1724_pcm_prepare,
  1002. .trigger = snd_vt1724_pcm_trigger,
  1003. .pointer = snd_vt1724_pcm_pointer,
  1004. };
  1005. static int snd_vt1724_pcm_profi(struct snd_ice1712 *ice, int device)
  1006. {
  1007. struct snd_pcm *pcm;
  1008. int capt, err;
  1009. if ((ice->eeprom.data[ICE_EEP2_SYSCONF] & VT1724_CFG_ADC_MASK) ==
  1010. VT1724_CFG_ADC_NONE)
  1011. capt = 0;
  1012. else
  1013. capt = 1;
  1014. err = snd_pcm_new(ice->card, "ICE1724", device, 1, capt, &pcm);
  1015. if (err < 0)
  1016. return err;
  1017. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_vt1724_playback_pro_ops);
  1018. if (capt)
  1019. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  1020. &snd_vt1724_capture_pro_ops);
  1021. pcm->private_data = ice;
  1022. pcm->info_flags = 0;
  1023. strcpy(pcm->name, "ICE1724");
  1024. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1025. snd_dma_pci_data(ice->pci),
  1026. 256*1024, 256*1024);
  1027. ice->pcm_pro = pcm;
  1028. return 0;
  1029. }
  1030. /*
  1031. * SPDIF PCM
  1032. */
  1033. /* update spdif control bits; call with reg_lock */
  1034. static void update_spdif_bits(struct snd_ice1712 *ice, unsigned int val)
  1035. {
  1036. unsigned char cbit, disabled;
  1037. cbit = inb(ICEREG1724(ice, SPDIF_CFG));
  1038. disabled = cbit & ~VT1724_CFG_SPDIF_OUT_EN;
  1039. if (cbit != disabled)
  1040. outb(disabled, ICEREG1724(ice, SPDIF_CFG));
  1041. outw(val, ICEMT1724(ice, SPDIF_CTRL));
  1042. if (cbit != disabled)
  1043. outb(cbit, ICEREG1724(ice, SPDIF_CFG));
  1044. outw(val, ICEMT1724(ice, SPDIF_CTRL));
  1045. }
  1046. /* update SPDIF control bits according to the given rate */
  1047. static void update_spdif_rate(struct snd_ice1712 *ice, unsigned int rate)
  1048. {
  1049. unsigned int val, nval;
  1050. unsigned long flags;
  1051. spin_lock_irqsave(&ice->reg_lock, flags);
  1052. nval = val = inw(ICEMT1724(ice, SPDIF_CTRL));
  1053. nval &= ~(7 << 12);
  1054. switch (rate) {
  1055. case 44100: break;
  1056. case 48000: nval |= 2 << 12; break;
  1057. case 32000: nval |= 3 << 12; break;
  1058. case 88200: nval |= 4 << 12; break;
  1059. case 96000: nval |= 5 << 12; break;
  1060. case 192000: nval |= 6 << 12; break;
  1061. case 176400: nval |= 7 << 12; break;
  1062. }
  1063. if (val != nval)
  1064. update_spdif_bits(ice, nval);
  1065. spin_unlock_irqrestore(&ice->reg_lock, flags);
  1066. }
  1067. static int snd_vt1724_playback_spdif_prepare(struct snd_pcm_substream *substream)
  1068. {
  1069. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1070. if (!ice->force_pdma4)
  1071. update_spdif_rate(ice, substream->runtime->rate);
  1072. return snd_vt1724_pcm_prepare(substream);
  1073. }
  1074. static int snd_vt1724_playback_spdif_open(struct snd_pcm_substream *substream)
  1075. {
  1076. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1077. struct snd_pcm_runtime *runtime = substream->runtime;
  1078. runtime->private_data = (void *)&vt1724_playback_spdif_reg;
  1079. ice->playback_con_substream = substream;
  1080. if (ice->force_pdma4) {
  1081. runtime->hw = snd_vt1724_2ch_stereo;
  1082. set_rate_constraints(ice, substream);
  1083. } else
  1084. runtime->hw = snd_vt1724_spdif;
  1085. snd_pcm_set_sync(substream);
  1086. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  1087. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
  1088. VT1724_BUFFER_ALIGN);
  1089. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
  1090. VT1724_BUFFER_ALIGN);
  1091. constrain_rate_if_locked(substream);
  1092. if (ice->spdif.ops.open)
  1093. ice->spdif.ops.open(ice, substream);
  1094. return 0;
  1095. }
  1096. static int snd_vt1724_playback_spdif_close(struct snd_pcm_substream *substream)
  1097. {
  1098. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1099. if (PRO_RATE_RESET)
  1100. snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
  1101. ice->playback_con_substream = NULL;
  1102. if (ice->spdif.ops.close)
  1103. ice->spdif.ops.close(ice, substream);
  1104. return 0;
  1105. }
  1106. static int snd_vt1724_capture_spdif_open(struct snd_pcm_substream *substream)
  1107. {
  1108. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1109. struct snd_pcm_runtime *runtime = substream->runtime;
  1110. runtime->private_data = (void *)&vt1724_capture_spdif_reg;
  1111. ice->capture_con_substream = substream;
  1112. if (ice->force_rdma1) {
  1113. runtime->hw = snd_vt1724_2ch_stereo;
  1114. set_rate_constraints(ice, substream);
  1115. } else
  1116. runtime->hw = snd_vt1724_spdif;
  1117. snd_pcm_set_sync(substream);
  1118. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  1119. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
  1120. VT1724_BUFFER_ALIGN);
  1121. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
  1122. VT1724_BUFFER_ALIGN);
  1123. constrain_rate_if_locked(substream);
  1124. if (ice->spdif.ops.open)
  1125. ice->spdif.ops.open(ice, substream);
  1126. return 0;
  1127. }
  1128. static int snd_vt1724_capture_spdif_close(struct snd_pcm_substream *substream)
  1129. {
  1130. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1131. if (PRO_RATE_RESET)
  1132. snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
  1133. ice->capture_con_substream = NULL;
  1134. if (ice->spdif.ops.close)
  1135. ice->spdif.ops.close(ice, substream);
  1136. return 0;
  1137. }
  1138. static struct snd_pcm_ops snd_vt1724_playback_spdif_ops = {
  1139. .open = snd_vt1724_playback_spdif_open,
  1140. .close = snd_vt1724_playback_spdif_close,
  1141. .ioctl = snd_pcm_lib_ioctl,
  1142. .hw_params = snd_vt1724_pcm_hw_params,
  1143. .hw_free = snd_vt1724_pcm_hw_free,
  1144. .prepare = snd_vt1724_playback_spdif_prepare,
  1145. .trigger = snd_vt1724_pcm_trigger,
  1146. .pointer = snd_vt1724_pcm_pointer,
  1147. };
  1148. static struct snd_pcm_ops snd_vt1724_capture_spdif_ops = {
  1149. .open = snd_vt1724_capture_spdif_open,
  1150. .close = snd_vt1724_capture_spdif_close,
  1151. .ioctl = snd_pcm_lib_ioctl,
  1152. .hw_params = snd_vt1724_pcm_hw_params,
  1153. .hw_free = snd_vt1724_pcm_hw_free,
  1154. .prepare = snd_vt1724_pcm_prepare,
  1155. .trigger = snd_vt1724_pcm_trigger,
  1156. .pointer = snd_vt1724_pcm_pointer,
  1157. };
  1158. static int snd_vt1724_pcm_spdif(struct snd_ice1712 *ice, int device)
  1159. {
  1160. char *name;
  1161. struct snd_pcm *pcm;
  1162. int play, capt;
  1163. int err;
  1164. if (ice->force_pdma4 ||
  1165. (ice->eeprom.data[ICE_EEP2_SPDIF] & VT1724_CFG_SPDIF_OUT_INT)) {
  1166. play = 1;
  1167. ice->has_spdif = 1;
  1168. } else
  1169. play = 0;
  1170. if (ice->force_rdma1 ||
  1171. (ice->eeprom.data[ICE_EEP2_SPDIF] & VT1724_CFG_SPDIF_IN)) {
  1172. capt = 1;
  1173. ice->has_spdif = 1;
  1174. } else
  1175. capt = 0;
  1176. if (!play && !capt)
  1177. return 0; /* no spdif device */
  1178. if (ice->force_pdma4 || ice->force_rdma1)
  1179. name = "ICE1724 Secondary";
  1180. else
  1181. name = "ICE1724 IEC958";
  1182. err = snd_pcm_new(ice->card, name, device, play, capt, &pcm);
  1183. if (err < 0)
  1184. return err;
  1185. if (play)
  1186. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1187. &snd_vt1724_playback_spdif_ops);
  1188. if (capt)
  1189. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
  1190. &snd_vt1724_capture_spdif_ops);
  1191. pcm->private_data = ice;
  1192. pcm->info_flags = 0;
  1193. strcpy(pcm->name, name);
  1194. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1195. snd_dma_pci_data(ice->pci),
  1196. 256*1024, 256*1024);
  1197. ice->pcm = pcm;
  1198. return 0;
  1199. }
  1200. /*
  1201. * independent surround PCMs
  1202. */
  1203. static const struct vt1724_pcm_reg vt1724_playback_dma_regs[3] = {
  1204. {
  1205. .addr = VT1724_MT_PDMA1_ADDR,
  1206. .size = VT1724_MT_PDMA1_SIZE,
  1207. .count = VT1724_MT_PDMA1_COUNT,
  1208. .start = VT1724_PDMA1_START,
  1209. },
  1210. {
  1211. .addr = VT1724_MT_PDMA2_ADDR,
  1212. .size = VT1724_MT_PDMA2_SIZE,
  1213. .count = VT1724_MT_PDMA2_COUNT,
  1214. .start = VT1724_PDMA2_START,
  1215. },
  1216. {
  1217. .addr = VT1724_MT_PDMA3_ADDR,
  1218. .size = VT1724_MT_PDMA3_SIZE,
  1219. .count = VT1724_MT_PDMA3_COUNT,
  1220. .start = VT1724_PDMA3_START,
  1221. },
  1222. };
  1223. static int snd_vt1724_playback_indep_prepare(struct snd_pcm_substream *substream)
  1224. {
  1225. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1226. unsigned char val;
  1227. spin_lock_irq(&ice->reg_lock);
  1228. val = 3 - substream->number;
  1229. if (inb(ICEMT1724(ice, BURST)) < val)
  1230. outb(val, ICEMT1724(ice, BURST));
  1231. spin_unlock_irq(&ice->reg_lock);
  1232. return snd_vt1724_pcm_prepare(substream);
  1233. }
  1234. static int snd_vt1724_playback_indep_open(struct snd_pcm_substream *substream)
  1235. {
  1236. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1237. struct snd_pcm_runtime *runtime = substream->runtime;
  1238. mutex_lock(&ice->open_mutex);
  1239. /* already used by PDMA0? */
  1240. if (ice->pcm_reserved[substream->number]) {
  1241. mutex_unlock(&ice->open_mutex);
  1242. return -EBUSY; /* FIXME: should handle blocking mode properly */
  1243. }
  1244. mutex_unlock(&ice->open_mutex);
  1245. runtime->private_data = (void *)&vt1724_playback_dma_regs[substream->number];
  1246. ice->playback_con_substream_ds[substream->number] = substream;
  1247. runtime->hw = snd_vt1724_2ch_stereo;
  1248. snd_pcm_set_sync(substream);
  1249. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  1250. set_rate_constraints(ice, substream);
  1251. return 0;
  1252. }
  1253. static int snd_vt1724_playback_indep_close(struct snd_pcm_substream *substream)
  1254. {
  1255. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1256. if (PRO_RATE_RESET)
  1257. snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 0);
  1258. ice->playback_con_substream_ds[substream->number] = NULL;
  1259. ice->pcm_reserved[substream->number] = NULL;
  1260. return 0;
  1261. }
  1262. static struct snd_pcm_ops snd_vt1724_playback_indep_ops = {
  1263. .open = snd_vt1724_playback_indep_open,
  1264. .close = snd_vt1724_playback_indep_close,
  1265. .ioctl = snd_pcm_lib_ioctl,
  1266. .hw_params = snd_vt1724_pcm_hw_params,
  1267. .hw_free = snd_vt1724_pcm_hw_free,
  1268. .prepare = snd_vt1724_playback_indep_prepare,
  1269. .trigger = snd_vt1724_pcm_trigger,
  1270. .pointer = snd_vt1724_pcm_pointer,
  1271. };
  1272. static int snd_vt1724_pcm_indep(struct snd_ice1712 *ice, int device)
  1273. {
  1274. struct snd_pcm *pcm;
  1275. int play;
  1276. int err;
  1277. play = ice->num_total_dacs / 2 - 1;
  1278. if (play <= 0)
  1279. return 0;
  1280. err = snd_pcm_new(ice->card, "ICE1724 Surrounds", device, play, 0, &pcm);
  1281. if (err < 0)
  1282. return err;
  1283. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1284. &snd_vt1724_playback_indep_ops);
  1285. pcm->private_data = ice;
  1286. pcm->info_flags = 0;
  1287. strcpy(pcm->name, "ICE1724 Surround PCM");
  1288. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1289. snd_dma_pci_data(ice->pci),
  1290. 256*1024, 256*1024);
  1291. ice->pcm_ds = pcm;
  1292. return 0;
  1293. }
  1294. /*
  1295. * Mixer section
  1296. */
  1297. static int snd_vt1724_ac97_mixer(struct snd_ice1712 *ice)
  1298. {
  1299. int err;
  1300. if (!(ice->eeprom.data[ICE_EEP2_ACLINK] & VT1724_CFG_PRO_I2S)) {
  1301. struct snd_ac97_bus *pbus;
  1302. struct snd_ac97_template ac97;
  1303. static struct snd_ac97_bus_ops ops = {
  1304. .write = snd_vt1724_ac97_write,
  1305. .read = snd_vt1724_ac97_read,
  1306. };
  1307. /* cold reset */
  1308. outb(inb(ICEMT1724(ice, AC97_CMD)) | 0x80, ICEMT1724(ice, AC97_CMD));
  1309. mdelay(5); /* FIXME */
  1310. outb(inb(ICEMT1724(ice, AC97_CMD)) & ~0x80, ICEMT1724(ice, AC97_CMD));
  1311. err = snd_ac97_bus(ice->card, 0, &ops, NULL, &pbus);
  1312. if (err < 0)
  1313. return err;
  1314. memset(&ac97, 0, sizeof(ac97));
  1315. ac97.private_data = ice;
  1316. err = snd_ac97_mixer(pbus, &ac97, &ice->ac97);
  1317. if (err < 0)
  1318. dev_warn(ice->card->dev,
  1319. "cannot initialize pro ac97, skipped\n");
  1320. else
  1321. return 0;
  1322. }
  1323. /* I2S mixer only */
  1324. strcat(ice->card->mixername, "ICE1724 - multitrack");
  1325. return 0;
  1326. }
  1327. /*
  1328. *
  1329. */
  1330. static inline unsigned int eeprom_triple(struct snd_ice1712 *ice, int idx)
  1331. {
  1332. return (unsigned int)ice->eeprom.data[idx] | \
  1333. ((unsigned int)ice->eeprom.data[idx + 1] << 8) | \
  1334. ((unsigned int)ice->eeprom.data[idx + 2] << 16);
  1335. }
  1336. static void snd_vt1724_proc_read(struct snd_info_entry *entry,
  1337. struct snd_info_buffer *buffer)
  1338. {
  1339. struct snd_ice1712 *ice = entry->private_data;
  1340. unsigned int idx;
  1341. snd_iprintf(buffer, "%s\n\n", ice->card->longname);
  1342. snd_iprintf(buffer, "EEPROM:\n");
  1343. snd_iprintf(buffer, " Subvendor : 0x%x\n", ice->eeprom.subvendor);
  1344. snd_iprintf(buffer, " Size : %i bytes\n", ice->eeprom.size);
  1345. snd_iprintf(buffer, " Version : %i\n", ice->eeprom.version);
  1346. snd_iprintf(buffer, " System Config : 0x%x\n",
  1347. ice->eeprom.data[ICE_EEP2_SYSCONF]);
  1348. snd_iprintf(buffer, " ACLink : 0x%x\n",
  1349. ice->eeprom.data[ICE_EEP2_ACLINK]);
  1350. snd_iprintf(buffer, " I2S : 0x%x\n",
  1351. ice->eeprom.data[ICE_EEP2_I2S]);
  1352. snd_iprintf(buffer, " S/PDIF : 0x%x\n",
  1353. ice->eeprom.data[ICE_EEP2_SPDIF]);
  1354. snd_iprintf(buffer, " GPIO direction : 0x%x\n",
  1355. ice->eeprom.gpiodir);
  1356. snd_iprintf(buffer, " GPIO mask : 0x%x\n",
  1357. ice->eeprom.gpiomask);
  1358. snd_iprintf(buffer, " GPIO state : 0x%x\n",
  1359. ice->eeprom.gpiostate);
  1360. for (idx = 0x12; idx < ice->eeprom.size; idx++)
  1361. snd_iprintf(buffer, " Extra #%02i : 0x%x\n",
  1362. idx, ice->eeprom.data[idx]);
  1363. snd_iprintf(buffer, "\nRegisters:\n");
  1364. snd_iprintf(buffer, " PSDOUT03 : 0x%08x\n",
  1365. (unsigned)inl(ICEMT1724(ice, ROUTE_PLAYBACK)));
  1366. for (idx = 0x0; idx < 0x20 ; idx++)
  1367. snd_iprintf(buffer, " CCS%02x : 0x%02x\n",
  1368. idx, inb(ice->port+idx));
  1369. for (idx = 0x0; idx < 0x30 ; idx++)
  1370. snd_iprintf(buffer, " MT%02x : 0x%02x\n",
  1371. idx, inb(ice->profi_port+idx));
  1372. }
  1373. static void snd_vt1724_proc_init(struct snd_ice1712 *ice)
  1374. {
  1375. struct snd_info_entry *entry;
  1376. if (!snd_card_proc_new(ice->card, "ice1724", &entry))
  1377. snd_info_set_text_ops(entry, ice, snd_vt1724_proc_read);
  1378. }
  1379. /*
  1380. *
  1381. */
  1382. static int snd_vt1724_eeprom_info(struct snd_kcontrol *kcontrol,
  1383. struct snd_ctl_elem_info *uinfo)
  1384. {
  1385. uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
  1386. uinfo->count = sizeof(struct snd_ice1712_eeprom);
  1387. return 0;
  1388. }
  1389. static int snd_vt1724_eeprom_get(struct snd_kcontrol *kcontrol,
  1390. struct snd_ctl_elem_value *ucontrol)
  1391. {
  1392. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1393. memcpy(ucontrol->value.bytes.data, &ice->eeprom, sizeof(ice->eeprom));
  1394. return 0;
  1395. }
  1396. static struct snd_kcontrol_new snd_vt1724_eeprom = {
  1397. .iface = SNDRV_CTL_ELEM_IFACE_CARD,
  1398. .name = "ICE1724 EEPROM",
  1399. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1400. .info = snd_vt1724_eeprom_info,
  1401. .get = snd_vt1724_eeprom_get
  1402. };
  1403. /*
  1404. */
  1405. static int snd_vt1724_spdif_info(struct snd_kcontrol *kcontrol,
  1406. struct snd_ctl_elem_info *uinfo)
  1407. {
  1408. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1409. uinfo->count = 1;
  1410. return 0;
  1411. }
  1412. static unsigned int encode_spdif_bits(struct snd_aes_iec958 *diga)
  1413. {
  1414. unsigned int val, rbits;
  1415. val = diga->status[0] & 0x03; /* professional, non-audio */
  1416. if (val & 0x01) {
  1417. /* professional */
  1418. if ((diga->status[0] & IEC958_AES0_PRO_EMPHASIS) ==
  1419. IEC958_AES0_PRO_EMPHASIS_5015)
  1420. val |= 1U << 3;
  1421. rbits = (diga->status[4] >> 3) & 0x0f;
  1422. if (rbits) {
  1423. switch (rbits) {
  1424. case 2: val |= 5 << 12; break; /* 96k */
  1425. case 3: val |= 6 << 12; break; /* 192k */
  1426. case 10: val |= 4 << 12; break; /* 88.2k */
  1427. case 11: val |= 7 << 12; break; /* 176.4k */
  1428. }
  1429. } else {
  1430. switch (diga->status[0] & IEC958_AES0_PRO_FS) {
  1431. case IEC958_AES0_PRO_FS_44100:
  1432. break;
  1433. case IEC958_AES0_PRO_FS_32000:
  1434. val |= 3U << 12;
  1435. break;
  1436. default:
  1437. val |= 2U << 12;
  1438. break;
  1439. }
  1440. }
  1441. } else {
  1442. /* consumer */
  1443. val |= diga->status[1] & 0x04; /* copyright */
  1444. if ((diga->status[0] & IEC958_AES0_CON_EMPHASIS) ==
  1445. IEC958_AES0_CON_EMPHASIS_5015)
  1446. val |= 1U << 3;
  1447. val |= (unsigned int)(diga->status[1] & 0x3f) << 4; /* category */
  1448. val |= (unsigned int)(diga->status[3] & IEC958_AES3_CON_FS) << 12; /* fs */
  1449. }
  1450. return val;
  1451. }
  1452. static void decode_spdif_bits(struct snd_aes_iec958 *diga, unsigned int val)
  1453. {
  1454. memset(diga->status, 0, sizeof(diga->status));
  1455. diga->status[0] = val & 0x03; /* professional, non-audio */
  1456. if (val & 0x01) {
  1457. /* professional */
  1458. if (val & (1U << 3))
  1459. diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_5015;
  1460. switch ((val >> 12) & 0x7) {
  1461. case 0:
  1462. break;
  1463. case 2:
  1464. diga->status[0] |= IEC958_AES0_PRO_FS_32000;
  1465. break;
  1466. default:
  1467. diga->status[0] |= IEC958_AES0_PRO_FS_48000;
  1468. break;
  1469. }
  1470. } else {
  1471. /* consumer */
  1472. diga->status[0] |= val & (1U << 2); /* copyright */
  1473. if (val & (1U << 3))
  1474. diga->status[0] |= IEC958_AES0_CON_EMPHASIS_5015;
  1475. diga->status[1] |= (val >> 4) & 0x3f; /* category */
  1476. diga->status[3] |= (val >> 12) & 0x07; /* fs */
  1477. }
  1478. }
  1479. static int snd_vt1724_spdif_default_get(struct snd_kcontrol *kcontrol,
  1480. struct snd_ctl_elem_value *ucontrol)
  1481. {
  1482. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1483. unsigned int val;
  1484. val = inw(ICEMT1724(ice, SPDIF_CTRL));
  1485. decode_spdif_bits(&ucontrol->value.iec958, val);
  1486. return 0;
  1487. }
  1488. static int snd_vt1724_spdif_default_put(struct snd_kcontrol *kcontrol,
  1489. struct snd_ctl_elem_value *ucontrol)
  1490. {
  1491. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1492. unsigned int val, old;
  1493. val = encode_spdif_bits(&ucontrol->value.iec958);
  1494. spin_lock_irq(&ice->reg_lock);
  1495. old = inw(ICEMT1724(ice, SPDIF_CTRL));
  1496. if (val != old)
  1497. update_spdif_bits(ice, val);
  1498. spin_unlock_irq(&ice->reg_lock);
  1499. return val != old;
  1500. }
  1501. static struct snd_kcontrol_new snd_vt1724_spdif_default =
  1502. {
  1503. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1504. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
  1505. .info = snd_vt1724_spdif_info,
  1506. .get = snd_vt1724_spdif_default_get,
  1507. .put = snd_vt1724_spdif_default_put
  1508. };
  1509. static int snd_vt1724_spdif_maskc_get(struct snd_kcontrol *kcontrol,
  1510. struct snd_ctl_elem_value *ucontrol)
  1511. {
  1512. ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
  1513. IEC958_AES0_PROFESSIONAL |
  1514. IEC958_AES0_CON_NOT_COPYRIGHT |
  1515. IEC958_AES0_CON_EMPHASIS;
  1516. ucontrol->value.iec958.status[1] = IEC958_AES1_CON_ORIGINAL |
  1517. IEC958_AES1_CON_CATEGORY;
  1518. ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS;
  1519. return 0;
  1520. }
  1521. static int snd_vt1724_spdif_maskp_get(struct snd_kcontrol *kcontrol,
  1522. struct snd_ctl_elem_value *ucontrol)
  1523. {
  1524. ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
  1525. IEC958_AES0_PROFESSIONAL |
  1526. IEC958_AES0_PRO_FS |
  1527. IEC958_AES0_PRO_EMPHASIS;
  1528. return 0;
  1529. }
  1530. static struct snd_kcontrol_new snd_vt1724_spdif_maskc =
  1531. {
  1532. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1533. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1534. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
  1535. .info = snd_vt1724_spdif_info,
  1536. .get = snd_vt1724_spdif_maskc_get,
  1537. };
  1538. static struct snd_kcontrol_new snd_vt1724_spdif_maskp =
  1539. {
  1540. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1541. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1542. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK),
  1543. .info = snd_vt1724_spdif_info,
  1544. .get = snd_vt1724_spdif_maskp_get,
  1545. };
  1546. #define snd_vt1724_spdif_sw_info snd_ctl_boolean_mono_info
  1547. static int snd_vt1724_spdif_sw_get(struct snd_kcontrol *kcontrol,
  1548. struct snd_ctl_elem_value *ucontrol)
  1549. {
  1550. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1551. ucontrol->value.integer.value[0] = inb(ICEREG1724(ice, SPDIF_CFG)) &
  1552. VT1724_CFG_SPDIF_OUT_EN ? 1 : 0;
  1553. return 0;
  1554. }
  1555. static int snd_vt1724_spdif_sw_put(struct snd_kcontrol *kcontrol,
  1556. struct snd_ctl_elem_value *ucontrol)
  1557. {
  1558. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1559. unsigned char old, val;
  1560. spin_lock_irq(&ice->reg_lock);
  1561. old = val = inb(ICEREG1724(ice, SPDIF_CFG));
  1562. val &= ~VT1724_CFG_SPDIF_OUT_EN;
  1563. if (ucontrol->value.integer.value[0])
  1564. val |= VT1724_CFG_SPDIF_OUT_EN;
  1565. if (old != val)
  1566. outb(val, ICEREG1724(ice, SPDIF_CFG));
  1567. spin_unlock_irq(&ice->reg_lock);
  1568. return old != val;
  1569. }
  1570. static struct snd_kcontrol_new snd_vt1724_spdif_switch =
  1571. {
  1572. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1573. /* FIXME: the following conflict with IEC958 Playback Route */
  1574. /* .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, SWITCH), */
  1575. .name = SNDRV_CTL_NAME_IEC958("Output ", NONE, SWITCH),
  1576. .info = snd_vt1724_spdif_sw_info,
  1577. .get = snd_vt1724_spdif_sw_get,
  1578. .put = snd_vt1724_spdif_sw_put
  1579. };
  1580. #if 0 /* NOT USED YET */
  1581. /*
  1582. * GPIO access from extern
  1583. */
  1584. #define snd_vt1724_gpio_info snd_ctl_boolean_mono_info
  1585. int snd_vt1724_gpio_get(struct snd_kcontrol *kcontrol,
  1586. struct snd_ctl_elem_value *ucontrol)
  1587. {
  1588. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1589. int shift = kcontrol->private_value & 0xff;
  1590. int invert = (kcontrol->private_value & (1<<24)) ? 1 : 0;
  1591. snd_ice1712_save_gpio_status(ice);
  1592. ucontrol->value.integer.value[0] =
  1593. (snd_ice1712_gpio_read(ice) & (1 << shift) ? 1 : 0) ^ invert;
  1594. snd_ice1712_restore_gpio_status(ice);
  1595. return 0;
  1596. }
  1597. int snd_ice1712_gpio_put(struct snd_kcontrol *kcontrol,
  1598. struct snd_ctl_elem_value *ucontrol)
  1599. {
  1600. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1601. int shift = kcontrol->private_value & 0xff;
  1602. int invert = (kcontrol->private_value & (1<<24)) ? mask : 0;
  1603. unsigned int val, nval;
  1604. if (kcontrol->private_value & (1 << 31))
  1605. return -EPERM;
  1606. nval = (ucontrol->value.integer.value[0] ? (1 << shift) : 0) ^ invert;
  1607. snd_ice1712_save_gpio_status(ice);
  1608. val = snd_ice1712_gpio_read(ice);
  1609. nval |= val & ~(1 << shift);
  1610. if (val != nval)
  1611. snd_ice1712_gpio_write(ice, nval);
  1612. snd_ice1712_restore_gpio_status(ice);
  1613. return val != nval;
  1614. }
  1615. #endif /* NOT USED YET */
  1616. /*
  1617. * rate
  1618. */
  1619. static int snd_vt1724_pro_internal_clock_info(struct snd_kcontrol *kcontrol,
  1620. struct snd_ctl_elem_info *uinfo)
  1621. {
  1622. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1623. int hw_rates_count = ice->hw_rates->count;
  1624. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1625. uinfo->count = 1;
  1626. /* internal clocks */
  1627. uinfo->value.enumerated.items = hw_rates_count;
  1628. /* external clocks */
  1629. if (ice->force_rdma1 ||
  1630. (ice->eeprom.data[ICE_EEP2_SPDIF] & VT1724_CFG_SPDIF_IN))
  1631. uinfo->value.enumerated.items += ice->ext_clock_count;
  1632. /* upper limit - keep at top */
  1633. if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
  1634. uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
  1635. if (uinfo->value.enumerated.item >= hw_rates_count)
  1636. /* ext_clock items */
  1637. strcpy(uinfo->value.enumerated.name,
  1638. ice->ext_clock_names[
  1639. uinfo->value.enumerated.item - hw_rates_count]);
  1640. else
  1641. /* int clock items */
  1642. sprintf(uinfo->value.enumerated.name, "%d",
  1643. ice->hw_rates->list[uinfo->value.enumerated.item]);
  1644. return 0;
  1645. }
  1646. static int snd_vt1724_pro_internal_clock_get(struct snd_kcontrol *kcontrol,
  1647. struct snd_ctl_elem_value *ucontrol)
  1648. {
  1649. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1650. unsigned int i, rate;
  1651. spin_lock_irq(&ice->reg_lock);
  1652. if (ice->is_spdif_master(ice)) {
  1653. ucontrol->value.enumerated.item[0] = ice->hw_rates->count +
  1654. ice->get_spdif_master_type(ice);
  1655. } else {
  1656. rate = ice->get_rate(ice);
  1657. ucontrol->value.enumerated.item[0] = 0;
  1658. for (i = 0; i < ice->hw_rates->count; i++) {
  1659. if (ice->hw_rates->list[i] == rate) {
  1660. ucontrol->value.enumerated.item[0] = i;
  1661. break;
  1662. }
  1663. }
  1664. }
  1665. spin_unlock_irq(&ice->reg_lock);
  1666. return 0;
  1667. }
  1668. static int stdclock_get_spdif_master_type(struct snd_ice1712 *ice)
  1669. {
  1670. /* standard external clock - only single type - SPDIF IN */
  1671. return 0;
  1672. }
  1673. /* setting clock to external - SPDIF */
  1674. static int stdclock_set_spdif_clock(struct snd_ice1712 *ice, int type)
  1675. {
  1676. unsigned char oval;
  1677. unsigned char i2s_oval;
  1678. oval = inb(ICEMT1724(ice, RATE));
  1679. outb(oval | VT1724_SPDIF_MASTER, ICEMT1724(ice, RATE));
  1680. /* setting 256fs */
  1681. i2s_oval = inb(ICEMT1724(ice, I2S_FORMAT));
  1682. outb(i2s_oval & ~VT1724_MT_I2S_MCLK_128X, ICEMT1724(ice, I2S_FORMAT));
  1683. return 0;
  1684. }
  1685. static int snd_vt1724_pro_internal_clock_put(struct snd_kcontrol *kcontrol,
  1686. struct snd_ctl_elem_value *ucontrol)
  1687. {
  1688. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1689. unsigned int old_rate, new_rate;
  1690. unsigned int item = ucontrol->value.enumerated.item[0];
  1691. unsigned int first_ext_clock = ice->hw_rates->count;
  1692. if (item > first_ext_clock + ice->ext_clock_count - 1)
  1693. return -EINVAL;
  1694. /* if rate = 0 => external clock */
  1695. spin_lock_irq(&ice->reg_lock);
  1696. if (ice->is_spdif_master(ice))
  1697. old_rate = 0;
  1698. else
  1699. old_rate = ice->get_rate(ice);
  1700. if (item >= first_ext_clock) {
  1701. /* switching to external clock */
  1702. ice->set_spdif_clock(ice, item - first_ext_clock);
  1703. new_rate = 0;
  1704. } else {
  1705. /* internal on-card clock */
  1706. new_rate = ice->hw_rates->list[item];
  1707. ice->pro_rate_default = new_rate;
  1708. spin_unlock_irq(&ice->reg_lock);
  1709. snd_vt1724_set_pro_rate(ice, ice->pro_rate_default, 1);
  1710. spin_lock_irq(&ice->reg_lock);
  1711. }
  1712. spin_unlock_irq(&ice->reg_lock);
  1713. /* the first switch to the ext. clock mode? */
  1714. if (old_rate != new_rate && !new_rate) {
  1715. /* notify akm chips as well */
  1716. unsigned int i;
  1717. if (ice->gpio.set_pro_rate)
  1718. ice->gpio.set_pro_rate(ice, 0);
  1719. for (i = 0; i < ice->akm_codecs; i++) {
  1720. if (ice->akm[i].ops.set_rate_val)
  1721. ice->akm[i].ops.set_rate_val(&ice->akm[i], 0);
  1722. }
  1723. }
  1724. return old_rate != new_rate;
  1725. }
  1726. static struct snd_kcontrol_new snd_vt1724_pro_internal_clock = {
  1727. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1728. .name = "Multi Track Internal Clock",
  1729. .info = snd_vt1724_pro_internal_clock_info,
  1730. .get = snd_vt1724_pro_internal_clock_get,
  1731. .put = snd_vt1724_pro_internal_clock_put
  1732. };
  1733. #define snd_vt1724_pro_rate_locking_info snd_ctl_boolean_mono_info
  1734. static int snd_vt1724_pro_rate_locking_get(struct snd_kcontrol *kcontrol,
  1735. struct snd_ctl_elem_value *ucontrol)
  1736. {
  1737. ucontrol->value.integer.value[0] = PRO_RATE_LOCKED;
  1738. return 0;
  1739. }
  1740. static int snd_vt1724_pro_rate_locking_put(struct snd_kcontrol *kcontrol,
  1741. struct snd_ctl_elem_value *ucontrol)
  1742. {
  1743. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1744. int change = 0, nval;
  1745. nval = ucontrol->value.integer.value[0] ? 1 : 0;
  1746. spin_lock_irq(&ice->reg_lock);
  1747. change = PRO_RATE_LOCKED != nval;
  1748. PRO_RATE_LOCKED = nval;
  1749. spin_unlock_irq(&ice->reg_lock);
  1750. return change;
  1751. }
  1752. static struct snd_kcontrol_new snd_vt1724_pro_rate_locking = {
  1753. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1754. .name = "Multi Track Rate Locking",
  1755. .info = snd_vt1724_pro_rate_locking_info,
  1756. .get = snd_vt1724_pro_rate_locking_get,
  1757. .put = snd_vt1724_pro_rate_locking_put
  1758. };
  1759. #define snd_vt1724_pro_rate_reset_info snd_ctl_boolean_mono_info
  1760. static int snd_vt1724_pro_rate_reset_get(struct snd_kcontrol *kcontrol,
  1761. struct snd_ctl_elem_value *ucontrol)
  1762. {
  1763. ucontrol->value.integer.value[0] = PRO_RATE_RESET ? 1 : 0;
  1764. return 0;
  1765. }
  1766. static int snd_vt1724_pro_rate_reset_put(struct snd_kcontrol *kcontrol,
  1767. struct snd_ctl_elem_value *ucontrol)
  1768. {
  1769. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1770. int change = 0, nval;
  1771. nval = ucontrol->value.integer.value[0] ? 1 : 0;
  1772. spin_lock_irq(&ice->reg_lock);
  1773. change = PRO_RATE_RESET != nval;
  1774. PRO_RATE_RESET = nval;
  1775. spin_unlock_irq(&ice->reg_lock);
  1776. return change;
  1777. }
  1778. static struct snd_kcontrol_new snd_vt1724_pro_rate_reset = {
  1779. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1780. .name = "Multi Track Rate Reset",
  1781. .info = snd_vt1724_pro_rate_reset_info,
  1782. .get = snd_vt1724_pro_rate_reset_get,
  1783. .put = snd_vt1724_pro_rate_reset_put
  1784. };
  1785. /*
  1786. * routing
  1787. */
  1788. static int snd_vt1724_pro_route_info(struct snd_kcontrol *kcontrol,
  1789. struct snd_ctl_elem_info *uinfo)
  1790. {
  1791. static const char * const texts[] = {
  1792. "PCM Out", /* 0 */
  1793. "H/W In 0", "H/W In 1", /* 1-2 */
  1794. "IEC958 In L", "IEC958 In R", /* 3-4 */
  1795. };
  1796. return snd_ctl_enum_info(uinfo, 1, 5, texts);
  1797. }
  1798. static inline int analog_route_shift(int idx)
  1799. {
  1800. return (idx % 2) * 12 + ((idx / 2) * 3) + 8;
  1801. }
  1802. static inline int digital_route_shift(int idx)
  1803. {
  1804. return idx * 3;
  1805. }
  1806. int snd_ice1724_get_route_val(struct snd_ice1712 *ice, int shift)
  1807. {
  1808. unsigned long val;
  1809. unsigned char eitem;
  1810. static const unsigned char xlate[8] = {
  1811. 0, 255, 1, 2, 255, 255, 3, 4,
  1812. };
  1813. val = inl(ICEMT1724(ice, ROUTE_PLAYBACK));
  1814. val >>= shift;
  1815. val &= 7; /* we now have 3 bits per output */
  1816. eitem = xlate[val];
  1817. if (eitem == 255) {
  1818. snd_BUG();
  1819. return 0;
  1820. }
  1821. return eitem;
  1822. }
  1823. int snd_ice1724_put_route_val(struct snd_ice1712 *ice, unsigned int val,
  1824. int shift)
  1825. {
  1826. unsigned int old_val, nval;
  1827. int change;
  1828. static const unsigned char xroute[8] = {
  1829. 0, /* PCM */
  1830. 2, /* PSDIN0 Left */
  1831. 3, /* PSDIN0 Right */
  1832. 6, /* SPDIN Left */
  1833. 7, /* SPDIN Right */
  1834. };
  1835. nval = xroute[val % 5];
  1836. val = old_val = inl(ICEMT1724(ice, ROUTE_PLAYBACK));
  1837. val &= ~(0x07 << shift);
  1838. val |= nval << shift;
  1839. change = val != old_val;
  1840. if (change)
  1841. outl(val, ICEMT1724(ice, ROUTE_PLAYBACK));
  1842. return change;
  1843. }
  1844. static int snd_vt1724_pro_route_analog_get(struct snd_kcontrol *kcontrol,
  1845. struct snd_ctl_elem_value *ucontrol)
  1846. {
  1847. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1848. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1849. ucontrol->value.enumerated.item[0] =
  1850. snd_ice1724_get_route_val(ice, analog_route_shift(idx));
  1851. return 0;
  1852. }
  1853. static int snd_vt1724_pro_route_analog_put(struct snd_kcontrol *kcontrol,
  1854. struct snd_ctl_elem_value *ucontrol)
  1855. {
  1856. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1857. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1858. return snd_ice1724_put_route_val(ice,
  1859. ucontrol->value.enumerated.item[0],
  1860. analog_route_shift(idx));
  1861. }
  1862. static int snd_vt1724_pro_route_spdif_get(struct snd_kcontrol *kcontrol,
  1863. struct snd_ctl_elem_value *ucontrol)
  1864. {
  1865. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1866. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1867. ucontrol->value.enumerated.item[0] =
  1868. snd_ice1724_get_route_val(ice, digital_route_shift(idx));
  1869. return 0;
  1870. }
  1871. static int snd_vt1724_pro_route_spdif_put(struct snd_kcontrol *kcontrol,
  1872. struct snd_ctl_elem_value *ucontrol)
  1873. {
  1874. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1875. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1876. return snd_ice1724_put_route_val(ice,
  1877. ucontrol->value.enumerated.item[0],
  1878. digital_route_shift(idx));
  1879. }
  1880. static struct snd_kcontrol_new snd_vt1724_mixer_pro_analog_route =
  1881. {
  1882. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1883. .name = "H/W Playback Route",
  1884. .info = snd_vt1724_pro_route_info,
  1885. .get = snd_vt1724_pro_route_analog_get,
  1886. .put = snd_vt1724_pro_route_analog_put,
  1887. };
  1888. static struct snd_kcontrol_new snd_vt1724_mixer_pro_spdif_route = {
  1889. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1890. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, NONE) "Route",
  1891. .info = snd_vt1724_pro_route_info,
  1892. .get = snd_vt1724_pro_route_spdif_get,
  1893. .put = snd_vt1724_pro_route_spdif_put,
  1894. .count = 2,
  1895. };
  1896. static int snd_vt1724_pro_peak_info(struct snd_kcontrol *kcontrol,
  1897. struct snd_ctl_elem_info *uinfo)
  1898. {
  1899. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1900. uinfo->count = 22; /* FIXME: for compatibility with ice1712... */
  1901. uinfo->value.integer.min = 0;
  1902. uinfo->value.integer.max = 255;
  1903. return 0;
  1904. }
  1905. static int snd_vt1724_pro_peak_get(struct snd_kcontrol *kcontrol,
  1906. struct snd_ctl_elem_value *ucontrol)
  1907. {
  1908. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1909. int idx;
  1910. spin_lock_irq(&ice->reg_lock);
  1911. for (idx = 0; idx < 22; idx++) {
  1912. outb(idx, ICEMT1724(ice, MONITOR_PEAKINDEX));
  1913. ucontrol->value.integer.value[idx] =
  1914. inb(ICEMT1724(ice, MONITOR_PEAKDATA));
  1915. }
  1916. spin_unlock_irq(&ice->reg_lock);
  1917. return 0;
  1918. }
  1919. static struct snd_kcontrol_new snd_vt1724_mixer_pro_peak = {
  1920. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1921. .name = "Multi Track Peak",
  1922. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  1923. .info = snd_vt1724_pro_peak_info,
  1924. .get = snd_vt1724_pro_peak_get
  1925. };
  1926. /*
  1927. *
  1928. */
  1929. static struct snd_ice1712_card_info no_matched;
  1930. /*
  1931. ooAoo cards with no controls
  1932. */
  1933. static unsigned char ooaoo_sq210_eeprom[] = {
  1934. [ICE_EEP2_SYSCONF] = 0x4c, /* 49MHz crystal, no mpu401, no ADC,
  1935. 1xDACs */
  1936. [ICE_EEP2_ACLINK] = 0x80, /* I2S */
  1937. [ICE_EEP2_I2S] = 0x78, /* no volume, 96k, 24bit, 192k */
  1938. [ICE_EEP2_SPDIF] = 0xc1, /* out-en, out-int, out-ext */
  1939. [ICE_EEP2_GPIO_DIR] = 0x00, /* no GPIOs are used */
  1940. [ICE_EEP2_GPIO_DIR1] = 0x00,
  1941. [ICE_EEP2_GPIO_DIR2] = 0x00,
  1942. [ICE_EEP2_GPIO_MASK] = 0xff,
  1943. [ICE_EEP2_GPIO_MASK1] = 0xff,
  1944. [ICE_EEP2_GPIO_MASK2] = 0xff,
  1945. [ICE_EEP2_GPIO_STATE] = 0x00, /* inputs */
  1946. [ICE_EEP2_GPIO_STATE1] = 0x00, /* all 1, but GPIO_CPLD_RW
  1947. and GPIO15 always zero */
  1948. [ICE_EEP2_GPIO_STATE2] = 0x00, /* inputs */
  1949. };
  1950. static struct snd_ice1712_card_info snd_vt1724_ooaoo_cards[] = {
  1951. {
  1952. .name = "ooAoo SQ210a",
  1953. .model = "sq210a",
  1954. .eeprom_size = sizeof(ooaoo_sq210_eeprom),
  1955. .eeprom_data = ooaoo_sq210_eeprom,
  1956. },
  1957. { } /* terminator */
  1958. };
  1959. static struct snd_ice1712_card_info *card_tables[] = {
  1960. snd_vt1724_revo_cards,
  1961. snd_vt1724_amp_cards,
  1962. snd_vt1724_aureon_cards,
  1963. snd_vt1720_mobo_cards,
  1964. snd_vt1720_pontis_cards,
  1965. snd_vt1724_prodigy_hifi_cards,
  1966. snd_vt1724_prodigy192_cards,
  1967. snd_vt1724_juli_cards,
  1968. snd_vt1724_maya44_cards,
  1969. snd_vt1724_phase_cards,
  1970. snd_vt1724_wtm_cards,
  1971. snd_vt1724_se_cards,
  1972. snd_vt1724_qtet_cards,
  1973. snd_vt1724_ooaoo_cards,
  1974. snd_vt1724_psc724_cards,
  1975. NULL,
  1976. };
  1977. /*
  1978. */
  1979. static void wait_i2c_busy(struct snd_ice1712 *ice)
  1980. {
  1981. int t = 0x10000;
  1982. while ((inb(ICEREG1724(ice, I2C_CTRL)) & VT1724_I2C_BUSY) && t--)
  1983. ;
  1984. if (t == -1)
  1985. dev_err(ice->card->dev, "i2c busy timeout\n");
  1986. }
  1987. unsigned char snd_vt1724_read_i2c(struct snd_ice1712 *ice,
  1988. unsigned char dev, unsigned char addr)
  1989. {
  1990. unsigned char val;
  1991. mutex_lock(&ice->i2c_mutex);
  1992. wait_i2c_busy(ice);
  1993. outb(addr, ICEREG1724(ice, I2C_BYTE_ADDR));
  1994. outb(dev & ~VT1724_I2C_WRITE, ICEREG1724(ice, I2C_DEV_ADDR));
  1995. wait_i2c_busy(ice);
  1996. val = inb(ICEREG1724(ice, I2C_DATA));
  1997. mutex_unlock(&ice->i2c_mutex);
  1998. /*
  1999. dev_dbg(ice->card->dev, "i2c_read: [0x%x,0x%x] = 0x%x\n", dev, addr, val);
  2000. */
  2001. return val;
  2002. }
  2003. void snd_vt1724_write_i2c(struct snd_ice1712 *ice,
  2004. unsigned char dev, unsigned char addr, unsigned char data)
  2005. {
  2006. mutex_lock(&ice->i2c_mutex);
  2007. wait_i2c_busy(ice);
  2008. /*
  2009. dev_dbg(ice->card->dev, "i2c_write: [0x%x,0x%x] = 0x%x\n", dev, addr, data);
  2010. */
  2011. outb(addr, ICEREG1724(ice, I2C_BYTE_ADDR));
  2012. outb(data, ICEREG1724(ice, I2C_DATA));
  2013. outb(dev | VT1724_I2C_WRITE, ICEREG1724(ice, I2C_DEV_ADDR));
  2014. wait_i2c_busy(ice);
  2015. mutex_unlock(&ice->i2c_mutex);
  2016. }
  2017. static int snd_vt1724_read_eeprom(struct snd_ice1712 *ice,
  2018. const char *modelname)
  2019. {
  2020. const int dev = 0xa0; /* EEPROM device address */
  2021. unsigned int i, size;
  2022. struct snd_ice1712_card_info * const *tbl, *c;
  2023. if (!modelname || !*modelname) {
  2024. ice->eeprom.subvendor = 0;
  2025. if ((inb(ICEREG1724(ice, I2C_CTRL)) & VT1724_I2C_EEPROM) != 0)
  2026. ice->eeprom.subvendor =
  2027. (snd_vt1724_read_i2c(ice, dev, 0x00) << 0) |
  2028. (snd_vt1724_read_i2c(ice, dev, 0x01) << 8) |
  2029. (snd_vt1724_read_i2c(ice, dev, 0x02) << 16) |
  2030. (snd_vt1724_read_i2c(ice, dev, 0x03) << 24);
  2031. if (ice->eeprom.subvendor == 0 ||
  2032. ice->eeprom.subvendor == (unsigned int)-1) {
  2033. /* invalid subvendor from EEPROM, try the PCI
  2034. * subststem ID instead
  2035. */
  2036. u16 vendor, device;
  2037. pci_read_config_word(ice->pci, PCI_SUBSYSTEM_VENDOR_ID,
  2038. &vendor);
  2039. pci_read_config_word(ice->pci, PCI_SUBSYSTEM_ID, &device);
  2040. ice->eeprom.subvendor =
  2041. ((unsigned int)swab16(vendor) << 16) | swab16(device);
  2042. if (ice->eeprom.subvendor == 0 ||
  2043. ice->eeprom.subvendor == (unsigned int)-1) {
  2044. dev_err(ice->card->dev,
  2045. "No valid ID is found\n");
  2046. return -ENXIO;
  2047. }
  2048. }
  2049. }
  2050. for (tbl = card_tables; *tbl; tbl++) {
  2051. for (c = *tbl; c->name; c++) {
  2052. if (modelname && c->model &&
  2053. !strcmp(modelname, c->model)) {
  2054. dev_info(ice->card->dev,
  2055. "Using board model %s\n",
  2056. c->name);
  2057. ice->eeprom.subvendor = c->subvendor;
  2058. } else if (c->subvendor != ice->eeprom.subvendor)
  2059. continue;
  2060. ice->card_info = c;
  2061. if (!c->eeprom_size || !c->eeprom_data)
  2062. goto found;
  2063. /* if the EEPROM is given by the driver, use it */
  2064. dev_dbg(ice->card->dev, "using the defined eeprom..\n");
  2065. ice->eeprom.version = 2;
  2066. ice->eeprom.size = c->eeprom_size + 6;
  2067. memcpy(ice->eeprom.data, c->eeprom_data, c->eeprom_size);
  2068. goto read_skipped;
  2069. }
  2070. }
  2071. dev_warn(ice->card->dev, "No matching model found for ID 0x%x\n",
  2072. ice->eeprom.subvendor);
  2073. #ifdef CONFIG_PM_SLEEP
  2074. /* assume AC97-only card which can suspend without additional code */
  2075. ice->pm_suspend_enabled = 1;
  2076. #endif
  2077. found:
  2078. ice->eeprom.size = snd_vt1724_read_i2c(ice, dev, 0x04);
  2079. if (ice->eeprom.size < 6)
  2080. ice->eeprom.size = 32;
  2081. else if (ice->eeprom.size > 32) {
  2082. dev_err(ice->card->dev, "Invalid EEPROM (size = %i)\n",
  2083. ice->eeprom.size);
  2084. return -EIO;
  2085. }
  2086. ice->eeprom.version = snd_vt1724_read_i2c(ice, dev, 0x05);
  2087. if (ice->eeprom.version != 1 && ice->eeprom.version != 2)
  2088. dev_warn(ice->card->dev, "Invalid EEPROM version %i\n",
  2089. ice->eeprom.version);
  2090. size = ice->eeprom.size - 6;
  2091. for (i = 0; i < size; i++)
  2092. ice->eeprom.data[i] = snd_vt1724_read_i2c(ice, dev, i + 6);
  2093. read_skipped:
  2094. ice->eeprom.gpiomask = eeprom_triple(ice, ICE_EEP2_GPIO_MASK);
  2095. ice->eeprom.gpiostate = eeprom_triple(ice, ICE_EEP2_GPIO_STATE);
  2096. ice->eeprom.gpiodir = eeprom_triple(ice, ICE_EEP2_GPIO_DIR);
  2097. return 0;
  2098. }
  2099. static void snd_vt1724_chip_reset(struct snd_ice1712 *ice)
  2100. {
  2101. outb(VT1724_RESET , ICEREG1724(ice, CONTROL));
  2102. inb(ICEREG1724(ice, CONTROL)); /* pci posting flush */
  2103. msleep(10);
  2104. outb(0, ICEREG1724(ice, CONTROL));
  2105. inb(ICEREG1724(ice, CONTROL)); /* pci posting flush */
  2106. msleep(10);
  2107. }
  2108. static int snd_vt1724_chip_init(struct snd_ice1712 *ice)
  2109. {
  2110. outb(ice->eeprom.data[ICE_EEP2_SYSCONF], ICEREG1724(ice, SYS_CFG));
  2111. outb(ice->eeprom.data[ICE_EEP2_ACLINK], ICEREG1724(ice, AC97_CFG));
  2112. outb(ice->eeprom.data[ICE_EEP2_I2S], ICEREG1724(ice, I2S_FEATURES));
  2113. outb(ice->eeprom.data[ICE_EEP2_SPDIF], ICEREG1724(ice, SPDIF_CFG));
  2114. ice->gpio.write_mask = ice->eeprom.gpiomask;
  2115. ice->gpio.direction = ice->eeprom.gpiodir;
  2116. snd_vt1724_set_gpio_mask(ice, ice->eeprom.gpiomask);
  2117. snd_vt1724_set_gpio_dir(ice, ice->eeprom.gpiodir);
  2118. snd_vt1724_set_gpio_data(ice, ice->eeprom.gpiostate);
  2119. outb(0, ICEREG1724(ice, POWERDOWN));
  2120. /* MPU_RX and TX irq masks are cleared later dynamically */
  2121. outb(VT1724_IRQ_MPU_RX | VT1724_IRQ_MPU_TX , ICEREG1724(ice, IRQMASK));
  2122. /* don't handle FIFO overrun/underruns (just yet),
  2123. * since they cause machine lockups
  2124. */
  2125. outb(VT1724_MULTI_FIFO_ERR, ICEMT1724(ice, DMA_INT_MASK));
  2126. return 0;
  2127. }
  2128. static int snd_vt1724_spdif_build_controls(struct snd_ice1712 *ice)
  2129. {
  2130. int err;
  2131. struct snd_kcontrol *kctl;
  2132. if (snd_BUG_ON(!ice->pcm))
  2133. return -EIO;
  2134. if (!ice->own_routing) {
  2135. err = snd_ctl_add(ice->card,
  2136. snd_ctl_new1(&snd_vt1724_mixer_pro_spdif_route, ice));
  2137. if (err < 0)
  2138. return err;
  2139. }
  2140. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_spdif_switch, ice));
  2141. if (err < 0)
  2142. return err;
  2143. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_vt1724_spdif_default, ice));
  2144. if (err < 0)
  2145. return err;
  2146. kctl->id.device = ice->pcm->device;
  2147. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_vt1724_spdif_maskc, ice));
  2148. if (err < 0)
  2149. return err;
  2150. kctl->id.device = ice->pcm->device;
  2151. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_vt1724_spdif_maskp, ice));
  2152. if (err < 0)
  2153. return err;
  2154. kctl->id.device = ice->pcm->device;
  2155. #if 0 /* use default only */
  2156. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_vt1724_spdif_stream, ice));
  2157. if (err < 0)
  2158. return err;
  2159. kctl->id.device = ice->pcm->device;
  2160. ice->spdif.stream_ctl = kctl;
  2161. #endif
  2162. return 0;
  2163. }
  2164. static int snd_vt1724_build_controls(struct snd_ice1712 *ice)
  2165. {
  2166. int err;
  2167. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_eeprom, ice));
  2168. if (err < 0)
  2169. return err;
  2170. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_pro_internal_clock, ice));
  2171. if (err < 0)
  2172. return err;
  2173. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_pro_rate_locking, ice));
  2174. if (err < 0)
  2175. return err;
  2176. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_vt1724_pro_rate_reset, ice));
  2177. if (err < 0)
  2178. return err;
  2179. if (!ice->own_routing && ice->num_total_dacs > 0) {
  2180. struct snd_kcontrol_new tmp = snd_vt1724_mixer_pro_analog_route;
  2181. tmp.count = ice->num_total_dacs;
  2182. if (ice->vt1720 && tmp.count > 2)
  2183. tmp.count = 2;
  2184. err = snd_ctl_add(ice->card, snd_ctl_new1(&tmp, ice));
  2185. if (err < 0)
  2186. return err;
  2187. }
  2188. return snd_ctl_add(ice->card,
  2189. snd_ctl_new1(&snd_vt1724_mixer_pro_peak, ice));
  2190. }
  2191. static int snd_vt1724_free(struct snd_ice1712 *ice)
  2192. {
  2193. if (!ice->port)
  2194. goto __hw_end;
  2195. /* mask all interrupts */
  2196. outb(0xff, ICEMT1724(ice, DMA_INT_MASK));
  2197. outb(0xff, ICEREG1724(ice, IRQMASK));
  2198. /* --- */
  2199. __hw_end:
  2200. if (ice->irq >= 0)
  2201. free_irq(ice->irq, ice);
  2202. pci_release_regions(ice->pci);
  2203. snd_ice1712_akm4xxx_free(ice);
  2204. pci_disable_device(ice->pci);
  2205. kfree(ice->spec);
  2206. kfree(ice);
  2207. return 0;
  2208. }
  2209. static int snd_vt1724_dev_free(struct snd_device *device)
  2210. {
  2211. struct snd_ice1712 *ice = device->device_data;
  2212. return snd_vt1724_free(ice);
  2213. }
  2214. static int snd_vt1724_create(struct snd_card *card,
  2215. struct pci_dev *pci,
  2216. const char *modelname,
  2217. struct snd_ice1712 **r_ice1712)
  2218. {
  2219. struct snd_ice1712 *ice;
  2220. int err;
  2221. static struct snd_device_ops ops = {
  2222. .dev_free = snd_vt1724_dev_free,
  2223. };
  2224. *r_ice1712 = NULL;
  2225. /* enable PCI device */
  2226. err = pci_enable_device(pci);
  2227. if (err < 0)
  2228. return err;
  2229. ice = kzalloc(sizeof(*ice), GFP_KERNEL);
  2230. if (ice == NULL) {
  2231. pci_disable_device(pci);
  2232. return -ENOMEM;
  2233. }
  2234. ice->vt1724 = 1;
  2235. spin_lock_init(&ice->reg_lock);
  2236. mutex_init(&ice->gpio_mutex);
  2237. mutex_init(&ice->open_mutex);
  2238. mutex_init(&ice->i2c_mutex);
  2239. ice->gpio.set_mask = snd_vt1724_set_gpio_mask;
  2240. ice->gpio.get_mask = snd_vt1724_get_gpio_mask;
  2241. ice->gpio.set_dir = snd_vt1724_set_gpio_dir;
  2242. ice->gpio.get_dir = snd_vt1724_get_gpio_dir;
  2243. ice->gpio.set_data = snd_vt1724_set_gpio_data;
  2244. ice->gpio.get_data = snd_vt1724_get_gpio_data;
  2245. ice->card = card;
  2246. ice->pci = pci;
  2247. ice->irq = -1;
  2248. pci_set_master(pci);
  2249. snd_vt1724_proc_init(ice);
  2250. synchronize_irq(pci->irq);
  2251. card->private_data = ice;
  2252. err = pci_request_regions(pci, "ICE1724");
  2253. if (err < 0) {
  2254. kfree(ice);
  2255. pci_disable_device(pci);
  2256. return err;
  2257. }
  2258. ice->port = pci_resource_start(pci, 0);
  2259. ice->profi_port = pci_resource_start(pci, 1);
  2260. if (request_irq(pci->irq, snd_vt1724_interrupt,
  2261. IRQF_SHARED, KBUILD_MODNAME, ice)) {
  2262. dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
  2263. snd_vt1724_free(ice);
  2264. return -EIO;
  2265. }
  2266. ice->irq = pci->irq;
  2267. snd_vt1724_chip_reset(ice);
  2268. if (snd_vt1724_read_eeprom(ice, modelname) < 0) {
  2269. snd_vt1724_free(ice);
  2270. return -EIO;
  2271. }
  2272. if (snd_vt1724_chip_init(ice) < 0) {
  2273. snd_vt1724_free(ice);
  2274. return -EIO;
  2275. }
  2276. err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ice, &ops);
  2277. if (err < 0) {
  2278. snd_vt1724_free(ice);
  2279. return err;
  2280. }
  2281. *r_ice1712 = ice;
  2282. return 0;
  2283. }
  2284. /*
  2285. *
  2286. * Registration
  2287. *
  2288. */
  2289. static int snd_vt1724_probe(struct pci_dev *pci,
  2290. const struct pci_device_id *pci_id)
  2291. {
  2292. static int dev;
  2293. struct snd_card *card;
  2294. struct snd_ice1712 *ice;
  2295. int pcm_dev = 0, err;
  2296. struct snd_ice1712_card_info * const *tbl, *c;
  2297. if (dev >= SNDRV_CARDS)
  2298. return -ENODEV;
  2299. if (!enable[dev]) {
  2300. dev++;
  2301. return -ENOENT;
  2302. }
  2303. err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
  2304. 0, &card);
  2305. if (err < 0)
  2306. return err;
  2307. strcpy(card->driver, "ICE1724");
  2308. strcpy(card->shortname, "ICEnsemble ICE1724");
  2309. err = snd_vt1724_create(card, pci, model[dev], &ice);
  2310. if (err < 0) {
  2311. snd_card_free(card);
  2312. return err;
  2313. }
  2314. /* field init before calling chip_init */
  2315. ice->ext_clock_count = 0;
  2316. for (tbl = card_tables; *tbl; tbl++) {
  2317. for (c = *tbl; c->name; c++) {
  2318. if ((model[dev] && c->model &&
  2319. !strcmp(model[dev], c->model)) ||
  2320. (c->subvendor == ice->eeprom.subvendor)) {
  2321. strcpy(card->shortname, c->name);
  2322. if (c->driver) /* specific driver? */
  2323. strcpy(card->driver, c->driver);
  2324. if (c->chip_init) {
  2325. err = c->chip_init(ice);
  2326. if (err < 0) {
  2327. snd_card_free(card);
  2328. return err;
  2329. }
  2330. }
  2331. goto __found;
  2332. }
  2333. }
  2334. }
  2335. c = &no_matched;
  2336. __found:
  2337. /*
  2338. * VT1724 has separate DMAs for the analog and the SPDIF streams while
  2339. * ICE1712 has only one for both (mixed up).
  2340. *
  2341. * Confusingly the analog PCM is named "professional" here because it
  2342. * was called so in ice1712 driver, and vt1724 driver is derived from
  2343. * ice1712 driver.
  2344. */
  2345. ice->pro_rate_default = PRO_RATE_DEFAULT;
  2346. if (!ice->is_spdif_master)
  2347. ice->is_spdif_master = stdclock_is_spdif_master;
  2348. if (!ice->get_rate)
  2349. ice->get_rate = stdclock_get_rate;
  2350. if (!ice->set_rate)
  2351. ice->set_rate = stdclock_set_rate;
  2352. if (!ice->set_mclk)
  2353. ice->set_mclk = stdclock_set_mclk;
  2354. if (!ice->set_spdif_clock)
  2355. ice->set_spdif_clock = stdclock_set_spdif_clock;
  2356. if (!ice->get_spdif_master_type)
  2357. ice->get_spdif_master_type = stdclock_get_spdif_master_type;
  2358. if (!ice->ext_clock_names)
  2359. ice->ext_clock_names = ext_clock_names;
  2360. if (!ice->ext_clock_count)
  2361. ice->ext_clock_count = ARRAY_SIZE(ext_clock_names);
  2362. if (!ice->hw_rates)
  2363. set_std_hw_rates(ice);
  2364. err = snd_vt1724_pcm_profi(ice, pcm_dev++);
  2365. if (err < 0) {
  2366. snd_card_free(card);
  2367. return err;
  2368. }
  2369. err = snd_vt1724_pcm_spdif(ice, pcm_dev++);
  2370. if (err < 0) {
  2371. snd_card_free(card);
  2372. return err;
  2373. }
  2374. err = snd_vt1724_pcm_indep(ice, pcm_dev++);
  2375. if (err < 0) {
  2376. snd_card_free(card);
  2377. return err;
  2378. }
  2379. err = snd_vt1724_ac97_mixer(ice);
  2380. if (err < 0) {
  2381. snd_card_free(card);
  2382. return err;
  2383. }
  2384. err = snd_vt1724_build_controls(ice);
  2385. if (err < 0) {
  2386. snd_card_free(card);
  2387. return err;
  2388. }
  2389. if (ice->pcm && ice->has_spdif) { /* has SPDIF I/O */
  2390. err = snd_vt1724_spdif_build_controls(ice);
  2391. if (err < 0) {
  2392. snd_card_free(card);
  2393. return err;
  2394. }
  2395. }
  2396. if (c->build_controls) {
  2397. err = c->build_controls(ice);
  2398. if (err < 0) {
  2399. snd_card_free(card);
  2400. return err;
  2401. }
  2402. }
  2403. if (!c->no_mpu401) {
  2404. if (ice->eeprom.data[ICE_EEP2_SYSCONF] & VT1724_CFG_MPU401) {
  2405. struct snd_rawmidi *rmidi;
  2406. err = snd_rawmidi_new(card, "MIDI", 0, 1, 1, &rmidi);
  2407. if (err < 0) {
  2408. snd_card_free(card);
  2409. return err;
  2410. }
  2411. ice->rmidi[0] = rmidi;
  2412. rmidi->private_data = ice;
  2413. strcpy(rmidi->name, "ICE1724 MIDI");
  2414. rmidi->info_flags = SNDRV_RAWMIDI_INFO_OUTPUT |
  2415. SNDRV_RAWMIDI_INFO_INPUT |
  2416. SNDRV_RAWMIDI_INFO_DUPLEX;
  2417. snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT,
  2418. &vt1724_midi_output_ops);
  2419. snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT,
  2420. &vt1724_midi_input_ops);
  2421. /* set watermarks */
  2422. outb(VT1724_MPU_RX_FIFO | 0x1,
  2423. ICEREG1724(ice, MPU_FIFO_WM));
  2424. outb(0x1, ICEREG1724(ice, MPU_FIFO_WM));
  2425. /* set UART mode */
  2426. outb(VT1724_MPU_UART, ICEREG1724(ice, MPU_CTRL));
  2427. }
  2428. }
  2429. sprintf(card->longname, "%s at 0x%lx, irq %i",
  2430. card->shortname, ice->port, ice->irq);
  2431. err = snd_card_register(card);
  2432. if (err < 0) {
  2433. snd_card_free(card);
  2434. return err;
  2435. }
  2436. pci_set_drvdata(pci, card);
  2437. dev++;
  2438. return 0;
  2439. }
  2440. static void snd_vt1724_remove(struct pci_dev *pci)
  2441. {
  2442. struct snd_card *card = pci_get_drvdata(pci);
  2443. struct snd_ice1712 *ice = card->private_data;
  2444. if (ice->card_info && ice->card_info->chip_exit)
  2445. ice->card_info->chip_exit(ice);
  2446. snd_card_free(card);
  2447. }
  2448. #ifdef CONFIG_PM_SLEEP
  2449. static int snd_vt1724_suspend(struct device *dev)
  2450. {
  2451. struct snd_card *card = dev_get_drvdata(dev);
  2452. struct snd_ice1712 *ice = card->private_data;
  2453. if (!ice->pm_suspend_enabled)
  2454. return 0;
  2455. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  2456. snd_pcm_suspend_all(ice->pcm);
  2457. snd_pcm_suspend_all(ice->pcm_pro);
  2458. snd_pcm_suspend_all(ice->pcm_ds);
  2459. snd_ac97_suspend(ice->ac97);
  2460. spin_lock_irq(&ice->reg_lock);
  2461. ice->pm_saved_is_spdif_master = ice->is_spdif_master(ice);
  2462. ice->pm_saved_spdif_ctrl = inw(ICEMT1724(ice, SPDIF_CTRL));
  2463. ice->pm_saved_spdif_cfg = inb(ICEREG1724(ice, SPDIF_CFG));
  2464. ice->pm_saved_route = inl(ICEMT1724(ice, ROUTE_PLAYBACK));
  2465. spin_unlock_irq(&ice->reg_lock);
  2466. if (ice->pm_suspend)
  2467. ice->pm_suspend(ice);
  2468. return 0;
  2469. }
  2470. static int snd_vt1724_resume(struct device *dev)
  2471. {
  2472. struct snd_card *card = dev_get_drvdata(dev);
  2473. struct snd_ice1712 *ice = card->private_data;
  2474. if (!ice->pm_suspend_enabled)
  2475. return 0;
  2476. snd_vt1724_chip_reset(ice);
  2477. if (snd_vt1724_chip_init(ice) < 0) {
  2478. snd_card_disconnect(card);
  2479. return -EIO;
  2480. }
  2481. if (ice->pm_resume)
  2482. ice->pm_resume(ice);
  2483. if (ice->pm_saved_is_spdif_master) {
  2484. /* switching to external clock via SPDIF */
  2485. ice->set_spdif_clock(ice, 0);
  2486. } else {
  2487. /* internal on-card clock */
  2488. int rate;
  2489. if (ice->cur_rate)
  2490. rate = ice->cur_rate;
  2491. else
  2492. rate = ice->pro_rate_default;
  2493. snd_vt1724_set_pro_rate(ice, rate, 1);
  2494. }
  2495. update_spdif_bits(ice, ice->pm_saved_spdif_ctrl);
  2496. outb(ice->pm_saved_spdif_cfg, ICEREG1724(ice, SPDIF_CFG));
  2497. outl(ice->pm_saved_route, ICEMT1724(ice, ROUTE_PLAYBACK));
  2498. snd_ac97_resume(ice->ac97);
  2499. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  2500. return 0;
  2501. }
  2502. static SIMPLE_DEV_PM_OPS(snd_vt1724_pm, snd_vt1724_suspend, snd_vt1724_resume);
  2503. #define SND_VT1724_PM_OPS &snd_vt1724_pm
  2504. #else
  2505. #define SND_VT1724_PM_OPS NULL
  2506. #endif /* CONFIG_PM_SLEEP */
  2507. static struct pci_driver vt1724_driver = {
  2508. .name = KBUILD_MODNAME,
  2509. .id_table = snd_vt1724_ids,
  2510. .probe = snd_vt1724_probe,
  2511. .remove = snd_vt1724_remove,
  2512. .driver = {
  2513. .pm = SND_VT1724_PM_OPS,
  2514. },
  2515. };
  2516. module_pci_driver(vt1724_driver);