intel8x0.c 92 KB

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  1. /*
  2. * ALSA driver for Intel ICH (i8x0) chipsets
  3. *
  4. * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
  5. *
  6. *
  7. * This code also contains alpha support for SiS 735 chipsets provided
  8. * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
  9. * for SiS735, so the code is not fully functional.
  10. *
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License as published by
  14. * the Free Software Foundation; either version 2 of the License, or
  15. * (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  25. *
  26. */
  27. #include <linux/io.h>
  28. #include <linux/delay.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/init.h>
  31. #include <linux/pci.h>
  32. #include <linux/slab.h>
  33. #include <linux/module.h>
  34. #include <sound/core.h>
  35. #include <sound/pcm.h>
  36. #include <sound/ac97_codec.h>
  37. #include <sound/info.h>
  38. #include <sound/initval.h>
  39. /* for 440MX workaround */
  40. #include <asm/pgtable.h>
  41. #include <asm/cacheflush.h>
  42. #ifdef CONFIG_KVM_GUEST
  43. #include <linux/kvm_para.h>
  44. #else
  45. #define kvm_para_available() (0)
  46. #endif
  47. MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
  48. MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
  49. MODULE_LICENSE("GPL");
  50. MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
  51. "{Intel,82901AB-ICH0},"
  52. "{Intel,82801BA-ICH2},"
  53. "{Intel,82801CA-ICH3},"
  54. "{Intel,82801DB-ICH4},"
  55. "{Intel,ICH5},"
  56. "{Intel,ICH6},"
  57. "{Intel,ICH7},"
  58. "{Intel,6300ESB},"
  59. "{Intel,ESB2},"
  60. "{Intel,MX440},"
  61. "{SiS,SI7012},"
  62. "{NVidia,nForce Audio},"
  63. "{NVidia,nForce2 Audio},"
  64. "{NVidia,nForce3 Audio},"
  65. "{NVidia,MCP04},"
  66. "{NVidia,MCP501},"
  67. "{NVidia,CK804},"
  68. "{NVidia,CK8},"
  69. "{NVidia,CK8S},"
  70. "{AMD,AMD768},"
  71. "{AMD,AMD8111},"
  72. "{ALI,M5455}}");
  73. static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */
  74. static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
  75. static int ac97_clock;
  76. static char *ac97_quirk;
  77. static bool buggy_semaphore;
  78. static int buggy_irq = -1; /* auto-check */
  79. static bool xbox;
  80. static int spdif_aclink = -1;
  81. static int inside_vm = -1;
  82. module_param(index, int, 0444);
  83. MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
  84. module_param(id, charp, 0444);
  85. MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
  86. module_param(ac97_clock, int, 0444);
  87. MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = whitelist + auto-detect, 1 = force autodetect).");
  88. module_param(ac97_quirk, charp, 0444);
  89. MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
  90. module_param(buggy_semaphore, bool, 0444);
  91. MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
  92. module_param(buggy_irq, bint, 0444);
  93. MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
  94. module_param(xbox, bool, 0444);
  95. MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
  96. module_param(spdif_aclink, int, 0444);
  97. MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
  98. module_param(inside_vm, bint, 0444);
  99. MODULE_PARM_DESC(inside_vm, "KVM/Parallels optimization.");
  100. /* just for backward compatibility */
  101. static bool enable;
  102. module_param(enable, bool, 0444);
  103. static int joystick;
  104. module_param(joystick, int, 0444);
  105. /*
  106. * Direct registers
  107. */
  108. enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
  109. #define ICHREG(x) ICH_REG_##x
  110. #define DEFINE_REGSET(name,base) \
  111. enum { \
  112. ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \
  113. ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \
  114. ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \
  115. ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \
  116. ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \
  117. ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \
  118. ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \
  119. };
  120. /* busmaster blocks */
  121. DEFINE_REGSET(OFF, 0); /* offset */
  122. DEFINE_REGSET(PI, 0x00); /* PCM in */
  123. DEFINE_REGSET(PO, 0x10); /* PCM out */
  124. DEFINE_REGSET(MC, 0x20); /* Mic in */
  125. /* ICH4 busmaster blocks */
  126. DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */
  127. DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */
  128. DEFINE_REGSET(SP, 0x60); /* SPDIF out */
  129. /* values for each busmaster block */
  130. /* LVI */
  131. #define ICH_REG_LVI_MASK 0x1f
  132. /* SR */
  133. #define ICH_FIFOE 0x10 /* FIFO error */
  134. #define ICH_BCIS 0x08 /* buffer completion interrupt status */
  135. #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */
  136. #define ICH_CELV 0x02 /* current equals last valid */
  137. #define ICH_DCH 0x01 /* DMA controller halted */
  138. /* PIV */
  139. #define ICH_REG_PIV_MASK 0x1f /* mask */
  140. /* CR */
  141. #define ICH_IOCE 0x10 /* interrupt on completion enable */
  142. #define ICH_FEIE 0x08 /* fifo error interrupt enable */
  143. #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */
  144. #define ICH_RESETREGS 0x02 /* reset busmaster registers */
  145. #define ICH_STARTBM 0x01 /* start busmaster operation */
  146. /* global block */
  147. #define ICH_REG_GLOB_CNT 0x2c /* dword - global control */
  148. #define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */
  149. #define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */
  150. #define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */
  151. #define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */
  152. #define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */
  153. #define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */
  154. #define ICH_PCM_246_MASK 0x00300000 /* chan mask (not all chips) */
  155. #define ICH_PCM_8 0x00300000 /* 8 channels (not all chips) */
  156. #define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */
  157. #define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */
  158. #define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */
  159. #define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */
  160. #define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */
  161. #define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */
  162. #define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */
  163. #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */
  164. #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */
  165. #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */
  166. #define ICH_ACLINK 0x00000008 /* AClink shut off */
  167. #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */
  168. #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */
  169. #define ICH_GIE 0x00000001 /* GPI interrupt enable */
  170. #define ICH_REG_GLOB_STA 0x30 /* dword - global status */
  171. #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */
  172. #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */
  173. #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */
  174. #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */
  175. #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */
  176. #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */
  177. #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */
  178. #define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */
  179. #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */
  180. #define ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */
  181. #define ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */
  182. #define ICH_MD3 0x00020000 /* modem power down semaphore */
  183. #define ICH_AD3 0x00010000 /* audio power down semaphore */
  184. #define ICH_RCS 0x00008000 /* read completion status */
  185. #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */
  186. #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */
  187. #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */
  188. #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */
  189. #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */
  190. #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */
  191. #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */
  192. #define ICH_MCINT 0x00000080 /* MIC capture interrupt */
  193. #define ICH_POINT 0x00000040 /* playback interrupt */
  194. #define ICH_PIINT 0x00000020 /* capture interrupt */
  195. #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */
  196. #define ICH_MOINT 0x00000004 /* modem playback interrupt */
  197. #define ICH_MIINT 0x00000002 /* modem capture interrupt */
  198. #define ICH_GSCI 0x00000001 /* GPI status change interrupt */
  199. #define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */
  200. #define ICH_CAS 0x01 /* codec access semaphore */
  201. #define ICH_REG_SDM 0x80
  202. #define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */
  203. #define ICH_DI2L_SHIFT 6
  204. #define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */
  205. #define ICH_DI1L_SHIFT 4
  206. #define ICH_SE 0x00000008 /* steer enable */
  207. #define ICH_LDI_MASK 0x00000003 /* last codec read data input */
  208. #define ICH_MAX_FRAGS 32 /* max hw frags */
  209. /*
  210. * registers for Ali5455
  211. */
  212. /* ALi 5455 busmaster blocks */
  213. DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */
  214. DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */
  215. DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */
  216. DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */
  217. DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */
  218. DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */
  219. DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */
  220. DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */
  221. DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */
  222. DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */
  223. DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */
  224. enum {
  225. ICH_REG_ALI_SCR = 0x00, /* System Control Register */
  226. ICH_REG_ALI_SSR = 0x04, /* System Status Register */
  227. ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */
  228. ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */
  229. ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */
  230. ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */
  231. ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */
  232. ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */
  233. ICH_REG_ALI_CPR = 0x20, /* Command Port Register */
  234. ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */
  235. ICH_REG_ALI_SPR = 0x24, /* Status Port Register */
  236. ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */
  237. ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */
  238. ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */
  239. ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */
  240. ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */
  241. ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */
  242. ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */
  243. ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */
  244. ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */
  245. ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */
  246. };
  247. #define ALI_CAS_SEM_BUSY 0x80000000
  248. #define ALI_CPR_ADDR_SECONDARY 0x100
  249. #define ALI_CPR_ADDR_READ 0x80
  250. #define ALI_CSPSR_CODEC_READY 0x08
  251. #define ALI_CSPSR_READ_OK 0x02
  252. #define ALI_CSPSR_WRITE_OK 0x01
  253. /* interrupts for the whole chip by interrupt status register finish */
  254. #define ALI_INT_MICIN2 (1<<26)
  255. #define ALI_INT_PCMIN2 (1<<25)
  256. #define ALI_INT_I2SIN (1<<24)
  257. #define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */
  258. #define ALI_INT_SPDIFIN (1<<22)
  259. #define ALI_INT_LFEOUT (1<<21)
  260. #define ALI_INT_CENTEROUT (1<<20)
  261. #define ALI_INT_CODECSPDIFOUT (1<<19)
  262. #define ALI_INT_MICIN (1<<18)
  263. #define ALI_INT_PCMOUT (1<<17)
  264. #define ALI_INT_PCMIN (1<<16)
  265. #define ALI_INT_CPRAIS (1<<7) /* command port available */
  266. #define ALI_INT_SPRAIS (1<<5) /* status port available */
  267. #define ALI_INT_GPIO (1<<1)
  268. #define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
  269. ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
  270. #define ICH_ALI_SC_RESET (1<<31) /* master reset */
  271. #define ICH_ALI_SC_AC97_DBL (1<<30)
  272. #define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */
  273. #define ICH_ALI_SC_IN_BITS (3<<18)
  274. #define ICH_ALI_SC_OUT_BITS (3<<16)
  275. #define ICH_ALI_SC_6CH_CFG (3<<14)
  276. #define ICH_ALI_SC_PCM_4 (1<<8)
  277. #define ICH_ALI_SC_PCM_6 (2<<8)
  278. #define ICH_ALI_SC_PCM_246_MASK (3<<8)
  279. #define ICH_ALI_SS_SEC_ID (3<<5)
  280. #define ICH_ALI_SS_PRI_ID (3<<3)
  281. #define ICH_ALI_IF_AC97SP (1<<21)
  282. #define ICH_ALI_IF_MC (1<<20)
  283. #define ICH_ALI_IF_PI (1<<19)
  284. #define ICH_ALI_IF_MC2 (1<<18)
  285. #define ICH_ALI_IF_PI2 (1<<17)
  286. #define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */
  287. #define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */
  288. #define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
  289. #define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */
  290. #define ICH_ALI_IF_PO_SPDF (1<<3)
  291. #define ICH_ALI_IF_PO (1<<1)
  292. /*
  293. *
  294. */
  295. enum {
  296. ICHD_PCMIN,
  297. ICHD_PCMOUT,
  298. ICHD_MIC,
  299. ICHD_MIC2,
  300. ICHD_PCM2IN,
  301. ICHD_SPBAR,
  302. ICHD_LAST = ICHD_SPBAR
  303. };
  304. enum {
  305. NVD_PCMIN,
  306. NVD_PCMOUT,
  307. NVD_MIC,
  308. NVD_SPBAR,
  309. NVD_LAST = NVD_SPBAR
  310. };
  311. enum {
  312. ALID_PCMIN,
  313. ALID_PCMOUT,
  314. ALID_MIC,
  315. ALID_AC97SPDIFOUT,
  316. ALID_SPDIFIN,
  317. ALID_SPDIFOUT,
  318. ALID_LAST = ALID_SPDIFOUT
  319. };
  320. #define get_ichdev(substream) (substream->runtime->private_data)
  321. struct ichdev {
  322. unsigned int ichd; /* ich device number */
  323. unsigned long reg_offset; /* offset to bmaddr */
  324. u32 *bdbar; /* CPU address (32bit) */
  325. unsigned int bdbar_addr; /* PCI bus address (32bit) */
  326. struct snd_pcm_substream *substream;
  327. unsigned int physbuf; /* physical address (32bit) */
  328. unsigned int size;
  329. unsigned int fragsize;
  330. unsigned int fragsize1;
  331. unsigned int position;
  332. unsigned int pos_shift;
  333. unsigned int last_pos;
  334. int frags;
  335. int lvi;
  336. int lvi_frag;
  337. int civ;
  338. int ack;
  339. int ack_reload;
  340. unsigned int ack_bit;
  341. unsigned int roff_sr;
  342. unsigned int roff_picb;
  343. unsigned int int_sta_mask; /* interrupt status mask */
  344. unsigned int ali_slot; /* ALI DMA slot */
  345. struct ac97_pcm *pcm;
  346. int pcm_open_flag;
  347. unsigned int page_attr_changed: 1;
  348. unsigned int suspended: 1;
  349. };
  350. struct intel8x0 {
  351. unsigned int device_type;
  352. int irq;
  353. void __iomem *addr;
  354. void __iomem *bmaddr;
  355. struct pci_dev *pci;
  356. struct snd_card *card;
  357. int pcm_devs;
  358. struct snd_pcm *pcm[6];
  359. struct ichdev ichd[6];
  360. unsigned multi4: 1,
  361. multi6: 1,
  362. multi8 :1,
  363. dra: 1,
  364. smp20bit: 1;
  365. unsigned in_ac97_init: 1,
  366. in_sdin_init: 1;
  367. unsigned in_measurement: 1; /* during ac97 clock measurement */
  368. unsigned fix_nocache: 1; /* workaround for 440MX */
  369. unsigned buggy_irq: 1; /* workaround for buggy mobos */
  370. unsigned xbox: 1; /* workaround for Xbox AC'97 detection */
  371. unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */
  372. unsigned inside_vm: 1; /* enable VM optimization */
  373. int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
  374. unsigned int sdm_saved; /* SDM reg value */
  375. struct snd_ac97_bus *ac97_bus;
  376. struct snd_ac97 *ac97[3];
  377. unsigned int ac97_sdin[3];
  378. unsigned int max_codecs, ncodecs;
  379. unsigned int *codec_bit;
  380. unsigned int codec_isr_bits;
  381. unsigned int codec_ready_bits;
  382. spinlock_t reg_lock;
  383. u32 bdbars_count;
  384. struct snd_dma_buffer bdbars;
  385. u32 int_sta_reg; /* interrupt status register */
  386. u32 int_sta_mask; /* interrupt status mask */
  387. };
  388. static const struct pci_device_id snd_intel8x0_ids[] = {
  389. { PCI_VDEVICE(INTEL, 0x2415), DEVICE_INTEL }, /* 82801AA */
  390. { PCI_VDEVICE(INTEL, 0x2425), DEVICE_INTEL }, /* 82901AB */
  391. { PCI_VDEVICE(INTEL, 0x2445), DEVICE_INTEL }, /* 82801BA */
  392. { PCI_VDEVICE(INTEL, 0x2485), DEVICE_INTEL }, /* ICH3 */
  393. { PCI_VDEVICE(INTEL, 0x24c5), DEVICE_INTEL_ICH4 }, /* ICH4 */
  394. { PCI_VDEVICE(INTEL, 0x24d5), DEVICE_INTEL_ICH4 }, /* ICH5 */
  395. { PCI_VDEVICE(INTEL, 0x25a6), DEVICE_INTEL_ICH4 }, /* ESB */
  396. { PCI_VDEVICE(INTEL, 0x266e), DEVICE_INTEL_ICH4 }, /* ICH6 */
  397. { PCI_VDEVICE(INTEL, 0x27de), DEVICE_INTEL_ICH4 }, /* ICH7 */
  398. { PCI_VDEVICE(INTEL, 0x2698), DEVICE_INTEL_ICH4 }, /* ESB2 */
  399. { PCI_VDEVICE(INTEL, 0x7195), DEVICE_INTEL }, /* 440MX */
  400. { PCI_VDEVICE(SI, 0x7012), DEVICE_SIS }, /* SI7012 */
  401. { PCI_VDEVICE(NVIDIA, 0x01b1), DEVICE_NFORCE }, /* NFORCE */
  402. { PCI_VDEVICE(NVIDIA, 0x003a), DEVICE_NFORCE }, /* MCP04 */
  403. { PCI_VDEVICE(NVIDIA, 0x006a), DEVICE_NFORCE }, /* NFORCE2 */
  404. { PCI_VDEVICE(NVIDIA, 0x0059), DEVICE_NFORCE }, /* CK804 */
  405. { PCI_VDEVICE(NVIDIA, 0x008a), DEVICE_NFORCE }, /* CK8 */
  406. { PCI_VDEVICE(NVIDIA, 0x00da), DEVICE_NFORCE }, /* NFORCE3 */
  407. { PCI_VDEVICE(NVIDIA, 0x00ea), DEVICE_NFORCE }, /* CK8S */
  408. { PCI_VDEVICE(NVIDIA, 0x026b), DEVICE_NFORCE }, /* MCP51 */
  409. { PCI_VDEVICE(AMD, 0x746d), DEVICE_INTEL }, /* AMD8111 */
  410. { PCI_VDEVICE(AMD, 0x7445), DEVICE_INTEL }, /* AMD768 */
  411. { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI }, /* Ali5455 */
  412. { 0, }
  413. };
  414. MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);
  415. /*
  416. * Lowlevel I/O - busmaster
  417. */
  418. static inline u8 igetbyte(struct intel8x0 *chip, u32 offset)
  419. {
  420. return ioread8(chip->bmaddr + offset);
  421. }
  422. static inline u16 igetword(struct intel8x0 *chip, u32 offset)
  423. {
  424. return ioread16(chip->bmaddr + offset);
  425. }
  426. static inline u32 igetdword(struct intel8x0 *chip, u32 offset)
  427. {
  428. return ioread32(chip->bmaddr + offset);
  429. }
  430. static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
  431. {
  432. iowrite8(val, chip->bmaddr + offset);
  433. }
  434. static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val)
  435. {
  436. iowrite16(val, chip->bmaddr + offset);
  437. }
  438. static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
  439. {
  440. iowrite32(val, chip->bmaddr + offset);
  441. }
  442. /*
  443. * Lowlevel I/O - AC'97 registers
  444. */
  445. static inline u16 iagetword(struct intel8x0 *chip, u32 offset)
  446. {
  447. return ioread16(chip->addr + offset);
  448. }
  449. static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
  450. {
  451. iowrite16(val, chip->addr + offset);
  452. }
  453. /*
  454. * Basic I/O
  455. */
  456. /*
  457. * access to AC97 codec via normal i/o (for ICH and SIS7012)
  458. */
  459. static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
  460. {
  461. int time;
  462. if (codec > 2)
  463. return -EIO;
  464. if (chip->in_sdin_init) {
  465. /* we don't know the ready bit assignment at the moment */
  466. /* so we check any */
  467. codec = chip->codec_isr_bits;
  468. } else {
  469. codec = chip->codec_bit[chip->ac97_sdin[codec]];
  470. }
  471. /* codec ready ? */
  472. if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
  473. return -EIO;
  474. if (chip->buggy_semaphore)
  475. return 0; /* just ignore ... */
  476. /* Anyone holding a semaphore for 1 msec should be shot... */
  477. time = 100;
  478. do {
  479. if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
  480. return 0;
  481. udelay(10);
  482. } while (time--);
  483. /* access to some forbidden (non existent) ac97 registers will not
  484. * reset the semaphore. So even if you don't get the semaphore, still
  485. * continue the access. We don't need the semaphore anyway. */
  486. dev_err(chip->card->dev,
  487. "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
  488. igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
  489. iagetword(chip, 0); /* clear semaphore flag */
  490. /* I don't care about the semaphore */
  491. return -EBUSY;
  492. }
  493. static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
  494. unsigned short reg,
  495. unsigned short val)
  496. {
  497. struct intel8x0 *chip = ac97->private_data;
  498. if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
  499. if (! chip->in_ac97_init)
  500. dev_err(chip->card->dev,
  501. "codec_write %d: semaphore is not ready for register 0x%x\n",
  502. ac97->num, reg);
  503. }
  504. iaputword(chip, reg + ac97->num * 0x80, val);
  505. }
  506. static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
  507. unsigned short reg)
  508. {
  509. struct intel8x0 *chip = ac97->private_data;
  510. unsigned short res;
  511. unsigned int tmp;
  512. if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
  513. if (! chip->in_ac97_init)
  514. dev_err(chip->card->dev,
  515. "codec_read %d: semaphore is not ready for register 0x%x\n",
  516. ac97->num, reg);
  517. res = 0xffff;
  518. } else {
  519. res = iagetword(chip, reg + ac97->num * 0x80);
  520. if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
  521. /* reset RCS and preserve other R/WC bits */
  522. iputdword(chip, ICHREG(GLOB_STA), tmp &
  523. ~(chip->codec_ready_bits | ICH_GSCI));
  524. if (! chip->in_ac97_init)
  525. dev_err(chip->card->dev,
  526. "codec_read %d: read timeout for register 0x%x\n",
  527. ac97->num, reg);
  528. res = 0xffff;
  529. }
  530. }
  531. return res;
  532. }
  533. static void snd_intel8x0_codec_read_test(struct intel8x0 *chip,
  534. unsigned int codec)
  535. {
  536. unsigned int tmp;
  537. if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
  538. iagetword(chip, codec * 0x80);
  539. if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
  540. /* reset RCS and preserve other R/WC bits */
  541. iputdword(chip, ICHREG(GLOB_STA), tmp &
  542. ~(chip->codec_ready_bits | ICH_GSCI));
  543. }
  544. }
  545. }
  546. /*
  547. * access to AC97 for Ali5455
  548. */
  549. static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
  550. {
  551. int count = 0;
  552. for (count = 0; count < 0x7f; count++) {
  553. int val = igetbyte(chip, ICHREG(ALI_CSPSR));
  554. if (val & mask)
  555. return 0;
  556. }
  557. if (! chip->in_ac97_init)
  558. dev_warn(chip->card->dev, "AC97 codec ready timeout.\n");
  559. return -EBUSY;
  560. }
  561. static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
  562. {
  563. int time = 100;
  564. if (chip->buggy_semaphore)
  565. return 0; /* just ignore ... */
  566. while (--time && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
  567. udelay(1);
  568. if (! time && ! chip->in_ac97_init)
  569. dev_warn(chip->card->dev, "ali_codec_semaphore timeout\n");
  570. return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
  571. }
  572. static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
  573. {
  574. struct intel8x0 *chip = ac97->private_data;
  575. unsigned short data = 0xffff;
  576. if (snd_intel8x0_ali_codec_semaphore(chip))
  577. goto __err;
  578. reg |= ALI_CPR_ADDR_READ;
  579. if (ac97->num)
  580. reg |= ALI_CPR_ADDR_SECONDARY;
  581. iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
  582. if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
  583. goto __err;
  584. data = igetword(chip, ICHREG(ALI_SPR));
  585. __err:
  586. return data;
  587. }
  588. static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
  589. unsigned short val)
  590. {
  591. struct intel8x0 *chip = ac97->private_data;
  592. if (snd_intel8x0_ali_codec_semaphore(chip))
  593. return;
  594. iputword(chip, ICHREG(ALI_CPR), val);
  595. if (ac97->num)
  596. reg |= ALI_CPR_ADDR_SECONDARY;
  597. iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
  598. snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
  599. }
  600. /*
  601. * DMA I/O
  602. */
  603. static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev)
  604. {
  605. int idx;
  606. u32 *bdbar = ichdev->bdbar;
  607. unsigned long port = ichdev->reg_offset;
  608. iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
  609. if (ichdev->size == ichdev->fragsize) {
  610. ichdev->ack_reload = ichdev->ack = 2;
  611. ichdev->fragsize1 = ichdev->fragsize >> 1;
  612. for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
  613. bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
  614. bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
  615. ichdev->fragsize1 >> ichdev->pos_shift);
  616. bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
  617. bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
  618. ichdev->fragsize1 >> ichdev->pos_shift);
  619. }
  620. ichdev->frags = 2;
  621. } else {
  622. ichdev->ack_reload = ichdev->ack = 1;
  623. ichdev->fragsize1 = ichdev->fragsize;
  624. for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
  625. bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
  626. (((idx >> 1) * ichdev->fragsize) %
  627. ichdev->size));
  628. bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
  629. ichdev->fragsize >> ichdev->pos_shift);
  630. #if 0
  631. dev_dbg(chip->card->dev, "bdbar[%i] = 0x%x [0x%x]\n",
  632. idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
  633. #endif
  634. }
  635. ichdev->frags = ichdev->size / ichdev->fragsize;
  636. }
  637. iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
  638. ichdev->civ = 0;
  639. iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
  640. ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
  641. ichdev->position = 0;
  642. #if 0
  643. dev_dbg(chip->card->dev,
  644. "lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
  645. ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
  646. ichdev->fragsize1);
  647. #endif
  648. /* clear interrupts */
  649. iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
  650. }
  651. #ifdef __i386__
  652. /*
  653. * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
  654. * which aborts PCI busmaster for audio transfer. A workaround is to set
  655. * the pages as non-cached. For details, see the errata in
  656. * http://download.intel.com/design/chipsets/specupdt/24505108.pdf
  657. */
  658. static void fill_nocache(void *buf, int size, int nocache)
  659. {
  660. size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
  661. if (nocache)
  662. set_pages_uc(virt_to_page(buf), size);
  663. else
  664. set_pages_wb(virt_to_page(buf), size);
  665. }
  666. #else
  667. #define fill_nocache(buf, size, nocache) do { ; } while (0)
  668. #endif
  669. /*
  670. * Interrupt handler
  671. */
  672. static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
  673. {
  674. unsigned long port = ichdev->reg_offset;
  675. unsigned long flags;
  676. int status, civ, i, step;
  677. int ack = 0;
  678. spin_lock_irqsave(&chip->reg_lock, flags);
  679. status = igetbyte(chip, port + ichdev->roff_sr);
  680. civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
  681. if (!(status & ICH_BCIS)) {
  682. step = 0;
  683. } else if (civ == ichdev->civ) {
  684. // snd_printd("civ same %d\n", civ);
  685. step = 1;
  686. ichdev->civ++;
  687. ichdev->civ &= ICH_REG_LVI_MASK;
  688. } else {
  689. step = civ - ichdev->civ;
  690. if (step < 0)
  691. step += ICH_REG_LVI_MASK + 1;
  692. // if (step != 1)
  693. // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
  694. ichdev->civ = civ;
  695. }
  696. ichdev->position += step * ichdev->fragsize1;
  697. if (! chip->in_measurement)
  698. ichdev->position %= ichdev->size;
  699. ichdev->lvi += step;
  700. ichdev->lvi &= ICH_REG_LVI_MASK;
  701. iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
  702. for (i = 0; i < step; i++) {
  703. ichdev->lvi_frag++;
  704. ichdev->lvi_frag %= ichdev->frags;
  705. ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
  706. #if 0
  707. dev_dbg(chip->card->dev,
  708. "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",
  709. ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
  710. ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
  711. inl(port + 4), inb(port + ICH_REG_OFF_CR));
  712. #endif
  713. if (--ichdev->ack == 0) {
  714. ichdev->ack = ichdev->ack_reload;
  715. ack = 1;
  716. }
  717. }
  718. spin_unlock_irqrestore(&chip->reg_lock, flags);
  719. if (ack && ichdev->substream) {
  720. snd_pcm_period_elapsed(ichdev->substream);
  721. }
  722. iputbyte(chip, port + ichdev->roff_sr,
  723. status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
  724. }
  725. static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
  726. {
  727. struct intel8x0 *chip = dev_id;
  728. struct ichdev *ichdev;
  729. unsigned int status;
  730. unsigned int i;
  731. status = igetdword(chip, chip->int_sta_reg);
  732. if (status == 0xffffffff) /* we are not yet resumed */
  733. return IRQ_NONE;
  734. if ((status & chip->int_sta_mask) == 0) {
  735. if (status) {
  736. /* ack */
  737. iputdword(chip, chip->int_sta_reg, status);
  738. if (! chip->buggy_irq)
  739. status = 0;
  740. }
  741. return IRQ_RETVAL(status);
  742. }
  743. for (i = 0; i < chip->bdbars_count; i++) {
  744. ichdev = &chip->ichd[i];
  745. if (status & ichdev->int_sta_mask)
  746. snd_intel8x0_update(chip, ichdev);
  747. }
  748. /* ack them */
  749. iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
  750. return IRQ_HANDLED;
  751. }
  752. /*
  753. * PCM part
  754. */
  755. static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
  756. {
  757. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  758. struct ichdev *ichdev = get_ichdev(substream);
  759. unsigned char val = 0;
  760. unsigned long port = ichdev->reg_offset;
  761. switch (cmd) {
  762. case SNDRV_PCM_TRIGGER_RESUME:
  763. ichdev->suspended = 0;
  764. /* fallthru */
  765. case SNDRV_PCM_TRIGGER_START:
  766. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  767. val = ICH_IOCE | ICH_STARTBM;
  768. ichdev->last_pos = ichdev->position;
  769. break;
  770. case SNDRV_PCM_TRIGGER_SUSPEND:
  771. ichdev->suspended = 1;
  772. /* fallthru */
  773. case SNDRV_PCM_TRIGGER_STOP:
  774. val = 0;
  775. break;
  776. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  777. val = ICH_IOCE;
  778. break;
  779. default:
  780. return -EINVAL;
  781. }
  782. iputbyte(chip, port + ICH_REG_OFF_CR, val);
  783. if (cmd == SNDRV_PCM_TRIGGER_STOP) {
  784. /* wait until DMA stopped */
  785. while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
  786. /* reset whole DMA things */
  787. iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
  788. }
  789. return 0;
  790. }
  791. static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
  792. {
  793. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  794. struct ichdev *ichdev = get_ichdev(substream);
  795. unsigned long port = ichdev->reg_offset;
  796. static int fiforeg[] = {
  797. ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
  798. };
  799. unsigned int val, fifo;
  800. val = igetdword(chip, ICHREG(ALI_DMACR));
  801. switch (cmd) {
  802. case SNDRV_PCM_TRIGGER_RESUME:
  803. ichdev->suspended = 0;
  804. /* fallthru */
  805. case SNDRV_PCM_TRIGGER_START:
  806. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  807. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  808. /* clear FIFO for synchronization of channels */
  809. fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
  810. fifo &= ~(0xff << (ichdev->ali_slot % 4));
  811. fifo |= 0x83 << (ichdev->ali_slot % 4);
  812. iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
  813. }
  814. iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
  815. val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
  816. /* start DMA */
  817. iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
  818. break;
  819. case SNDRV_PCM_TRIGGER_SUSPEND:
  820. ichdev->suspended = 1;
  821. /* fallthru */
  822. case SNDRV_PCM_TRIGGER_STOP:
  823. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  824. /* pause */
  825. iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
  826. iputbyte(chip, port + ICH_REG_OFF_CR, 0);
  827. while (igetbyte(chip, port + ICH_REG_OFF_CR))
  828. ;
  829. if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
  830. break;
  831. /* reset whole DMA things */
  832. iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
  833. /* clear interrupts */
  834. iputbyte(chip, port + ICH_REG_OFF_SR,
  835. igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
  836. iputdword(chip, ICHREG(ALI_INTERRUPTSR),
  837. igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
  838. break;
  839. default:
  840. return -EINVAL;
  841. }
  842. return 0;
  843. }
  844. static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
  845. struct snd_pcm_hw_params *hw_params)
  846. {
  847. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  848. struct ichdev *ichdev = get_ichdev(substream);
  849. struct snd_pcm_runtime *runtime = substream->runtime;
  850. int dbl = params_rate(hw_params) > 48000;
  851. int err;
  852. if (chip->fix_nocache && ichdev->page_attr_changed) {
  853. fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
  854. ichdev->page_attr_changed = 0;
  855. }
  856. err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  857. if (err < 0)
  858. return err;
  859. if (chip->fix_nocache) {
  860. if (runtime->dma_area && ! ichdev->page_attr_changed) {
  861. fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
  862. ichdev->page_attr_changed = 1;
  863. }
  864. }
  865. if (ichdev->pcm_open_flag) {
  866. snd_ac97_pcm_close(ichdev->pcm);
  867. ichdev->pcm_open_flag = 0;
  868. }
  869. err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
  870. params_channels(hw_params),
  871. ichdev->pcm->r[dbl].slots);
  872. if (err >= 0) {
  873. ichdev->pcm_open_flag = 1;
  874. /* Force SPDIF setting */
  875. if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
  876. snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
  877. params_rate(hw_params));
  878. }
  879. return err;
  880. }
  881. static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
  882. {
  883. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  884. struct ichdev *ichdev = get_ichdev(substream);
  885. if (ichdev->pcm_open_flag) {
  886. snd_ac97_pcm_close(ichdev->pcm);
  887. ichdev->pcm_open_flag = 0;
  888. }
  889. if (chip->fix_nocache && ichdev->page_attr_changed) {
  890. fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
  891. ichdev->page_attr_changed = 0;
  892. }
  893. return snd_pcm_lib_free_pages(substream);
  894. }
  895. static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
  896. struct snd_pcm_runtime *runtime)
  897. {
  898. unsigned int cnt;
  899. int dbl = runtime->rate > 48000;
  900. spin_lock_irq(&chip->reg_lock);
  901. switch (chip->device_type) {
  902. case DEVICE_ALI:
  903. cnt = igetdword(chip, ICHREG(ALI_SCR));
  904. cnt &= ~ICH_ALI_SC_PCM_246_MASK;
  905. if (runtime->channels == 4 || dbl)
  906. cnt |= ICH_ALI_SC_PCM_4;
  907. else if (runtime->channels == 6)
  908. cnt |= ICH_ALI_SC_PCM_6;
  909. iputdword(chip, ICHREG(ALI_SCR), cnt);
  910. break;
  911. case DEVICE_SIS:
  912. cnt = igetdword(chip, ICHREG(GLOB_CNT));
  913. cnt &= ~ICH_SIS_PCM_246_MASK;
  914. if (runtime->channels == 4 || dbl)
  915. cnt |= ICH_SIS_PCM_4;
  916. else if (runtime->channels == 6)
  917. cnt |= ICH_SIS_PCM_6;
  918. iputdword(chip, ICHREG(GLOB_CNT), cnt);
  919. break;
  920. default:
  921. cnt = igetdword(chip, ICHREG(GLOB_CNT));
  922. cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
  923. if (runtime->channels == 4 || dbl)
  924. cnt |= ICH_PCM_4;
  925. else if (runtime->channels == 6)
  926. cnt |= ICH_PCM_6;
  927. else if (runtime->channels == 8)
  928. cnt |= ICH_PCM_8;
  929. if (chip->device_type == DEVICE_NFORCE) {
  930. /* reset to 2ch once to keep the 6 channel data in alignment,
  931. * to start from Front Left always
  932. */
  933. if (cnt & ICH_PCM_246_MASK) {
  934. iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
  935. spin_unlock_irq(&chip->reg_lock);
  936. msleep(50); /* grrr... */
  937. spin_lock_irq(&chip->reg_lock);
  938. }
  939. } else if (chip->device_type == DEVICE_INTEL_ICH4) {
  940. if (runtime->sample_bits > 16)
  941. cnt |= ICH_PCM_20BIT;
  942. }
  943. iputdword(chip, ICHREG(GLOB_CNT), cnt);
  944. break;
  945. }
  946. spin_unlock_irq(&chip->reg_lock);
  947. }
  948. static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
  949. {
  950. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  951. struct snd_pcm_runtime *runtime = substream->runtime;
  952. struct ichdev *ichdev = get_ichdev(substream);
  953. ichdev->physbuf = runtime->dma_addr;
  954. ichdev->size = snd_pcm_lib_buffer_bytes(substream);
  955. ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
  956. if (ichdev->ichd == ICHD_PCMOUT) {
  957. snd_intel8x0_setup_pcm_out(chip, runtime);
  958. if (chip->device_type == DEVICE_INTEL_ICH4)
  959. ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
  960. }
  961. snd_intel8x0_setup_periods(chip, ichdev);
  962. return 0;
  963. }
  964. static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
  965. {
  966. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  967. struct ichdev *ichdev = get_ichdev(substream);
  968. size_t ptr1, ptr;
  969. int civ, timeout = 10;
  970. unsigned int position;
  971. spin_lock(&chip->reg_lock);
  972. do {
  973. civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
  974. ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
  975. position = ichdev->position;
  976. if (ptr1 == 0) {
  977. udelay(10);
  978. continue;
  979. }
  980. if (civ != igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV))
  981. continue;
  982. /* IO read operation is very expensive inside virtual machine
  983. * as it is emulated. The probability that subsequent PICB read
  984. * will return different result is high enough to loop till
  985. * timeout here.
  986. * Same CIV is strict enough condition to be sure that PICB
  987. * is valid inside VM on emulated card. */
  988. if (chip->inside_vm)
  989. break;
  990. if (ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
  991. break;
  992. } while (timeout--);
  993. ptr = ichdev->last_pos;
  994. if (ptr1 != 0) {
  995. ptr1 <<= ichdev->pos_shift;
  996. ptr = ichdev->fragsize1 - ptr1;
  997. ptr += position;
  998. if (ptr < ichdev->last_pos) {
  999. unsigned int pos_base, last_base;
  1000. pos_base = position / ichdev->fragsize1;
  1001. last_base = ichdev->last_pos / ichdev->fragsize1;
  1002. /* another sanity check; ptr1 can go back to full
  1003. * before the base position is updated
  1004. */
  1005. if (pos_base == last_base)
  1006. ptr = ichdev->last_pos;
  1007. }
  1008. }
  1009. ichdev->last_pos = ptr;
  1010. spin_unlock(&chip->reg_lock);
  1011. if (ptr >= ichdev->size)
  1012. return 0;
  1013. return bytes_to_frames(substream->runtime, ptr);
  1014. }
  1015. static struct snd_pcm_hardware snd_intel8x0_stream =
  1016. {
  1017. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  1018. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  1019. SNDRV_PCM_INFO_MMAP_VALID |
  1020. SNDRV_PCM_INFO_PAUSE |
  1021. SNDRV_PCM_INFO_RESUME),
  1022. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  1023. .rates = SNDRV_PCM_RATE_48000,
  1024. .rate_min = 48000,
  1025. .rate_max = 48000,
  1026. .channels_min = 2,
  1027. .channels_max = 2,
  1028. .buffer_bytes_max = 128 * 1024,
  1029. .period_bytes_min = 32,
  1030. .period_bytes_max = 128 * 1024,
  1031. .periods_min = 1,
  1032. .periods_max = 1024,
  1033. .fifo_size = 0,
  1034. };
  1035. static unsigned int channels4[] = {
  1036. 2, 4,
  1037. };
  1038. static struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
  1039. .count = ARRAY_SIZE(channels4),
  1040. .list = channels4,
  1041. .mask = 0,
  1042. };
  1043. static unsigned int channels6[] = {
  1044. 2, 4, 6,
  1045. };
  1046. static struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
  1047. .count = ARRAY_SIZE(channels6),
  1048. .list = channels6,
  1049. .mask = 0,
  1050. };
  1051. static unsigned int channels8[] = {
  1052. 2, 4, 6, 8,
  1053. };
  1054. static struct snd_pcm_hw_constraint_list hw_constraints_channels8 = {
  1055. .count = ARRAY_SIZE(channels8),
  1056. .list = channels8,
  1057. .mask = 0,
  1058. };
  1059. static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
  1060. {
  1061. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1062. struct snd_pcm_runtime *runtime = substream->runtime;
  1063. int err;
  1064. ichdev->substream = substream;
  1065. runtime->hw = snd_intel8x0_stream;
  1066. runtime->hw.rates = ichdev->pcm->rates;
  1067. snd_pcm_limit_hw_rates(runtime);
  1068. if (chip->device_type == DEVICE_SIS) {
  1069. runtime->hw.buffer_bytes_max = 64*1024;
  1070. runtime->hw.period_bytes_max = 64*1024;
  1071. }
  1072. if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
  1073. return err;
  1074. runtime->private_data = ichdev;
  1075. return 0;
  1076. }
  1077. static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
  1078. {
  1079. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1080. struct snd_pcm_runtime *runtime = substream->runtime;
  1081. int err;
  1082. err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
  1083. if (err < 0)
  1084. return err;
  1085. if (chip->multi8) {
  1086. runtime->hw.channels_max = 8;
  1087. snd_pcm_hw_constraint_list(runtime, 0,
  1088. SNDRV_PCM_HW_PARAM_CHANNELS,
  1089. &hw_constraints_channels8);
  1090. } else if (chip->multi6) {
  1091. runtime->hw.channels_max = 6;
  1092. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
  1093. &hw_constraints_channels6);
  1094. } else if (chip->multi4) {
  1095. runtime->hw.channels_max = 4;
  1096. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
  1097. &hw_constraints_channels4);
  1098. }
  1099. if (chip->dra) {
  1100. snd_ac97_pcm_double_rate_rules(runtime);
  1101. }
  1102. if (chip->smp20bit) {
  1103. runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
  1104. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
  1105. }
  1106. return 0;
  1107. }
  1108. static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
  1109. {
  1110. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1111. chip->ichd[ICHD_PCMOUT].substream = NULL;
  1112. return 0;
  1113. }
  1114. static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
  1115. {
  1116. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1117. return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
  1118. }
  1119. static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
  1120. {
  1121. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1122. chip->ichd[ICHD_PCMIN].substream = NULL;
  1123. return 0;
  1124. }
  1125. static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
  1126. {
  1127. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1128. return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
  1129. }
  1130. static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
  1131. {
  1132. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1133. chip->ichd[ICHD_MIC].substream = NULL;
  1134. return 0;
  1135. }
  1136. static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
  1137. {
  1138. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1139. return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
  1140. }
  1141. static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
  1142. {
  1143. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1144. chip->ichd[ICHD_MIC2].substream = NULL;
  1145. return 0;
  1146. }
  1147. static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
  1148. {
  1149. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1150. return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
  1151. }
  1152. static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
  1153. {
  1154. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1155. chip->ichd[ICHD_PCM2IN].substream = NULL;
  1156. return 0;
  1157. }
  1158. static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
  1159. {
  1160. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1161. int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
  1162. return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
  1163. }
  1164. static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
  1165. {
  1166. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1167. int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;
  1168. chip->ichd[idx].substream = NULL;
  1169. return 0;
  1170. }
  1171. static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
  1172. {
  1173. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1174. unsigned int val;
  1175. spin_lock_irq(&chip->reg_lock);
  1176. val = igetdword(chip, ICHREG(ALI_INTERFACECR));
  1177. val |= ICH_ALI_IF_AC97SP;
  1178. iputdword(chip, ICHREG(ALI_INTERFACECR), val);
  1179. /* also needs to set ALI_SC_CODEC_SPDF correctly */
  1180. spin_unlock_irq(&chip->reg_lock);
  1181. return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
  1182. }
  1183. static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
  1184. {
  1185. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1186. unsigned int val;
  1187. chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
  1188. spin_lock_irq(&chip->reg_lock);
  1189. val = igetdword(chip, ICHREG(ALI_INTERFACECR));
  1190. val &= ~ICH_ALI_IF_AC97SP;
  1191. iputdword(chip, ICHREG(ALI_INTERFACECR), val);
  1192. spin_unlock_irq(&chip->reg_lock);
  1193. return 0;
  1194. }
  1195. #if 0 // NYI
  1196. static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
  1197. {
  1198. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1199. return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
  1200. }
  1201. static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
  1202. {
  1203. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1204. chip->ichd[ALID_SPDIFIN].substream = NULL;
  1205. return 0;
  1206. }
  1207. static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
  1208. {
  1209. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1210. return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
  1211. }
  1212. static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
  1213. {
  1214. struct intel8x0 *chip = snd_pcm_substream_chip(substream);
  1215. chip->ichd[ALID_SPDIFOUT].substream = NULL;
  1216. return 0;
  1217. }
  1218. #endif
  1219. static struct snd_pcm_ops snd_intel8x0_playback_ops = {
  1220. .open = snd_intel8x0_playback_open,
  1221. .close = snd_intel8x0_playback_close,
  1222. .ioctl = snd_pcm_lib_ioctl,
  1223. .hw_params = snd_intel8x0_hw_params,
  1224. .hw_free = snd_intel8x0_hw_free,
  1225. .prepare = snd_intel8x0_pcm_prepare,
  1226. .trigger = snd_intel8x0_pcm_trigger,
  1227. .pointer = snd_intel8x0_pcm_pointer,
  1228. };
  1229. static struct snd_pcm_ops snd_intel8x0_capture_ops = {
  1230. .open = snd_intel8x0_capture_open,
  1231. .close = snd_intel8x0_capture_close,
  1232. .ioctl = snd_pcm_lib_ioctl,
  1233. .hw_params = snd_intel8x0_hw_params,
  1234. .hw_free = snd_intel8x0_hw_free,
  1235. .prepare = snd_intel8x0_pcm_prepare,
  1236. .trigger = snd_intel8x0_pcm_trigger,
  1237. .pointer = snd_intel8x0_pcm_pointer,
  1238. };
  1239. static struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
  1240. .open = snd_intel8x0_mic_open,
  1241. .close = snd_intel8x0_mic_close,
  1242. .ioctl = snd_pcm_lib_ioctl,
  1243. .hw_params = snd_intel8x0_hw_params,
  1244. .hw_free = snd_intel8x0_hw_free,
  1245. .prepare = snd_intel8x0_pcm_prepare,
  1246. .trigger = snd_intel8x0_pcm_trigger,
  1247. .pointer = snd_intel8x0_pcm_pointer,
  1248. };
  1249. static struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
  1250. .open = snd_intel8x0_mic2_open,
  1251. .close = snd_intel8x0_mic2_close,
  1252. .ioctl = snd_pcm_lib_ioctl,
  1253. .hw_params = snd_intel8x0_hw_params,
  1254. .hw_free = snd_intel8x0_hw_free,
  1255. .prepare = snd_intel8x0_pcm_prepare,
  1256. .trigger = snd_intel8x0_pcm_trigger,
  1257. .pointer = snd_intel8x0_pcm_pointer,
  1258. };
  1259. static struct snd_pcm_ops snd_intel8x0_capture2_ops = {
  1260. .open = snd_intel8x0_capture2_open,
  1261. .close = snd_intel8x0_capture2_close,
  1262. .ioctl = snd_pcm_lib_ioctl,
  1263. .hw_params = snd_intel8x0_hw_params,
  1264. .hw_free = snd_intel8x0_hw_free,
  1265. .prepare = snd_intel8x0_pcm_prepare,
  1266. .trigger = snd_intel8x0_pcm_trigger,
  1267. .pointer = snd_intel8x0_pcm_pointer,
  1268. };
  1269. static struct snd_pcm_ops snd_intel8x0_spdif_ops = {
  1270. .open = snd_intel8x0_spdif_open,
  1271. .close = snd_intel8x0_spdif_close,
  1272. .ioctl = snd_pcm_lib_ioctl,
  1273. .hw_params = snd_intel8x0_hw_params,
  1274. .hw_free = snd_intel8x0_hw_free,
  1275. .prepare = snd_intel8x0_pcm_prepare,
  1276. .trigger = snd_intel8x0_pcm_trigger,
  1277. .pointer = snd_intel8x0_pcm_pointer,
  1278. };
  1279. static struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
  1280. .open = snd_intel8x0_playback_open,
  1281. .close = snd_intel8x0_playback_close,
  1282. .ioctl = snd_pcm_lib_ioctl,
  1283. .hw_params = snd_intel8x0_hw_params,
  1284. .hw_free = snd_intel8x0_hw_free,
  1285. .prepare = snd_intel8x0_pcm_prepare,
  1286. .trigger = snd_intel8x0_ali_trigger,
  1287. .pointer = snd_intel8x0_pcm_pointer,
  1288. };
  1289. static struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
  1290. .open = snd_intel8x0_capture_open,
  1291. .close = snd_intel8x0_capture_close,
  1292. .ioctl = snd_pcm_lib_ioctl,
  1293. .hw_params = snd_intel8x0_hw_params,
  1294. .hw_free = snd_intel8x0_hw_free,
  1295. .prepare = snd_intel8x0_pcm_prepare,
  1296. .trigger = snd_intel8x0_ali_trigger,
  1297. .pointer = snd_intel8x0_pcm_pointer,
  1298. };
  1299. static struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
  1300. .open = snd_intel8x0_mic_open,
  1301. .close = snd_intel8x0_mic_close,
  1302. .ioctl = snd_pcm_lib_ioctl,
  1303. .hw_params = snd_intel8x0_hw_params,
  1304. .hw_free = snd_intel8x0_hw_free,
  1305. .prepare = snd_intel8x0_pcm_prepare,
  1306. .trigger = snd_intel8x0_ali_trigger,
  1307. .pointer = snd_intel8x0_pcm_pointer,
  1308. };
  1309. static struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
  1310. .open = snd_intel8x0_ali_ac97spdifout_open,
  1311. .close = snd_intel8x0_ali_ac97spdifout_close,
  1312. .ioctl = snd_pcm_lib_ioctl,
  1313. .hw_params = snd_intel8x0_hw_params,
  1314. .hw_free = snd_intel8x0_hw_free,
  1315. .prepare = snd_intel8x0_pcm_prepare,
  1316. .trigger = snd_intel8x0_ali_trigger,
  1317. .pointer = snd_intel8x0_pcm_pointer,
  1318. };
  1319. #if 0 // NYI
  1320. static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
  1321. .open = snd_intel8x0_ali_spdifin_open,
  1322. .close = snd_intel8x0_ali_spdifin_close,
  1323. .ioctl = snd_pcm_lib_ioctl,
  1324. .hw_params = snd_intel8x0_hw_params,
  1325. .hw_free = snd_intel8x0_hw_free,
  1326. .prepare = snd_intel8x0_pcm_prepare,
  1327. .trigger = snd_intel8x0_pcm_trigger,
  1328. .pointer = snd_intel8x0_pcm_pointer,
  1329. };
  1330. static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
  1331. .open = snd_intel8x0_ali_spdifout_open,
  1332. .close = snd_intel8x0_ali_spdifout_close,
  1333. .ioctl = snd_pcm_lib_ioctl,
  1334. .hw_params = snd_intel8x0_hw_params,
  1335. .hw_free = snd_intel8x0_hw_free,
  1336. .prepare = snd_intel8x0_pcm_prepare,
  1337. .trigger = snd_intel8x0_pcm_trigger,
  1338. .pointer = snd_intel8x0_pcm_pointer,
  1339. };
  1340. #endif // NYI
  1341. struct ich_pcm_table {
  1342. char *suffix;
  1343. struct snd_pcm_ops *playback_ops;
  1344. struct snd_pcm_ops *capture_ops;
  1345. size_t prealloc_size;
  1346. size_t prealloc_max_size;
  1347. int ac97_idx;
  1348. };
  1349. static int snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
  1350. struct ich_pcm_table *rec)
  1351. {
  1352. struct snd_pcm *pcm;
  1353. int err;
  1354. char name[32];
  1355. if (rec->suffix)
  1356. sprintf(name, "Intel ICH - %s", rec->suffix);
  1357. else
  1358. strcpy(name, "Intel ICH");
  1359. err = snd_pcm_new(chip->card, name, device,
  1360. rec->playback_ops ? 1 : 0,
  1361. rec->capture_ops ? 1 : 0, &pcm);
  1362. if (err < 0)
  1363. return err;
  1364. if (rec->playback_ops)
  1365. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
  1366. if (rec->capture_ops)
  1367. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
  1368. pcm->private_data = chip;
  1369. pcm->info_flags = 0;
  1370. if (rec->suffix)
  1371. sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
  1372. else
  1373. strcpy(pcm->name, chip->card->shortname);
  1374. chip->pcm[device] = pcm;
  1375. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1376. snd_dma_pci_data(chip->pci),
  1377. rec->prealloc_size, rec->prealloc_max_size);
  1378. if (rec->playback_ops &&
  1379. rec->playback_ops->open == snd_intel8x0_playback_open) {
  1380. struct snd_pcm_chmap *chmap;
  1381. int chs = 2;
  1382. if (chip->multi8)
  1383. chs = 8;
  1384. else if (chip->multi6)
  1385. chs = 6;
  1386. else if (chip->multi4)
  1387. chs = 4;
  1388. err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1389. snd_pcm_alt_chmaps, chs, 0,
  1390. &chmap);
  1391. if (err < 0)
  1392. return err;
  1393. chmap->channel_mask = SND_PCM_CHMAP_MASK_2468;
  1394. chip->ac97[0]->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap;
  1395. }
  1396. return 0;
  1397. }
  1398. static struct ich_pcm_table intel_pcms[] = {
  1399. {
  1400. .playback_ops = &snd_intel8x0_playback_ops,
  1401. .capture_ops = &snd_intel8x0_capture_ops,
  1402. .prealloc_size = 64 * 1024,
  1403. .prealloc_max_size = 128 * 1024,
  1404. },
  1405. {
  1406. .suffix = "MIC ADC",
  1407. .capture_ops = &snd_intel8x0_capture_mic_ops,
  1408. .prealloc_size = 0,
  1409. .prealloc_max_size = 128 * 1024,
  1410. .ac97_idx = ICHD_MIC,
  1411. },
  1412. {
  1413. .suffix = "MIC2 ADC",
  1414. .capture_ops = &snd_intel8x0_capture_mic2_ops,
  1415. .prealloc_size = 0,
  1416. .prealloc_max_size = 128 * 1024,
  1417. .ac97_idx = ICHD_MIC2,
  1418. },
  1419. {
  1420. .suffix = "ADC2",
  1421. .capture_ops = &snd_intel8x0_capture2_ops,
  1422. .prealloc_size = 0,
  1423. .prealloc_max_size = 128 * 1024,
  1424. .ac97_idx = ICHD_PCM2IN,
  1425. },
  1426. {
  1427. .suffix = "IEC958",
  1428. .playback_ops = &snd_intel8x0_spdif_ops,
  1429. .prealloc_size = 64 * 1024,
  1430. .prealloc_max_size = 128 * 1024,
  1431. .ac97_idx = ICHD_SPBAR,
  1432. },
  1433. };
  1434. static struct ich_pcm_table nforce_pcms[] = {
  1435. {
  1436. .playback_ops = &snd_intel8x0_playback_ops,
  1437. .capture_ops = &snd_intel8x0_capture_ops,
  1438. .prealloc_size = 64 * 1024,
  1439. .prealloc_max_size = 128 * 1024,
  1440. },
  1441. {
  1442. .suffix = "MIC ADC",
  1443. .capture_ops = &snd_intel8x0_capture_mic_ops,
  1444. .prealloc_size = 0,
  1445. .prealloc_max_size = 128 * 1024,
  1446. .ac97_idx = NVD_MIC,
  1447. },
  1448. {
  1449. .suffix = "IEC958",
  1450. .playback_ops = &snd_intel8x0_spdif_ops,
  1451. .prealloc_size = 64 * 1024,
  1452. .prealloc_max_size = 128 * 1024,
  1453. .ac97_idx = NVD_SPBAR,
  1454. },
  1455. };
  1456. static struct ich_pcm_table ali_pcms[] = {
  1457. {
  1458. .playback_ops = &snd_intel8x0_ali_playback_ops,
  1459. .capture_ops = &snd_intel8x0_ali_capture_ops,
  1460. .prealloc_size = 64 * 1024,
  1461. .prealloc_max_size = 128 * 1024,
  1462. },
  1463. {
  1464. .suffix = "MIC ADC",
  1465. .capture_ops = &snd_intel8x0_ali_capture_mic_ops,
  1466. .prealloc_size = 0,
  1467. .prealloc_max_size = 128 * 1024,
  1468. .ac97_idx = ALID_MIC,
  1469. },
  1470. {
  1471. .suffix = "IEC958",
  1472. .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
  1473. /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
  1474. .prealloc_size = 64 * 1024,
  1475. .prealloc_max_size = 128 * 1024,
  1476. .ac97_idx = ALID_AC97SPDIFOUT,
  1477. },
  1478. #if 0 // NYI
  1479. {
  1480. .suffix = "HW IEC958",
  1481. .playback_ops = &snd_intel8x0_ali_spdifout_ops,
  1482. .prealloc_size = 64 * 1024,
  1483. .prealloc_max_size = 128 * 1024,
  1484. },
  1485. #endif
  1486. };
  1487. static int snd_intel8x0_pcm(struct intel8x0 *chip)
  1488. {
  1489. int i, tblsize, device, err;
  1490. struct ich_pcm_table *tbl, *rec;
  1491. switch (chip->device_type) {
  1492. case DEVICE_INTEL_ICH4:
  1493. tbl = intel_pcms;
  1494. tblsize = ARRAY_SIZE(intel_pcms);
  1495. if (spdif_aclink)
  1496. tblsize--;
  1497. break;
  1498. case DEVICE_NFORCE:
  1499. tbl = nforce_pcms;
  1500. tblsize = ARRAY_SIZE(nforce_pcms);
  1501. if (spdif_aclink)
  1502. tblsize--;
  1503. break;
  1504. case DEVICE_ALI:
  1505. tbl = ali_pcms;
  1506. tblsize = ARRAY_SIZE(ali_pcms);
  1507. break;
  1508. default:
  1509. tbl = intel_pcms;
  1510. tblsize = 2;
  1511. break;
  1512. }
  1513. device = 0;
  1514. for (i = 0; i < tblsize; i++) {
  1515. rec = tbl + i;
  1516. if (i > 0 && rec->ac97_idx) {
  1517. /* activate PCM only when associated AC'97 codec */
  1518. if (! chip->ichd[rec->ac97_idx].pcm)
  1519. continue;
  1520. }
  1521. err = snd_intel8x0_pcm1(chip, device, rec);
  1522. if (err < 0)
  1523. return err;
  1524. device++;
  1525. }
  1526. chip->pcm_devs = device;
  1527. return 0;
  1528. }
  1529. /*
  1530. * Mixer part
  1531. */
  1532. static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
  1533. {
  1534. struct intel8x0 *chip = bus->private_data;
  1535. chip->ac97_bus = NULL;
  1536. }
  1537. static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
  1538. {
  1539. struct intel8x0 *chip = ac97->private_data;
  1540. chip->ac97[ac97->num] = NULL;
  1541. }
  1542. static struct ac97_pcm ac97_pcm_defs[] = {
  1543. /* front PCM */
  1544. {
  1545. .exclusive = 1,
  1546. .r = { {
  1547. .slots = (1 << AC97_SLOT_PCM_LEFT) |
  1548. (1 << AC97_SLOT_PCM_RIGHT) |
  1549. (1 << AC97_SLOT_PCM_CENTER) |
  1550. (1 << AC97_SLOT_PCM_SLEFT) |
  1551. (1 << AC97_SLOT_PCM_SRIGHT) |
  1552. (1 << AC97_SLOT_LFE)
  1553. },
  1554. {
  1555. .slots = (1 << AC97_SLOT_PCM_LEFT) |
  1556. (1 << AC97_SLOT_PCM_RIGHT) |
  1557. (1 << AC97_SLOT_PCM_LEFT_0) |
  1558. (1 << AC97_SLOT_PCM_RIGHT_0)
  1559. }
  1560. }
  1561. },
  1562. /* PCM IN #1 */
  1563. {
  1564. .stream = 1,
  1565. .exclusive = 1,
  1566. .r = { {
  1567. .slots = (1 << AC97_SLOT_PCM_LEFT) |
  1568. (1 << AC97_SLOT_PCM_RIGHT)
  1569. }
  1570. }
  1571. },
  1572. /* MIC IN #1 */
  1573. {
  1574. .stream = 1,
  1575. .exclusive = 1,
  1576. .r = { {
  1577. .slots = (1 << AC97_SLOT_MIC)
  1578. }
  1579. }
  1580. },
  1581. /* S/PDIF PCM */
  1582. {
  1583. .exclusive = 1,
  1584. .spdif = 1,
  1585. .r = { {
  1586. .slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
  1587. (1 << AC97_SLOT_SPDIF_RIGHT2)
  1588. }
  1589. }
  1590. },
  1591. /* PCM IN #2 */
  1592. {
  1593. .stream = 1,
  1594. .exclusive = 1,
  1595. .r = { {
  1596. .slots = (1 << AC97_SLOT_PCM_LEFT) |
  1597. (1 << AC97_SLOT_PCM_RIGHT)
  1598. }
  1599. }
  1600. },
  1601. /* MIC IN #2 */
  1602. {
  1603. .stream = 1,
  1604. .exclusive = 1,
  1605. .r = { {
  1606. .slots = (1 << AC97_SLOT_MIC)
  1607. }
  1608. }
  1609. },
  1610. };
  1611. static const struct ac97_quirk ac97_quirks[] = {
  1612. {
  1613. .subvendor = 0x0e11,
  1614. .subdevice = 0x000e,
  1615. .name = "Compaq Deskpro EN", /* AD1885 */
  1616. .type = AC97_TUNE_HP_ONLY
  1617. },
  1618. {
  1619. .subvendor = 0x0e11,
  1620. .subdevice = 0x008a,
  1621. .name = "Compaq Evo W4000", /* AD1885 */
  1622. .type = AC97_TUNE_HP_ONLY
  1623. },
  1624. {
  1625. .subvendor = 0x0e11,
  1626. .subdevice = 0x00b8,
  1627. .name = "Compaq Evo D510C",
  1628. .type = AC97_TUNE_HP_ONLY
  1629. },
  1630. {
  1631. .subvendor = 0x0e11,
  1632. .subdevice = 0x0860,
  1633. .name = "HP/Compaq nx7010",
  1634. .type = AC97_TUNE_MUTE_LED
  1635. },
  1636. {
  1637. .subvendor = 0x1014,
  1638. .subdevice = 0x0534,
  1639. .name = "ThinkPad X31",
  1640. .type = AC97_TUNE_INV_EAPD
  1641. },
  1642. {
  1643. .subvendor = 0x1014,
  1644. .subdevice = 0x1f00,
  1645. .name = "MS-9128",
  1646. .type = AC97_TUNE_ALC_JACK
  1647. },
  1648. {
  1649. .subvendor = 0x1014,
  1650. .subdevice = 0x0267,
  1651. .name = "IBM NetVista A30p", /* AD1981B */
  1652. .type = AC97_TUNE_HP_ONLY
  1653. },
  1654. {
  1655. .subvendor = 0x1025,
  1656. .subdevice = 0x0082,
  1657. .name = "Acer Travelmate 2310",
  1658. .type = AC97_TUNE_HP_ONLY
  1659. },
  1660. {
  1661. .subvendor = 0x1025,
  1662. .subdevice = 0x0083,
  1663. .name = "Acer Aspire 3003LCi",
  1664. .type = AC97_TUNE_HP_ONLY
  1665. },
  1666. {
  1667. .subvendor = 0x1028,
  1668. .subdevice = 0x00d8,
  1669. .name = "Dell Precision 530", /* AD1885 */
  1670. .type = AC97_TUNE_HP_ONLY
  1671. },
  1672. {
  1673. .subvendor = 0x1028,
  1674. .subdevice = 0x010d,
  1675. .name = "Dell", /* which model? AD1885 */
  1676. .type = AC97_TUNE_HP_ONLY
  1677. },
  1678. {
  1679. .subvendor = 0x1028,
  1680. .subdevice = 0x0126,
  1681. .name = "Dell Optiplex GX260", /* AD1981A */
  1682. .type = AC97_TUNE_HP_ONLY
  1683. },
  1684. {
  1685. .subvendor = 0x1028,
  1686. .subdevice = 0x012c,
  1687. .name = "Dell Precision 650", /* AD1981A */
  1688. .type = AC97_TUNE_HP_ONLY
  1689. },
  1690. {
  1691. .subvendor = 0x1028,
  1692. .subdevice = 0x012d,
  1693. .name = "Dell Precision 450", /* AD1981B*/
  1694. .type = AC97_TUNE_HP_ONLY
  1695. },
  1696. {
  1697. .subvendor = 0x1028,
  1698. .subdevice = 0x0147,
  1699. .name = "Dell", /* which model? AD1981B*/
  1700. .type = AC97_TUNE_HP_ONLY
  1701. },
  1702. {
  1703. .subvendor = 0x1028,
  1704. .subdevice = 0x0151,
  1705. .name = "Dell Optiplex GX270", /* AD1981B */
  1706. .type = AC97_TUNE_HP_ONLY
  1707. },
  1708. {
  1709. .subvendor = 0x1028,
  1710. .subdevice = 0x014e,
  1711. .name = "Dell D800", /* STAC9750/51 */
  1712. .type = AC97_TUNE_HP_ONLY
  1713. },
  1714. {
  1715. .subvendor = 0x1028,
  1716. .subdevice = 0x0163,
  1717. .name = "Dell Unknown", /* STAC9750/51 */
  1718. .type = AC97_TUNE_HP_ONLY
  1719. },
  1720. {
  1721. .subvendor = 0x1028,
  1722. .subdevice = 0x016a,
  1723. .name = "Dell Inspiron 8600", /* STAC9750/51 */
  1724. .type = AC97_TUNE_HP_ONLY
  1725. },
  1726. {
  1727. .subvendor = 0x1028,
  1728. .subdevice = 0x0182,
  1729. .name = "Dell Latitude D610", /* STAC9750/51 */
  1730. .type = AC97_TUNE_HP_ONLY
  1731. },
  1732. {
  1733. .subvendor = 0x1028,
  1734. .subdevice = 0x0186,
  1735. .name = "Dell Latitude D810", /* cf. Malone #41015 */
  1736. .type = AC97_TUNE_HP_MUTE_LED
  1737. },
  1738. {
  1739. .subvendor = 0x1028,
  1740. .subdevice = 0x0188,
  1741. .name = "Dell Inspiron 6000",
  1742. .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */
  1743. },
  1744. {
  1745. .subvendor = 0x1028,
  1746. .subdevice = 0x0189,
  1747. .name = "Dell Inspiron 9300",
  1748. .type = AC97_TUNE_HP_MUTE_LED
  1749. },
  1750. {
  1751. .subvendor = 0x1028,
  1752. .subdevice = 0x0191,
  1753. .name = "Dell Inspiron 8600",
  1754. .type = AC97_TUNE_HP_ONLY
  1755. },
  1756. {
  1757. .subvendor = 0x103c,
  1758. .subdevice = 0x006d,
  1759. .name = "HP zv5000",
  1760. .type = AC97_TUNE_MUTE_LED /*AD1981B*/
  1761. },
  1762. { /* FIXME: which codec? */
  1763. .subvendor = 0x103c,
  1764. .subdevice = 0x00c3,
  1765. .name = "HP xw6000",
  1766. .type = AC97_TUNE_HP_ONLY
  1767. },
  1768. {
  1769. .subvendor = 0x103c,
  1770. .subdevice = 0x088c,
  1771. .name = "HP nc8000",
  1772. .type = AC97_TUNE_HP_MUTE_LED
  1773. },
  1774. {
  1775. .subvendor = 0x103c,
  1776. .subdevice = 0x0890,
  1777. .name = "HP nc6000",
  1778. .type = AC97_TUNE_MUTE_LED
  1779. },
  1780. {
  1781. .subvendor = 0x103c,
  1782. .subdevice = 0x129d,
  1783. .name = "HP xw8000",
  1784. .type = AC97_TUNE_HP_ONLY
  1785. },
  1786. {
  1787. .subvendor = 0x103c,
  1788. .subdevice = 0x0938,
  1789. .name = "HP nc4200",
  1790. .type = AC97_TUNE_HP_MUTE_LED
  1791. },
  1792. {
  1793. .subvendor = 0x103c,
  1794. .subdevice = 0x099c,
  1795. .name = "HP nx6110/nc6120",
  1796. .type = AC97_TUNE_HP_MUTE_LED
  1797. },
  1798. {
  1799. .subvendor = 0x103c,
  1800. .subdevice = 0x0944,
  1801. .name = "HP nc6220",
  1802. .type = AC97_TUNE_HP_MUTE_LED
  1803. },
  1804. {
  1805. .subvendor = 0x103c,
  1806. .subdevice = 0x0934,
  1807. .name = "HP nc8220",
  1808. .type = AC97_TUNE_HP_MUTE_LED
  1809. },
  1810. {
  1811. .subvendor = 0x103c,
  1812. .subdevice = 0x12f1,
  1813. .name = "HP xw8200", /* AD1981B*/
  1814. .type = AC97_TUNE_HP_ONLY
  1815. },
  1816. {
  1817. .subvendor = 0x103c,
  1818. .subdevice = 0x12f2,
  1819. .name = "HP xw6200",
  1820. .type = AC97_TUNE_HP_ONLY
  1821. },
  1822. {
  1823. .subvendor = 0x103c,
  1824. .subdevice = 0x3008,
  1825. .name = "HP xw4200", /* AD1981B*/
  1826. .type = AC97_TUNE_HP_ONLY
  1827. },
  1828. {
  1829. .subvendor = 0x104d,
  1830. .subdevice = 0x8144,
  1831. .name = "Sony",
  1832. .type = AC97_TUNE_INV_EAPD
  1833. },
  1834. {
  1835. .subvendor = 0x104d,
  1836. .subdevice = 0x8197,
  1837. .name = "Sony S1XP",
  1838. .type = AC97_TUNE_INV_EAPD
  1839. },
  1840. {
  1841. .subvendor = 0x104d,
  1842. .subdevice = 0x81c0,
  1843. .name = "Sony VAIO VGN-T350P", /*AD1981B*/
  1844. .type = AC97_TUNE_INV_EAPD
  1845. },
  1846. {
  1847. .subvendor = 0x104d,
  1848. .subdevice = 0x81c5,
  1849. .name = "Sony VAIO VGN-B1VP", /*AD1981B*/
  1850. .type = AC97_TUNE_INV_EAPD
  1851. },
  1852. {
  1853. .subvendor = 0x1043,
  1854. .subdevice = 0x80f3,
  1855. .name = "ASUS ICH5/AD1985",
  1856. .type = AC97_TUNE_AD_SHARING
  1857. },
  1858. {
  1859. .subvendor = 0x10cf,
  1860. .subdevice = 0x11c3,
  1861. .name = "Fujitsu-Siemens E4010",
  1862. .type = AC97_TUNE_HP_ONLY
  1863. },
  1864. {
  1865. .subvendor = 0x10cf,
  1866. .subdevice = 0x1225,
  1867. .name = "Fujitsu-Siemens T3010",
  1868. .type = AC97_TUNE_HP_ONLY
  1869. },
  1870. {
  1871. .subvendor = 0x10cf,
  1872. .subdevice = 0x1253,
  1873. .name = "Fujitsu S6210", /* STAC9750/51 */
  1874. .type = AC97_TUNE_HP_ONLY
  1875. },
  1876. {
  1877. .subvendor = 0x10cf,
  1878. .subdevice = 0x127d,
  1879. .name = "Fujitsu Lifebook P7010",
  1880. .type = AC97_TUNE_HP_ONLY
  1881. },
  1882. {
  1883. .subvendor = 0x10cf,
  1884. .subdevice = 0x127e,
  1885. .name = "Fujitsu Lifebook C1211D",
  1886. .type = AC97_TUNE_HP_ONLY
  1887. },
  1888. {
  1889. .subvendor = 0x10cf,
  1890. .subdevice = 0x12ec,
  1891. .name = "Fujitsu-Siemens 4010",
  1892. .type = AC97_TUNE_HP_ONLY
  1893. },
  1894. {
  1895. .subvendor = 0x10cf,
  1896. .subdevice = 0x12f2,
  1897. .name = "Fujitsu-Siemens Celsius H320",
  1898. .type = AC97_TUNE_SWAP_HP
  1899. },
  1900. {
  1901. .subvendor = 0x10f1,
  1902. .subdevice = 0x2665,
  1903. .name = "Fujitsu-Siemens Celsius", /* AD1981? */
  1904. .type = AC97_TUNE_HP_ONLY
  1905. },
  1906. {
  1907. .subvendor = 0x10f1,
  1908. .subdevice = 0x2885,
  1909. .name = "AMD64 Mobo", /* ALC650 */
  1910. .type = AC97_TUNE_HP_ONLY
  1911. },
  1912. {
  1913. .subvendor = 0x10f1,
  1914. .subdevice = 0x2895,
  1915. .name = "Tyan Thunder K8WE",
  1916. .type = AC97_TUNE_HP_ONLY
  1917. },
  1918. {
  1919. .subvendor = 0x10f7,
  1920. .subdevice = 0x834c,
  1921. .name = "Panasonic CF-R4",
  1922. .type = AC97_TUNE_HP_ONLY,
  1923. },
  1924. {
  1925. .subvendor = 0x110a,
  1926. .subdevice = 0x0056,
  1927. .name = "Fujitsu-Siemens Scenic", /* AD1981? */
  1928. .type = AC97_TUNE_HP_ONLY
  1929. },
  1930. {
  1931. .subvendor = 0x11d4,
  1932. .subdevice = 0x5375,
  1933. .name = "ADI AD1985 (discrete)",
  1934. .type = AC97_TUNE_HP_ONLY
  1935. },
  1936. {
  1937. .subvendor = 0x1462,
  1938. .subdevice = 0x5470,
  1939. .name = "MSI P4 ATX 645 Ultra",
  1940. .type = AC97_TUNE_HP_ONLY
  1941. },
  1942. {
  1943. .subvendor = 0x161f,
  1944. .subdevice = 0x202f,
  1945. .name = "Gateway M520",
  1946. .type = AC97_TUNE_INV_EAPD
  1947. },
  1948. {
  1949. .subvendor = 0x161f,
  1950. .subdevice = 0x203a,
  1951. .name = "Gateway 4525GZ", /* AD1981B */
  1952. .type = AC97_TUNE_INV_EAPD
  1953. },
  1954. {
  1955. .subvendor = 0x1734,
  1956. .subdevice = 0x0088,
  1957. .name = "Fujitsu-Siemens D1522", /* AD1981 */
  1958. .type = AC97_TUNE_HP_ONLY
  1959. },
  1960. {
  1961. .subvendor = 0x8086,
  1962. .subdevice = 0x2000,
  1963. .mask = 0xfff0,
  1964. .name = "Intel ICH5/AD1985",
  1965. .type = AC97_TUNE_AD_SHARING
  1966. },
  1967. {
  1968. .subvendor = 0x8086,
  1969. .subdevice = 0x4000,
  1970. .mask = 0xfff0,
  1971. .name = "Intel ICH5/AD1985",
  1972. .type = AC97_TUNE_AD_SHARING
  1973. },
  1974. {
  1975. .subvendor = 0x8086,
  1976. .subdevice = 0x4856,
  1977. .name = "Intel D845WN (82801BA)",
  1978. .type = AC97_TUNE_SWAP_HP
  1979. },
  1980. {
  1981. .subvendor = 0x8086,
  1982. .subdevice = 0x4d44,
  1983. .name = "Intel D850EMV2", /* AD1885 */
  1984. .type = AC97_TUNE_HP_ONLY
  1985. },
  1986. {
  1987. .subvendor = 0x8086,
  1988. .subdevice = 0x4d56,
  1989. .name = "Intel ICH/AD1885",
  1990. .type = AC97_TUNE_HP_ONLY
  1991. },
  1992. {
  1993. .subvendor = 0x8086,
  1994. .subdevice = 0x6000,
  1995. .mask = 0xfff0,
  1996. .name = "Intel ICH5/AD1985",
  1997. .type = AC97_TUNE_AD_SHARING
  1998. },
  1999. {
  2000. .subvendor = 0x8086,
  2001. .subdevice = 0xe000,
  2002. .mask = 0xfff0,
  2003. .name = "Intel ICH5/AD1985",
  2004. .type = AC97_TUNE_AD_SHARING
  2005. },
  2006. #if 0 /* FIXME: this seems wrong on most boards */
  2007. {
  2008. .subvendor = 0x8086,
  2009. .subdevice = 0xa000,
  2010. .mask = 0xfff0,
  2011. .name = "Intel ICH5/AD1985",
  2012. .type = AC97_TUNE_HP_ONLY
  2013. },
  2014. #endif
  2015. { } /* terminator */
  2016. };
  2017. static int snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
  2018. const char *quirk_override)
  2019. {
  2020. struct snd_ac97_bus *pbus;
  2021. struct snd_ac97_template ac97;
  2022. int err;
  2023. unsigned int i, codecs;
  2024. unsigned int glob_sta = 0;
  2025. struct snd_ac97_bus_ops *ops;
  2026. static struct snd_ac97_bus_ops standard_bus_ops = {
  2027. .write = snd_intel8x0_codec_write,
  2028. .read = snd_intel8x0_codec_read,
  2029. };
  2030. static struct snd_ac97_bus_ops ali_bus_ops = {
  2031. .write = snd_intel8x0_ali_codec_write,
  2032. .read = snd_intel8x0_ali_codec_read,
  2033. };
  2034. chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
  2035. if (!spdif_aclink) {
  2036. switch (chip->device_type) {
  2037. case DEVICE_NFORCE:
  2038. chip->spdif_idx = NVD_SPBAR;
  2039. break;
  2040. case DEVICE_ALI:
  2041. chip->spdif_idx = ALID_AC97SPDIFOUT;
  2042. break;
  2043. case DEVICE_INTEL_ICH4:
  2044. chip->spdif_idx = ICHD_SPBAR;
  2045. break;
  2046. }
  2047. }
  2048. chip->in_ac97_init = 1;
  2049. memset(&ac97, 0, sizeof(ac97));
  2050. ac97.private_data = chip;
  2051. ac97.private_free = snd_intel8x0_mixer_free_ac97;
  2052. ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
  2053. if (chip->xbox)
  2054. ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
  2055. if (chip->device_type != DEVICE_ALI) {
  2056. glob_sta = igetdword(chip, ICHREG(GLOB_STA));
  2057. ops = &standard_bus_ops;
  2058. chip->in_sdin_init = 1;
  2059. codecs = 0;
  2060. for (i = 0; i < chip->max_codecs; i++) {
  2061. if (! (glob_sta & chip->codec_bit[i]))
  2062. continue;
  2063. if (chip->device_type == DEVICE_INTEL_ICH4) {
  2064. snd_intel8x0_codec_read_test(chip, codecs);
  2065. chip->ac97_sdin[codecs] =
  2066. igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
  2067. if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3))
  2068. chip->ac97_sdin[codecs] = 0;
  2069. } else
  2070. chip->ac97_sdin[codecs] = i;
  2071. codecs++;
  2072. }
  2073. chip->in_sdin_init = 0;
  2074. if (! codecs)
  2075. codecs = 1;
  2076. } else {
  2077. ops = &ali_bus_ops;
  2078. codecs = 1;
  2079. /* detect the secondary codec */
  2080. for (i = 0; i < 100; i++) {
  2081. unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
  2082. if (reg & 0x40) {
  2083. codecs = 2;
  2084. break;
  2085. }
  2086. iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
  2087. udelay(1);
  2088. }
  2089. }
  2090. if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
  2091. goto __err;
  2092. pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
  2093. if (ac97_clock >= 8000 && ac97_clock <= 48000)
  2094. pbus->clock = ac97_clock;
  2095. /* FIXME: my test board doesn't work well with VRA... */
  2096. if (chip->device_type == DEVICE_ALI)
  2097. pbus->no_vra = 1;
  2098. else
  2099. pbus->dra = 1;
  2100. chip->ac97_bus = pbus;
  2101. chip->ncodecs = codecs;
  2102. ac97.pci = chip->pci;
  2103. for (i = 0; i < codecs; i++) {
  2104. ac97.num = i;
  2105. if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
  2106. if (err != -EACCES)
  2107. dev_err(chip->card->dev,
  2108. "Unable to initialize codec #%d\n", i);
  2109. if (i == 0)
  2110. goto __err;
  2111. }
  2112. }
  2113. /* tune up the primary codec */
  2114. snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
  2115. /* enable separate SDINs for ICH4 */
  2116. if (chip->device_type == DEVICE_INTEL_ICH4)
  2117. pbus->isdin = 1;
  2118. /* find the available PCM streams */
  2119. i = ARRAY_SIZE(ac97_pcm_defs);
  2120. if (chip->device_type != DEVICE_INTEL_ICH4)
  2121. i -= 2; /* do not allocate PCM2IN and MIC2 */
  2122. if (chip->spdif_idx < 0)
  2123. i--; /* do not allocate S/PDIF */
  2124. err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
  2125. if (err < 0)
  2126. goto __err;
  2127. chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
  2128. chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
  2129. chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
  2130. if (chip->spdif_idx >= 0)
  2131. chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
  2132. if (chip->device_type == DEVICE_INTEL_ICH4) {
  2133. chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
  2134. chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
  2135. }
  2136. /* enable separate SDINs for ICH4 */
  2137. if (chip->device_type == DEVICE_INTEL_ICH4) {
  2138. struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
  2139. u8 tmp = igetbyte(chip, ICHREG(SDM));
  2140. tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
  2141. if (pcm) {
  2142. tmp |= ICH_SE; /* steer enable for multiple SDINs */
  2143. tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
  2144. for (i = 1; i < 4; i++) {
  2145. if (pcm->r[0].codec[i]) {
  2146. tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
  2147. break;
  2148. }
  2149. }
  2150. } else {
  2151. tmp &= ~ICH_SE; /* steer disable */
  2152. }
  2153. iputbyte(chip, ICHREG(SDM), tmp);
  2154. }
  2155. if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
  2156. chip->multi4 = 1;
  2157. if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) {
  2158. chip->multi6 = 1;
  2159. if (chip->ac97[0]->flags & AC97_HAS_8CH)
  2160. chip->multi8 = 1;
  2161. }
  2162. }
  2163. if (pbus->pcms[0].r[1].rslots[0]) {
  2164. chip->dra = 1;
  2165. }
  2166. if (chip->device_type == DEVICE_INTEL_ICH4) {
  2167. if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
  2168. chip->smp20bit = 1;
  2169. }
  2170. if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
  2171. /* 48kHz only */
  2172. chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
  2173. }
  2174. if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
  2175. /* use slot 10/11 for SPDIF */
  2176. u32 val;
  2177. val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
  2178. val |= ICH_PCM_SPDIF_1011;
  2179. iputdword(chip, ICHREG(GLOB_CNT), val);
  2180. snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
  2181. }
  2182. chip->in_ac97_init = 0;
  2183. return 0;
  2184. __err:
  2185. /* clear the cold-reset bit for the next chance */
  2186. if (chip->device_type != DEVICE_ALI)
  2187. iputdword(chip, ICHREG(GLOB_CNT),
  2188. igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
  2189. return err;
  2190. }
  2191. /*
  2192. *
  2193. */
  2194. static void do_ali_reset(struct intel8x0 *chip)
  2195. {
  2196. iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
  2197. iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
  2198. iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
  2199. iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
  2200. iputdword(chip, ICHREG(ALI_INTERFACECR),
  2201. ICH_ALI_IF_PI|ICH_ALI_IF_PO);
  2202. iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
  2203. iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
  2204. }
  2205. #ifdef CONFIG_SND_AC97_POWER_SAVE
  2206. static struct snd_pci_quirk ich_chip_reset_mode[] = {
  2207. SND_PCI_QUIRK(0x1014, 0x051f, "Thinkpad R32", 1),
  2208. { } /* end */
  2209. };
  2210. static int snd_intel8x0_ich_chip_cold_reset(struct intel8x0 *chip)
  2211. {
  2212. unsigned int cnt;
  2213. /* ACLink on, 2 channels */
  2214. if (snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
  2215. return -EIO;
  2216. cnt = igetdword(chip, ICHREG(GLOB_CNT));
  2217. cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
  2218. /* do cold reset - the full ac97 powerdown may leave the controller
  2219. * in a warm state but actually it cannot communicate with the codec.
  2220. */
  2221. iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
  2222. cnt = igetdword(chip, ICHREG(GLOB_CNT));
  2223. udelay(10);
  2224. iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
  2225. msleep(1);
  2226. return 0;
  2227. }
  2228. #define snd_intel8x0_ich_chip_can_cold_reset(chip) \
  2229. (!snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
  2230. #else
  2231. #define snd_intel8x0_ich_chip_cold_reset(chip) 0
  2232. #define snd_intel8x0_ich_chip_can_cold_reset(chip) (0)
  2233. #endif
  2234. static int snd_intel8x0_ich_chip_reset(struct intel8x0 *chip)
  2235. {
  2236. unsigned long end_time;
  2237. unsigned int cnt;
  2238. /* ACLink on, 2 channels */
  2239. cnt = igetdword(chip, ICHREG(GLOB_CNT));
  2240. cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
  2241. /* finish cold or do warm reset */
  2242. cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
  2243. iputdword(chip, ICHREG(GLOB_CNT), cnt);
  2244. end_time = (jiffies + (HZ / 4)) + 1;
  2245. do {
  2246. if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
  2247. return 0;
  2248. schedule_timeout_uninterruptible(1);
  2249. } while (time_after_eq(end_time, jiffies));
  2250. dev_err(chip->card->dev, "AC'97 warm reset still in progress? [0x%x]\n",
  2251. igetdword(chip, ICHREG(GLOB_CNT)));
  2252. return -EIO;
  2253. }
  2254. static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
  2255. {
  2256. unsigned long end_time;
  2257. unsigned int status, nstatus;
  2258. unsigned int cnt;
  2259. int err;
  2260. /* put logic to right state */
  2261. /* first clear status bits */
  2262. status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
  2263. if (chip->device_type == DEVICE_NFORCE)
  2264. status |= ICH_NVSPINT;
  2265. cnt = igetdword(chip, ICHREG(GLOB_STA));
  2266. iputdword(chip, ICHREG(GLOB_STA), cnt & status);
  2267. if (snd_intel8x0_ich_chip_can_cold_reset(chip))
  2268. err = snd_intel8x0_ich_chip_cold_reset(chip);
  2269. else
  2270. err = snd_intel8x0_ich_chip_reset(chip);
  2271. if (err < 0)
  2272. return err;
  2273. if (probing) {
  2274. /* wait for any codec ready status.
  2275. * Once it becomes ready it should remain ready
  2276. * as long as we do not disable the ac97 link.
  2277. */
  2278. end_time = jiffies + HZ;
  2279. do {
  2280. status = igetdword(chip, ICHREG(GLOB_STA)) &
  2281. chip->codec_isr_bits;
  2282. if (status)
  2283. break;
  2284. schedule_timeout_uninterruptible(1);
  2285. } while (time_after_eq(end_time, jiffies));
  2286. if (! status) {
  2287. /* no codec is found */
  2288. dev_err(chip->card->dev,
  2289. "codec_ready: codec is not ready [0x%x]\n",
  2290. igetdword(chip, ICHREG(GLOB_STA)));
  2291. return -EIO;
  2292. }
  2293. /* wait for other codecs ready status. */
  2294. end_time = jiffies + HZ / 4;
  2295. while (status != chip->codec_isr_bits &&
  2296. time_after_eq(end_time, jiffies)) {
  2297. schedule_timeout_uninterruptible(1);
  2298. status |= igetdword(chip, ICHREG(GLOB_STA)) &
  2299. chip->codec_isr_bits;
  2300. }
  2301. } else {
  2302. /* resume phase */
  2303. int i;
  2304. status = 0;
  2305. for (i = 0; i < chip->ncodecs; i++)
  2306. if (chip->ac97[i])
  2307. status |= chip->codec_bit[chip->ac97_sdin[i]];
  2308. /* wait until all the probed codecs are ready */
  2309. end_time = jiffies + HZ;
  2310. do {
  2311. nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
  2312. chip->codec_isr_bits;
  2313. if (status == nstatus)
  2314. break;
  2315. schedule_timeout_uninterruptible(1);
  2316. } while (time_after_eq(end_time, jiffies));
  2317. }
  2318. if (chip->device_type == DEVICE_SIS) {
  2319. /* unmute the output on SIS7012 */
  2320. iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
  2321. }
  2322. if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
  2323. /* enable SPDIF interrupt */
  2324. unsigned int val;
  2325. pci_read_config_dword(chip->pci, 0x4c, &val);
  2326. val |= 0x1000000;
  2327. pci_write_config_dword(chip->pci, 0x4c, val);
  2328. }
  2329. return 0;
  2330. }
  2331. static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
  2332. {
  2333. u32 reg;
  2334. int i = 0;
  2335. reg = igetdword(chip, ICHREG(ALI_SCR));
  2336. if ((reg & 2) == 0) /* Cold required */
  2337. reg |= 2;
  2338. else
  2339. reg |= 1; /* Warm */
  2340. reg &= ~0x80000000; /* ACLink on */
  2341. iputdword(chip, ICHREG(ALI_SCR), reg);
  2342. for (i = 0; i < HZ / 2; i++) {
  2343. if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
  2344. goto __ok;
  2345. schedule_timeout_uninterruptible(1);
  2346. }
  2347. dev_err(chip->card->dev, "AC'97 reset failed.\n");
  2348. if (probing)
  2349. return -EIO;
  2350. __ok:
  2351. for (i = 0; i < HZ / 2; i++) {
  2352. reg = igetdword(chip, ICHREG(ALI_RTSR));
  2353. if (reg & 0x80) /* primary codec */
  2354. break;
  2355. iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
  2356. schedule_timeout_uninterruptible(1);
  2357. }
  2358. do_ali_reset(chip);
  2359. return 0;
  2360. }
  2361. static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
  2362. {
  2363. unsigned int i, timeout;
  2364. int err;
  2365. if (chip->device_type != DEVICE_ALI) {
  2366. if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
  2367. return err;
  2368. iagetword(chip, 0); /* clear semaphore flag */
  2369. } else {
  2370. if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
  2371. return err;
  2372. }
  2373. /* disable interrupts */
  2374. for (i = 0; i < chip->bdbars_count; i++)
  2375. iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
  2376. /* reset channels */
  2377. for (i = 0; i < chip->bdbars_count; i++)
  2378. iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
  2379. for (i = 0; i < chip->bdbars_count; i++) {
  2380. timeout = 100000;
  2381. while (--timeout != 0) {
  2382. if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
  2383. break;
  2384. }
  2385. if (timeout == 0)
  2386. dev_err(chip->card->dev, "reset of registers failed?\n");
  2387. }
  2388. /* initialize Buffer Descriptor Lists */
  2389. for (i = 0; i < chip->bdbars_count; i++)
  2390. iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
  2391. chip->ichd[i].bdbar_addr);
  2392. return 0;
  2393. }
  2394. static int snd_intel8x0_free(struct intel8x0 *chip)
  2395. {
  2396. unsigned int i;
  2397. if (chip->irq < 0)
  2398. goto __hw_end;
  2399. /* disable interrupts */
  2400. for (i = 0; i < chip->bdbars_count; i++)
  2401. iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
  2402. /* reset channels */
  2403. for (i = 0; i < chip->bdbars_count; i++)
  2404. iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
  2405. if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
  2406. /* stop the spdif interrupt */
  2407. unsigned int val;
  2408. pci_read_config_dword(chip->pci, 0x4c, &val);
  2409. val &= ~0x1000000;
  2410. pci_write_config_dword(chip->pci, 0x4c, val);
  2411. }
  2412. /* --- */
  2413. __hw_end:
  2414. if (chip->irq >= 0)
  2415. free_irq(chip->irq, chip);
  2416. if (chip->bdbars.area) {
  2417. if (chip->fix_nocache)
  2418. fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
  2419. snd_dma_free_pages(&chip->bdbars);
  2420. }
  2421. if (chip->addr)
  2422. pci_iounmap(chip->pci, chip->addr);
  2423. if (chip->bmaddr)
  2424. pci_iounmap(chip->pci, chip->bmaddr);
  2425. pci_release_regions(chip->pci);
  2426. pci_disable_device(chip->pci);
  2427. kfree(chip);
  2428. return 0;
  2429. }
  2430. #ifdef CONFIG_PM_SLEEP
  2431. /*
  2432. * power management
  2433. */
  2434. static int intel8x0_suspend(struct device *dev)
  2435. {
  2436. struct snd_card *card = dev_get_drvdata(dev);
  2437. struct intel8x0 *chip = card->private_data;
  2438. int i;
  2439. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  2440. for (i = 0; i < chip->pcm_devs; i++)
  2441. snd_pcm_suspend_all(chip->pcm[i]);
  2442. /* clear nocache */
  2443. if (chip->fix_nocache) {
  2444. for (i = 0; i < chip->bdbars_count; i++) {
  2445. struct ichdev *ichdev = &chip->ichd[i];
  2446. if (ichdev->substream && ichdev->page_attr_changed) {
  2447. struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
  2448. if (runtime->dma_area)
  2449. fill_nocache(runtime->dma_area, runtime->dma_bytes, 0);
  2450. }
  2451. }
  2452. }
  2453. for (i = 0; i < chip->ncodecs; i++)
  2454. snd_ac97_suspend(chip->ac97[i]);
  2455. if (chip->device_type == DEVICE_INTEL_ICH4)
  2456. chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
  2457. if (chip->irq >= 0) {
  2458. free_irq(chip->irq, chip);
  2459. chip->irq = -1;
  2460. }
  2461. return 0;
  2462. }
  2463. static int intel8x0_resume(struct device *dev)
  2464. {
  2465. struct pci_dev *pci = to_pci_dev(dev);
  2466. struct snd_card *card = dev_get_drvdata(dev);
  2467. struct intel8x0 *chip = card->private_data;
  2468. int i;
  2469. snd_intel8x0_chip_init(chip, 0);
  2470. if (request_irq(pci->irq, snd_intel8x0_interrupt,
  2471. IRQF_SHARED, KBUILD_MODNAME, chip)) {
  2472. dev_err(dev, "unable to grab IRQ %d, disabling device\n",
  2473. pci->irq);
  2474. snd_card_disconnect(card);
  2475. return -EIO;
  2476. }
  2477. chip->irq = pci->irq;
  2478. synchronize_irq(chip->irq);
  2479. /* re-initialize mixer stuff */
  2480. if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
  2481. /* enable separate SDINs for ICH4 */
  2482. iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
  2483. /* use slot 10/11 for SPDIF */
  2484. iputdword(chip, ICHREG(GLOB_CNT),
  2485. (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
  2486. ICH_PCM_SPDIF_1011);
  2487. }
  2488. /* refill nocache */
  2489. if (chip->fix_nocache)
  2490. fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
  2491. for (i = 0; i < chip->ncodecs; i++)
  2492. snd_ac97_resume(chip->ac97[i]);
  2493. /* refill nocache */
  2494. if (chip->fix_nocache) {
  2495. for (i = 0; i < chip->bdbars_count; i++) {
  2496. struct ichdev *ichdev = &chip->ichd[i];
  2497. if (ichdev->substream && ichdev->page_attr_changed) {
  2498. struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
  2499. if (runtime->dma_area)
  2500. fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
  2501. }
  2502. }
  2503. }
  2504. /* resume status */
  2505. for (i = 0; i < chip->bdbars_count; i++) {
  2506. struct ichdev *ichdev = &chip->ichd[i];
  2507. unsigned long port = ichdev->reg_offset;
  2508. if (! ichdev->substream || ! ichdev->suspended)
  2509. continue;
  2510. if (ichdev->ichd == ICHD_PCMOUT)
  2511. snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
  2512. iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
  2513. iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
  2514. iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
  2515. iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
  2516. }
  2517. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  2518. return 0;
  2519. }
  2520. static SIMPLE_DEV_PM_OPS(intel8x0_pm, intel8x0_suspend, intel8x0_resume);
  2521. #define INTEL8X0_PM_OPS &intel8x0_pm
  2522. #else
  2523. #define INTEL8X0_PM_OPS NULL
  2524. #endif /* CONFIG_PM_SLEEP */
  2525. #define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */
  2526. static void intel8x0_measure_ac97_clock(struct intel8x0 *chip)
  2527. {
  2528. struct snd_pcm_substream *subs;
  2529. struct ichdev *ichdev;
  2530. unsigned long port;
  2531. unsigned long pos, pos1, t;
  2532. int civ, timeout = 1000, attempt = 1;
  2533. ktime_t start_time, stop_time;
  2534. if (chip->ac97_bus->clock != 48000)
  2535. return; /* specified in module option */
  2536. __again:
  2537. subs = chip->pcm[0]->streams[0].substream;
  2538. if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
  2539. dev_warn(chip->card->dev,
  2540. "no playback buffer allocated - aborting measure ac97 clock\n");
  2541. return;
  2542. }
  2543. ichdev = &chip->ichd[ICHD_PCMOUT];
  2544. ichdev->physbuf = subs->dma_buffer.addr;
  2545. ichdev->size = ichdev->fragsize = INTEL8X0_TESTBUF_SIZE;
  2546. ichdev->substream = NULL; /* don't process interrupts */
  2547. /* set rate */
  2548. if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
  2549. dev_err(chip->card->dev, "cannot set ac97 rate: clock = %d\n",
  2550. chip->ac97_bus->clock);
  2551. return;
  2552. }
  2553. snd_intel8x0_setup_periods(chip, ichdev);
  2554. port = ichdev->reg_offset;
  2555. spin_lock_irq(&chip->reg_lock);
  2556. chip->in_measurement = 1;
  2557. /* trigger */
  2558. if (chip->device_type != DEVICE_ALI)
  2559. iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
  2560. else {
  2561. iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
  2562. iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
  2563. }
  2564. start_time = ktime_get();
  2565. spin_unlock_irq(&chip->reg_lock);
  2566. msleep(50);
  2567. spin_lock_irq(&chip->reg_lock);
  2568. /* check the position */
  2569. do {
  2570. civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
  2571. pos1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
  2572. if (pos1 == 0) {
  2573. udelay(10);
  2574. continue;
  2575. }
  2576. if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
  2577. pos1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
  2578. break;
  2579. } while (timeout--);
  2580. if (pos1 == 0) { /* oops, this value is not reliable */
  2581. pos = 0;
  2582. } else {
  2583. pos = ichdev->fragsize1;
  2584. pos -= pos1 << ichdev->pos_shift;
  2585. pos += ichdev->position;
  2586. }
  2587. chip->in_measurement = 0;
  2588. stop_time = ktime_get();
  2589. /* stop */
  2590. if (chip->device_type == DEVICE_ALI) {
  2591. iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
  2592. iputbyte(chip, port + ICH_REG_OFF_CR, 0);
  2593. while (igetbyte(chip, port + ICH_REG_OFF_CR))
  2594. ;
  2595. } else {
  2596. iputbyte(chip, port + ICH_REG_OFF_CR, 0);
  2597. while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
  2598. ;
  2599. }
  2600. iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
  2601. spin_unlock_irq(&chip->reg_lock);
  2602. if (pos == 0) {
  2603. dev_err(chip->card->dev,
  2604. "measure - unreliable DMA position..\n");
  2605. __retry:
  2606. if (attempt < 3) {
  2607. msleep(300);
  2608. attempt++;
  2609. goto __again;
  2610. }
  2611. goto __end;
  2612. }
  2613. pos /= 4;
  2614. t = ktime_us_delta(stop_time, start_time);
  2615. dev_info(chip->card->dev,
  2616. "%s: measured %lu usecs (%lu samples)\n", __func__, t, pos);
  2617. if (t == 0) {
  2618. dev_err(chip->card->dev, "?? calculation error..\n");
  2619. goto __retry;
  2620. }
  2621. pos *= 1000;
  2622. pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
  2623. if (pos < 40000 || pos >= 60000) {
  2624. /* abnormal value. hw problem? */
  2625. dev_info(chip->card->dev, "measured clock %ld rejected\n", pos);
  2626. goto __retry;
  2627. } else if (pos > 40500 && pos < 41500)
  2628. /* first exception - 41000Hz reference clock */
  2629. chip->ac97_bus->clock = 41000;
  2630. else if (pos > 43600 && pos < 44600)
  2631. /* second exception - 44100HZ reference clock */
  2632. chip->ac97_bus->clock = 44100;
  2633. else if (pos < 47500 || pos > 48500)
  2634. /* not 48000Hz, tuning the clock.. */
  2635. chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
  2636. __end:
  2637. dev_info(chip->card->dev, "clocking to %d\n", chip->ac97_bus->clock);
  2638. snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
  2639. }
  2640. static struct snd_pci_quirk intel8x0_clock_list[] = {
  2641. SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000),
  2642. SND_PCI_QUIRK(0x1014, 0x0581, "AD1981B", 48000),
  2643. SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100),
  2644. SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000),
  2645. SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000),
  2646. SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000),
  2647. { } /* terminator */
  2648. };
  2649. static int intel8x0_in_clock_list(struct intel8x0 *chip)
  2650. {
  2651. struct pci_dev *pci = chip->pci;
  2652. const struct snd_pci_quirk *wl;
  2653. wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list);
  2654. if (!wl)
  2655. return 0;
  2656. dev_info(chip->card->dev, "white list rate for %04x:%04x is %i\n",
  2657. pci->subsystem_vendor, pci->subsystem_device, wl->value);
  2658. chip->ac97_bus->clock = wl->value;
  2659. return 1;
  2660. }
  2661. static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
  2662. struct snd_info_buffer *buffer)
  2663. {
  2664. struct intel8x0 *chip = entry->private_data;
  2665. unsigned int tmp;
  2666. snd_iprintf(buffer, "Intel8x0\n\n");
  2667. if (chip->device_type == DEVICE_ALI)
  2668. return;
  2669. tmp = igetdword(chip, ICHREG(GLOB_STA));
  2670. snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
  2671. snd_iprintf(buffer, "Global status : 0x%08x\n", tmp);
  2672. if (chip->device_type == DEVICE_INTEL_ICH4)
  2673. snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
  2674. snd_iprintf(buffer, "AC'97 codecs ready :");
  2675. if (tmp & chip->codec_isr_bits) {
  2676. int i;
  2677. static const char *codecs[3] = {
  2678. "primary", "secondary", "tertiary"
  2679. };
  2680. for (i = 0; i < chip->max_codecs; i++)
  2681. if (tmp & chip->codec_bit[i])
  2682. snd_iprintf(buffer, " %s", codecs[i]);
  2683. } else
  2684. snd_iprintf(buffer, " none");
  2685. snd_iprintf(buffer, "\n");
  2686. if (chip->device_type == DEVICE_INTEL_ICH4 ||
  2687. chip->device_type == DEVICE_SIS)
  2688. snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n",
  2689. chip->ac97_sdin[0],
  2690. chip->ac97_sdin[1],
  2691. chip->ac97_sdin[2]);
  2692. }
  2693. static void snd_intel8x0_proc_init(struct intel8x0 *chip)
  2694. {
  2695. struct snd_info_entry *entry;
  2696. if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
  2697. snd_info_set_text_ops(entry, chip, snd_intel8x0_proc_read);
  2698. }
  2699. static int snd_intel8x0_dev_free(struct snd_device *device)
  2700. {
  2701. struct intel8x0 *chip = device->device_data;
  2702. return snd_intel8x0_free(chip);
  2703. }
  2704. struct ich_reg_info {
  2705. unsigned int int_sta_mask;
  2706. unsigned int offset;
  2707. };
  2708. static unsigned int ich_codec_bits[3] = {
  2709. ICH_PCR, ICH_SCR, ICH_TCR
  2710. };
  2711. static unsigned int sis_codec_bits[3] = {
  2712. ICH_PCR, ICH_SCR, ICH_SIS_TCR
  2713. };
  2714. static int snd_intel8x0_inside_vm(struct pci_dev *pci)
  2715. {
  2716. int result = inside_vm;
  2717. char *msg = NULL;
  2718. /* check module parameter first (override detection) */
  2719. if (result >= 0) {
  2720. msg = result ? "enable (forced) VM" : "disable (forced) VM";
  2721. goto fini;
  2722. }
  2723. /* detect KVM and Parallels virtual environments */
  2724. result = kvm_para_available();
  2725. #ifdef X86_FEATURE_HYPERVISOR
  2726. result = result || boot_cpu_has(X86_FEATURE_HYPERVISOR);
  2727. #endif
  2728. if (!result)
  2729. goto fini;
  2730. /* check for known (emulated) devices */
  2731. if (pci->subsystem_vendor == 0x1af4 &&
  2732. pci->subsystem_device == 0x1100) {
  2733. /* KVM emulated sound, PCI SSID: 1af4:1100 */
  2734. msg = "enable KVM";
  2735. } else if (pci->subsystem_vendor == 0x1ab8) {
  2736. /* Parallels VM emulated sound, PCI SSID: 1ab8:xxxx */
  2737. msg = "enable Parallels VM";
  2738. } else {
  2739. msg = "disable (unknown or VT-d) VM";
  2740. result = 0;
  2741. }
  2742. fini:
  2743. if (msg != NULL)
  2744. dev_info(&pci->dev, "%s optimization\n", msg);
  2745. return result;
  2746. }
  2747. static int snd_intel8x0_create(struct snd_card *card,
  2748. struct pci_dev *pci,
  2749. unsigned long device_type,
  2750. struct intel8x0 **r_intel8x0)
  2751. {
  2752. struct intel8x0 *chip;
  2753. int err;
  2754. unsigned int i;
  2755. unsigned int int_sta_masks;
  2756. struct ichdev *ichdev;
  2757. static struct snd_device_ops ops = {
  2758. .dev_free = snd_intel8x0_dev_free,
  2759. };
  2760. static unsigned int bdbars[] = {
  2761. 3, /* DEVICE_INTEL */
  2762. 6, /* DEVICE_INTEL_ICH4 */
  2763. 3, /* DEVICE_SIS */
  2764. 6, /* DEVICE_ALI */
  2765. 4, /* DEVICE_NFORCE */
  2766. };
  2767. static struct ich_reg_info intel_regs[6] = {
  2768. { ICH_PIINT, 0 },
  2769. { ICH_POINT, 0x10 },
  2770. { ICH_MCINT, 0x20 },
  2771. { ICH_M2INT, 0x40 },
  2772. { ICH_P2INT, 0x50 },
  2773. { ICH_SPINT, 0x60 },
  2774. };
  2775. static struct ich_reg_info nforce_regs[4] = {
  2776. { ICH_PIINT, 0 },
  2777. { ICH_POINT, 0x10 },
  2778. { ICH_MCINT, 0x20 },
  2779. { ICH_NVSPINT, 0x70 },
  2780. };
  2781. static struct ich_reg_info ali_regs[6] = {
  2782. { ALI_INT_PCMIN, 0x40 },
  2783. { ALI_INT_PCMOUT, 0x50 },
  2784. { ALI_INT_MICIN, 0x60 },
  2785. { ALI_INT_CODECSPDIFOUT, 0x70 },
  2786. { ALI_INT_SPDIFIN, 0xa0 },
  2787. { ALI_INT_SPDIFOUT, 0xb0 },
  2788. };
  2789. struct ich_reg_info *tbl;
  2790. *r_intel8x0 = NULL;
  2791. if ((err = pci_enable_device(pci)) < 0)
  2792. return err;
  2793. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  2794. if (chip == NULL) {
  2795. pci_disable_device(pci);
  2796. return -ENOMEM;
  2797. }
  2798. spin_lock_init(&chip->reg_lock);
  2799. chip->device_type = device_type;
  2800. chip->card = card;
  2801. chip->pci = pci;
  2802. chip->irq = -1;
  2803. /* module parameters */
  2804. chip->buggy_irq = buggy_irq;
  2805. chip->buggy_semaphore = buggy_semaphore;
  2806. if (xbox)
  2807. chip->xbox = 1;
  2808. chip->inside_vm = snd_intel8x0_inside_vm(pci);
  2809. if (pci->vendor == PCI_VENDOR_ID_INTEL &&
  2810. pci->device == PCI_DEVICE_ID_INTEL_440MX)
  2811. chip->fix_nocache = 1; /* enable workaround */
  2812. if ((err = pci_request_regions(pci, card->shortname)) < 0) {
  2813. kfree(chip);
  2814. pci_disable_device(pci);
  2815. return err;
  2816. }
  2817. if (device_type == DEVICE_ALI) {
  2818. /* ALI5455 has no ac97 region */
  2819. chip->bmaddr = pci_iomap(pci, 0, 0);
  2820. goto port_inited;
  2821. }
  2822. if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
  2823. chip->addr = pci_iomap(pci, 2, 0);
  2824. else
  2825. chip->addr = pci_iomap(pci, 0, 0);
  2826. if (!chip->addr) {
  2827. dev_err(card->dev, "AC'97 space ioremap problem\n");
  2828. snd_intel8x0_free(chip);
  2829. return -EIO;
  2830. }
  2831. if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
  2832. chip->bmaddr = pci_iomap(pci, 3, 0);
  2833. else
  2834. chip->bmaddr = pci_iomap(pci, 1, 0);
  2835. port_inited:
  2836. if (!chip->bmaddr) {
  2837. dev_err(card->dev, "Controller space ioremap problem\n");
  2838. snd_intel8x0_free(chip);
  2839. return -EIO;
  2840. }
  2841. chip->bdbars_count = bdbars[device_type];
  2842. /* initialize offsets */
  2843. switch (device_type) {
  2844. case DEVICE_NFORCE:
  2845. tbl = nforce_regs;
  2846. break;
  2847. case DEVICE_ALI:
  2848. tbl = ali_regs;
  2849. break;
  2850. default:
  2851. tbl = intel_regs;
  2852. break;
  2853. }
  2854. for (i = 0; i < chip->bdbars_count; i++) {
  2855. ichdev = &chip->ichd[i];
  2856. ichdev->ichd = i;
  2857. ichdev->reg_offset = tbl[i].offset;
  2858. ichdev->int_sta_mask = tbl[i].int_sta_mask;
  2859. if (device_type == DEVICE_SIS) {
  2860. /* SiS 7012 swaps the registers */
  2861. ichdev->roff_sr = ICH_REG_OFF_PICB;
  2862. ichdev->roff_picb = ICH_REG_OFF_SR;
  2863. } else {
  2864. ichdev->roff_sr = ICH_REG_OFF_SR;
  2865. ichdev->roff_picb = ICH_REG_OFF_PICB;
  2866. }
  2867. if (device_type == DEVICE_ALI)
  2868. ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
  2869. /* SIS7012 handles the pcm data in bytes, others are in samples */
  2870. ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
  2871. }
  2872. /* allocate buffer descriptor lists */
  2873. /* the start of each lists must be aligned to 8 bytes */
  2874. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
  2875. chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
  2876. &chip->bdbars) < 0) {
  2877. snd_intel8x0_free(chip);
  2878. dev_err(card->dev, "cannot allocate buffer descriptors\n");
  2879. return -ENOMEM;
  2880. }
  2881. /* tables must be aligned to 8 bytes here, but the kernel pages
  2882. are much bigger, so we don't care (on i386) */
  2883. /* workaround for 440MX */
  2884. if (chip->fix_nocache)
  2885. fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
  2886. int_sta_masks = 0;
  2887. for (i = 0; i < chip->bdbars_count; i++) {
  2888. ichdev = &chip->ichd[i];
  2889. ichdev->bdbar = ((u32 *)chip->bdbars.area) +
  2890. (i * ICH_MAX_FRAGS * 2);
  2891. ichdev->bdbar_addr = chip->bdbars.addr +
  2892. (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
  2893. int_sta_masks |= ichdev->int_sta_mask;
  2894. }
  2895. chip->int_sta_reg = device_type == DEVICE_ALI ?
  2896. ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
  2897. chip->int_sta_mask = int_sta_masks;
  2898. pci_set_master(pci);
  2899. switch(chip->device_type) {
  2900. case DEVICE_INTEL_ICH4:
  2901. /* ICH4 can have three codecs */
  2902. chip->max_codecs = 3;
  2903. chip->codec_bit = ich_codec_bits;
  2904. chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
  2905. break;
  2906. case DEVICE_SIS:
  2907. /* recent SIS7012 can have three codecs */
  2908. chip->max_codecs = 3;
  2909. chip->codec_bit = sis_codec_bits;
  2910. chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
  2911. break;
  2912. default:
  2913. /* others up to two codecs */
  2914. chip->max_codecs = 2;
  2915. chip->codec_bit = ich_codec_bits;
  2916. chip->codec_ready_bits = ICH_PRI | ICH_SRI;
  2917. break;
  2918. }
  2919. for (i = 0; i < chip->max_codecs; i++)
  2920. chip->codec_isr_bits |= chip->codec_bit[i];
  2921. if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
  2922. snd_intel8x0_free(chip);
  2923. return err;
  2924. }
  2925. /* request irq after initializaing int_sta_mask, etc */
  2926. if (request_irq(pci->irq, snd_intel8x0_interrupt,
  2927. IRQF_SHARED, KBUILD_MODNAME, chip)) {
  2928. dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
  2929. snd_intel8x0_free(chip);
  2930. return -EBUSY;
  2931. }
  2932. chip->irq = pci->irq;
  2933. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  2934. snd_intel8x0_free(chip);
  2935. return err;
  2936. }
  2937. *r_intel8x0 = chip;
  2938. return 0;
  2939. }
  2940. static struct shortname_table {
  2941. unsigned int id;
  2942. const char *s;
  2943. } shortnames[] = {
  2944. { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
  2945. { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
  2946. { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
  2947. { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
  2948. { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
  2949. { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
  2950. { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
  2951. { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
  2952. { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
  2953. { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
  2954. { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
  2955. { PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
  2956. { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
  2957. { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
  2958. { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
  2959. { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
  2960. { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
  2961. { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
  2962. { 0x003a, "NVidia MCP04" },
  2963. { 0x746d, "AMD AMD8111" },
  2964. { 0x7445, "AMD AMD768" },
  2965. { 0x5455, "ALi M5455" },
  2966. { 0, NULL },
  2967. };
  2968. static struct snd_pci_quirk spdif_aclink_defaults[] = {
  2969. SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1),
  2970. { } /* end */
  2971. };
  2972. /* look up white/black list for SPDIF over ac-link */
  2973. static int check_default_spdif_aclink(struct pci_dev *pci)
  2974. {
  2975. const struct snd_pci_quirk *w;
  2976. w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults);
  2977. if (w) {
  2978. if (w->value)
  2979. dev_dbg(&pci->dev,
  2980. "Using SPDIF over AC-Link for %s\n",
  2981. snd_pci_quirk_name(w));
  2982. else
  2983. dev_dbg(&pci->dev,
  2984. "Using integrated SPDIF DMA for %s\n",
  2985. snd_pci_quirk_name(w));
  2986. return w->value;
  2987. }
  2988. return 0;
  2989. }
  2990. static int snd_intel8x0_probe(struct pci_dev *pci,
  2991. const struct pci_device_id *pci_id)
  2992. {
  2993. struct snd_card *card;
  2994. struct intel8x0 *chip;
  2995. int err;
  2996. struct shortname_table *name;
  2997. err = snd_card_new(&pci->dev, index, id, THIS_MODULE, 0, &card);
  2998. if (err < 0)
  2999. return err;
  3000. if (spdif_aclink < 0)
  3001. spdif_aclink = check_default_spdif_aclink(pci);
  3002. strcpy(card->driver, "ICH");
  3003. if (!spdif_aclink) {
  3004. switch (pci_id->driver_data) {
  3005. case DEVICE_NFORCE:
  3006. strcpy(card->driver, "NFORCE");
  3007. break;
  3008. case DEVICE_INTEL_ICH4:
  3009. strcpy(card->driver, "ICH4");
  3010. }
  3011. }
  3012. strcpy(card->shortname, "Intel ICH");
  3013. for (name = shortnames; name->id; name++) {
  3014. if (pci->device == name->id) {
  3015. strcpy(card->shortname, name->s);
  3016. break;
  3017. }
  3018. }
  3019. if (buggy_irq < 0) {
  3020. /* some Nforce[2] and ICH boards have problems with IRQ handling.
  3021. * Needs to return IRQ_HANDLED for unknown irqs.
  3022. */
  3023. if (pci_id->driver_data == DEVICE_NFORCE)
  3024. buggy_irq = 1;
  3025. else
  3026. buggy_irq = 0;
  3027. }
  3028. if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
  3029. &chip)) < 0) {
  3030. snd_card_free(card);
  3031. return err;
  3032. }
  3033. card->private_data = chip;
  3034. if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) {
  3035. snd_card_free(card);
  3036. return err;
  3037. }
  3038. if ((err = snd_intel8x0_pcm(chip)) < 0) {
  3039. snd_card_free(card);
  3040. return err;
  3041. }
  3042. snd_intel8x0_proc_init(chip);
  3043. snprintf(card->longname, sizeof(card->longname),
  3044. "%s with %s at irq %i", card->shortname,
  3045. snd_ac97_get_short_name(chip->ac97[0]), chip->irq);
  3046. if (ac97_clock == 0 || ac97_clock == 1) {
  3047. if (ac97_clock == 0) {
  3048. if (intel8x0_in_clock_list(chip) == 0)
  3049. intel8x0_measure_ac97_clock(chip);
  3050. } else {
  3051. intel8x0_measure_ac97_clock(chip);
  3052. }
  3053. }
  3054. if ((err = snd_card_register(card)) < 0) {
  3055. snd_card_free(card);
  3056. return err;
  3057. }
  3058. pci_set_drvdata(pci, card);
  3059. return 0;
  3060. }
  3061. static void snd_intel8x0_remove(struct pci_dev *pci)
  3062. {
  3063. snd_card_free(pci_get_drvdata(pci));
  3064. }
  3065. static struct pci_driver intel8x0_driver = {
  3066. .name = KBUILD_MODNAME,
  3067. .id_table = snd_intel8x0_ids,
  3068. .probe = snd_intel8x0_probe,
  3069. .remove = snd_intel8x0_remove,
  3070. .driver = {
  3071. .pm = INTEL8X0_PM_OPS,
  3072. },
  3073. };
  3074. module_pci_driver(intel8x0_driver);