nm256.c 45 KB

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  1. /*
  2. * Driver for NeoMagic 256AV and 256ZX chipsets.
  3. * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
  4. *
  5. * Based on nm256_audio.c OSS driver in linux kernel.
  6. * The original author of OSS nm256 driver wishes to remain anonymous,
  7. * so I just put my acknoledgment to him/her here.
  8. * The original author's web page is found at
  9. * http://www.uglx.org/sony.html
  10. *
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License as published by
  14. * the Free Software Foundation; either version 2 of the License, or
  15. * (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  25. */
  26. #include <linux/io.h>
  27. #include <linux/delay.h>
  28. #include <linux/interrupt.h>
  29. #include <linux/init.h>
  30. #include <linux/pci.h>
  31. #include <linux/slab.h>
  32. #include <linux/module.h>
  33. #include <linux/mutex.h>
  34. #include <sound/core.h>
  35. #include <sound/info.h>
  36. #include <sound/control.h>
  37. #include <sound/pcm.h>
  38. #include <sound/ac97_codec.h>
  39. #include <sound/initval.h>
  40. #define CARD_NAME "NeoMagic 256AV/ZX"
  41. #define DRIVER_NAME "NM256"
  42. MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
  43. MODULE_DESCRIPTION("NeoMagic NM256AV/ZX");
  44. MODULE_LICENSE("GPL");
  45. MODULE_SUPPORTED_DEVICE("{{NeoMagic,NM256AV},"
  46. "{NeoMagic,NM256ZX}}");
  47. /*
  48. * some compile conditions.
  49. */
  50. static int index = SNDRV_DEFAULT_IDX1; /* Index */
  51. static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */
  52. static int playback_bufsize = 16;
  53. static int capture_bufsize = 16;
  54. static bool force_ac97; /* disabled as default */
  55. static int buffer_top; /* not specified */
  56. static bool use_cache; /* disabled */
  57. static bool vaio_hack; /* disabled */
  58. static bool reset_workaround;
  59. static bool reset_workaround_2;
  60. module_param(index, int, 0444);
  61. MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
  62. module_param(id, charp, 0444);
  63. MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
  64. module_param(playback_bufsize, int, 0444);
  65. MODULE_PARM_DESC(playback_bufsize, "DAC frame size in kB for " CARD_NAME " soundcard.");
  66. module_param(capture_bufsize, int, 0444);
  67. MODULE_PARM_DESC(capture_bufsize, "ADC frame size in kB for " CARD_NAME " soundcard.");
  68. module_param(force_ac97, bool, 0444);
  69. MODULE_PARM_DESC(force_ac97, "Force to use AC97 codec for " CARD_NAME " soundcard.");
  70. module_param(buffer_top, int, 0444);
  71. MODULE_PARM_DESC(buffer_top, "Set the top address of audio buffer for " CARD_NAME " soundcard.");
  72. module_param(use_cache, bool, 0444);
  73. MODULE_PARM_DESC(use_cache, "Enable the cache for coefficient table access.");
  74. module_param(vaio_hack, bool, 0444);
  75. MODULE_PARM_DESC(vaio_hack, "Enable workaround for Sony VAIO notebooks.");
  76. module_param(reset_workaround, bool, 0444);
  77. MODULE_PARM_DESC(reset_workaround, "Enable AC97 RESET workaround for some laptops.");
  78. module_param(reset_workaround_2, bool, 0444);
  79. MODULE_PARM_DESC(reset_workaround_2, "Enable extended AC97 RESET workaround for some other laptops.");
  80. /* just for backward compatibility */
  81. static bool enable;
  82. module_param(enable, bool, 0444);
  83. /*
  84. * hw definitions
  85. */
  86. /* The BIOS signature. */
  87. #define NM_SIGNATURE 0x4e4d0000
  88. /* Signature mask. */
  89. #define NM_SIG_MASK 0xffff0000
  90. /* Size of the second memory area. */
  91. #define NM_PORT2_SIZE 4096
  92. /* The base offset of the mixer in the second memory area. */
  93. #define NM_MIXER_OFFSET 0x600
  94. /* The maximum size of a coefficient entry. */
  95. #define NM_MAX_PLAYBACK_COEF_SIZE 0x5000
  96. #define NM_MAX_RECORD_COEF_SIZE 0x1260
  97. /* The interrupt register. */
  98. #define NM_INT_REG 0xa04
  99. /* And its bits. */
  100. #define NM_PLAYBACK_INT 0x40
  101. #define NM_RECORD_INT 0x100
  102. #define NM_MISC_INT_1 0x4000
  103. #define NM_MISC_INT_2 0x1
  104. #define NM_ACK_INT(chip, X) snd_nm256_writew(chip, NM_INT_REG, (X) << 1)
  105. /* The AV's "mixer ready" status bit and location. */
  106. #define NM_MIXER_STATUS_OFFSET 0xa04
  107. #define NM_MIXER_READY_MASK 0x0800
  108. #define NM_MIXER_PRESENCE 0xa06
  109. #define NM_PRESENCE_MASK 0x0050
  110. #define NM_PRESENCE_VALUE 0x0040
  111. /*
  112. * For the ZX. It uses the same interrupt register, but it holds 32
  113. * bits instead of 16.
  114. */
  115. #define NM2_PLAYBACK_INT 0x10000
  116. #define NM2_RECORD_INT 0x80000
  117. #define NM2_MISC_INT_1 0x8
  118. #define NM2_MISC_INT_2 0x2
  119. #define NM2_ACK_INT(chip, X) snd_nm256_writel(chip, NM_INT_REG, (X))
  120. /* The ZX's "mixer ready" status bit and location. */
  121. #define NM2_MIXER_STATUS_OFFSET 0xa06
  122. #define NM2_MIXER_READY_MASK 0x0800
  123. /* The playback registers start from here. */
  124. #define NM_PLAYBACK_REG_OFFSET 0x0
  125. /* The record registers start from here. */
  126. #define NM_RECORD_REG_OFFSET 0x200
  127. /* The rate register is located 2 bytes from the start of the register area. */
  128. #define NM_RATE_REG_OFFSET 2
  129. /* Mono/stereo flag, number of bits on playback, and rate mask. */
  130. #define NM_RATE_STEREO 1
  131. #define NM_RATE_BITS_16 2
  132. #define NM_RATE_MASK 0xf0
  133. /* Playback enable register. */
  134. #define NM_PLAYBACK_ENABLE_REG (NM_PLAYBACK_REG_OFFSET + 0x1)
  135. #define NM_PLAYBACK_ENABLE_FLAG 1
  136. #define NM_PLAYBACK_ONESHOT 2
  137. #define NM_PLAYBACK_FREERUN 4
  138. /* Mutes the audio output. */
  139. #define NM_AUDIO_MUTE_REG (NM_PLAYBACK_REG_OFFSET + 0x18)
  140. #define NM_AUDIO_MUTE_LEFT 0x8000
  141. #define NM_AUDIO_MUTE_RIGHT 0x0080
  142. /* Recording enable register. */
  143. #define NM_RECORD_ENABLE_REG (NM_RECORD_REG_OFFSET + 0)
  144. #define NM_RECORD_ENABLE_FLAG 1
  145. #define NM_RECORD_FREERUN 2
  146. /* coefficient buffer pointer */
  147. #define NM_COEFF_START_OFFSET 0x1c
  148. #define NM_COEFF_END_OFFSET 0x20
  149. /* DMA buffer offsets */
  150. #define NM_RBUFFER_START (NM_RECORD_REG_OFFSET + 0x4)
  151. #define NM_RBUFFER_END (NM_RECORD_REG_OFFSET + 0x10)
  152. #define NM_RBUFFER_WMARK (NM_RECORD_REG_OFFSET + 0xc)
  153. #define NM_RBUFFER_CURRP (NM_RECORD_REG_OFFSET + 0x8)
  154. #define NM_PBUFFER_START (NM_PLAYBACK_REG_OFFSET + 0x4)
  155. #define NM_PBUFFER_END (NM_PLAYBACK_REG_OFFSET + 0x14)
  156. #define NM_PBUFFER_WMARK (NM_PLAYBACK_REG_OFFSET + 0xc)
  157. #define NM_PBUFFER_CURRP (NM_PLAYBACK_REG_OFFSET + 0x8)
  158. struct nm256_stream {
  159. struct nm256 *chip;
  160. struct snd_pcm_substream *substream;
  161. int running;
  162. int suspended;
  163. u32 buf; /* offset from chip->buffer */
  164. int bufsize; /* buffer size in bytes */
  165. void __iomem *bufptr; /* mapped pointer */
  166. unsigned long bufptr_addr; /* physical address of the mapped pointer */
  167. int dma_size; /* buffer size of the substream in bytes */
  168. int period_size; /* period size in bytes */
  169. int periods; /* # of periods */
  170. int shift; /* bit shifts */
  171. int cur_period; /* current period # */
  172. };
  173. struct nm256 {
  174. struct snd_card *card;
  175. void __iomem *cport; /* control port */
  176. struct resource *res_cport; /* its resource */
  177. unsigned long cport_addr; /* physical address */
  178. void __iomem *buffer; /* buffer */
  179. struct resource *res_buffer; /* its resource */
  180. unsigned long buffer_addr; /* buffer phyiscal address */
  181. u32 buffer_start; /* start offset from pci resource 0 */
  182. u32 buffer_end; /* end offset */
  183. u32 buffer_size; /* total buffer size */
  184. u32 all_coeff_buf; /* coefficient buffer */
  185. u32 coeff_buf[2]; /* coefficient buffer for each stream */
  186. unsigned int coeffs_current: 1; /* coeff. table is loaded? */
  187. unsigned int use_cache: 1; /* use one big coef. table */
  188. unsigned int reset_workaround: 1; /* Workaround for some laptops to avoid freeze */
  189. unsigned int reset_workaround_2: 1; /* Extended workaround for some other laptops to avoid freeze */
  190. unsigned int in_resume: 1;
  191. int mixer_base; /* register offset of ac97 mixer */
  192. int mixer_status_offset; /* offset of mixer status reg. */
  193. int mixer_status_mask; /* bit mask to test the mixer status */
  194. int irq;
  195. int irq_acks;
  196. irq_handler_t interrupt;
  197. int badintrcount; /* counter to check bogus interrupts */
  198. struct mutex irq_mutex;
  199. struct nm256_stream streams[2];
  200. struct snd_ac97 *ac97;
  201. unsigned short *ac97_regs; /* register caches, only for valid regs */
  202. struct snd_pcm *pcm;
  203. struct pci_dev *pci;
  204. spinlock_t reg_lock;
  205. };
  206. /*
  207. * include coefficient table
  208. */
  209. #include "nm256_coef.c"
  210. /*
  211. * PCI ids
  212. */
  213. static const struct pci_device_id snd_nm256_ids[] = {
  214. {PCI_VDEVICE(NEOMAGIC, PCI_DEVICE_ID_NEOMAGIC_NM256AV_AUDIO), 0},
  215. {PCI_VDEVICE(NEOMAGIC, PCI_DEVICE_ID_NEOMAGIC_NM256ZX_AUDIO), 0},
  216. {PCI_VDEVICE(NEOMAGIC, PCI_DEVICE_ID_NEOMAGIC_NM256XL_PLUS_AUDIO), 0},
  217. {0,},
  218. };
  219. MODULE_DEVICE_TABLE(pci, snd_nm256_ids);
  220. /*
  221. * lowlvel stuffs
  222. */
  223. static inline u8
  224. snd_nm256_readb(struct nm256 *chip, int offset)
  225. {
  226. return readb(chip->cport + offset);
  227. }
  228. static inline u16
  229. snd_nm256_readw(struct nm256 *chip, int offset)
  230. {
  231. return readw(chip->cport + offset);
  232. }
  233. static inline u32
  234. snd_nm256_readl(struct nm256 *chip, int offset)
  235. {
  236. return readl(chip->cport + offset);
  237. }
  238. static inline void
  239. snd_nm256_writeb(struct nm256 *chip, int offset, u8 val)
  240. {
  241. writeb(val, chip->cport + offset);
  242. }
  243. static inline void
  244. snd_nm256_writew(struct nm256 *chip, int offset, u16 val)
  245. {
  246. writew(val, chip->cport + offset);
  247. }
  248. static inline void
  249. snd_nm256_writel(struct nm256 *chip, int offset, u32 val)
  250. {
  251. writel(val, chip->cport + offset);
  252. }
  253. static inline void
  254. snd_nm256_write_buffer(struct nm256 *chip, void *src, int offset, int size)
  255. {
  256. offset -= chip->buffer_start;
  257. #ifdef CONFIG_SND_DEBUG
  258. if (offset < 0 || offset >= chip->buffer_size) {
  259. dev_err(chip->card->dev,
  260. "write_buffer invalid offset = %d size = %d\n",
  261. offset, size);
  262. return;
  263. }
  264. #endif
  265. memcpy_toio(chip->buffer + offset, src, size);
  266. }
  267. /*
  268. * coefficient handlers -- what a magic!
  269. */
  270. static u16
  271. snd_nm256_get_start_offset(int which)
  272. {
  273. u16 offset = 0;
  274. while (which-- > 0)
  275. offset += coefficient_sizes[which];
  276. return offset;
  277. }
  278. static void
  279. snd_nm256_load_one_coefficient(struct nm256 *chip, int stream, u32 port, int which)
  280. {
  281. u32 coeff_buf = chip->coeff_buf[stream];
  282. u16 offset = snd_nm256_get_start_offset(which);
  283. u16 size = coefficient_sizes[which];
  284. snd_nm256_write_buffer(chip, coefficients + offset, coeff_buf, size);
  285. snd_nm256_writel(chip, port, coeff_buf);
  286. /* ??? Record seems to behave differently than playback. */
  287. if (stream == SNDRV_PCM_STREAM_PLAYBACK)
  288. size--;
  289. snd_nm256_writel(chip, port + 4, coeff_buf + size);
  290. }
  291. static void
  292. snd_nm256_load_coefficient(struct nm256 *chip, int stream, int number)
  293. {
  294. /* The enable register for the specified engine. */
  295. u32 poffset = (stream == SNDRV_PCM_STREAM_CAPTURE ?
  296. NM_RECORD_ENABLE_REG : NM_PLAYBACK_ENABLE_REG);
  297. u32 addr = NM_COEFF_START_OFFSET;
  298. addr += (stream == SNDRV_PCM_STREAM_CAPTURE ?
  299. NM_RECORD_REG_OFFSET : NM_PLAYBACK_REG_OFFSET);
  300. if (snd_nm256_readb(chip, poffset) & 1) {
  301. dev_dbg(chip->card->dev,
  302. "NM256: Engine was enabled while loading coefficients!\n");
  303. return;
  304. }
  305. /* The recording engine uses coefficient values 8-15. */
  306. number &= 7;
  307. if (stream == SNDRV_PCM_STREAM_CAPTURE)
  308. number += 8;
  309. if (! chip->use_cache) {
  310. snd_nm256_load_one_coefficient(chip, stream, addr, number);
  311. return;
  312. }
  313. if (! chip->coeffs_current) {
  314. snd_nm256_write_buffer(chip, coefficients, chip->all_coeff_buf,
  315. NM_TOTAL_COEFF_COUNT * 4);
  316. chip->coeffs_current = 1;
  317. } else {
  318. u32 base = chip->all_coeff_buf;
  319. u32 offset = snd_nm256_get_start_offset(number);
  320. u32 end_offset = offset + coefficient_sizes[number];
  321. snd_nm256_writel(chip, addr, base + offset);
  322. if (stream == SNDRV_PCM_STREAM_PLAYBACK)
  323. end_offset--;
  324. snd_nm256_writel(chip, addr + 4, base + end_offset);
  325. }
  326. }
  327. /* The actual rates supported by the card. */
  328. static unsigned int samplerates[8] = {
  329. 8000, 11025, 16000, 22050, 24000, 32000, 44100, 48000,
  330. };
  331. static struct snd_pcm_hw_constraint_list constraints_rates = {
  332. .count = ARRAY_SIZE(samplerates),
  333. .list = samplerates,
  334. .mask = 0,
  335. };
  336. /*
  337. * return the index of the target rate
  338. */
  339. static int
  340. snd_nm256_fixed_rate(unsigned int rate)
  341. {
  342. unsigned int i;
  343. for (i = 0; i < ARRAY_SIZE(samplerates); i++) {
  344. if (rate == samplerates[i])
  345. return i;
  346. }
  347. snd_BUG();
  348. return 0;
  349. }
  350. /*
  351. * set sample rate and format
  352. */
  353. static void
  354. snd_nm256_set_format(struct nm256 *chip, struct nm256_stream *s,
  355. struct snd_pcm_substream *substream)
  356. {
  357. struct snd_pcm_runtime *runtime = substream->runtime;
  358. int rate_index = snd_nm256_fixed_rate(runtime->rate);
  359. unsigned char ratebits = (rate_index << 4) & NM_RATE_MASK;
  360. s->shift = 0;
  361. if (snd_pcm_format_width(runtime->format) == 16) {
  362. ratebits |= NM_RATE_BITS_16;
  363. s->shift++;
  364. }
  365. if (runtime->channels > 1) {
  366. ratebits |= NM_RATE_STEREO;
  367. s->shift++;
  368. }
  369. runtime->rate = samplerates[rate_index];
  370. switch (substream->stream) {
  371. case SNDRV_PCM_STREAM_PLAYBACK:
  372. snd_nm256_load_coefficient(chip, 0, rate_index); /* 0 = playback */
  373. snd_nm256_writeb(chip,
  374. NM_PLAYBACK_REG_OFFSET + NM_RATE_REG_OFFSET,
  375. ratebits);
  376. break;
  377. case SNDRV_PCM_STREAM_CAPTURE:
  378. snd_nm256_load_coefficient(chip, 1, rate_index); /* 1 = record */
  379. snd_nm256_writeb(chip,
  380. NM_RECORD_REG_OFFSET + NM_RATE_REG_OFFSET,
  381. ratebits);
  382. break;
  383. }
  384. }
  385. /* acquire interrupt */
  386. static int snd_nm256_acquire_irq(struct nm256 *chip)
  387. {
  388. mutex_lock(&chip->irq_mutex);
  389. if (chip->irq < 0) {
  390. if (request_irq(chip->pci->irq, chip->interrupt, IRQF_SHARED,
  391. KBUILD_MODNAME, chip)) {
  392. dev_err(chip->card->dev,
  393. "unable to grab IRQ %d\n", chip->pci->irq);
  394. mutex_unlock(&chip->irq_mutex);
  395. return -EBUSY;
  396. }
  397. chip->irq = chip->pci->irq;
  398. }
  399. chip->irq_acks++;
  400. mutex_unlock(&chip->irq_mutex);
  401. return 0;
  402. }
  403. /* release interrupt */
  404. static void snd_nm256_release_irq(struct nm256 *chip)
  405. {
  406. mutex_lock(&chip->irq_mutex);
  407. if (chip->irq_acks > 0)
  408. chip->irq_acks--;
  409. if (chip->irq_acks == 0 && chip->irq >= 0) {
  410. free_irq(chip->irq, chip);
  411. chip->irq = -1;
  412. }
  413. mutex_unlock(&chip->irq_mutex);
  414. }
  415. /*
  416. * start / stop
  417. */
  418. /* update the watermark (current period) */
  419. static void snd_nm256_pcm_mark(struct nm256 *chip, struct nm256_stream *s, int reg)
  420. {
  421. s->cur_period++;
  422. s->cur_period %= s->periods;
  423. snd_nm256_writel(chip, reg, s->buf + s->cur_period * s->period_size);
  424. }
  425. #define snd_nm256_playback_mark(chip, s) snd_nm256_pcm_mark(chip, s, NM_PBUFFER_WMARK)
  426. #define snd_nm256_capture_mark(chip, s) snd_nm256_pcm_mark(chip, s, NM_RBUFFER_WMARK)
  427. static void
  428. snd_nm256_playback_start(struct nm256 *chip, struct nm256_stream *s,
  429. struct snd_pcm_substream *substream)
  430. {
  431. /* program buffer pointers */
  432. snd_nm256_writel(chip, NM_PBUFFER_START, s->buf);
  433. snd_nm256_writel(chip, NM_PBUFFER_END, s->buf + s->dma_size - (1 << s->shift));
  434. snd_nm256_writel(chip, NM_PBUFFER_CURRP, s->buf);
  435. snd_nm256_playback_mark(chip, s);
  436. /* Enable playback engine and interrupts. */
  437. snd_nm256_writeb(chip, NM_PLAYBACK_ENABLE_REG,
  438. NM_PLAYBACK_ENABLE_FLAG | NM_PLAYBACK_FREERUN);
  439. /* Enable both channels. */
  440. snd_nm256_writew(chip, NM_AUDIO_MUTE_REG, 0x0);
  441. }
  442. static void
  443. snd_nm256_capture_start(struct nm256 *chip, struct nm256_stream *s,
  444. struct snd_pcm_substream *substream)
  445. {
  446. /* program buffer pointers */
  447. snd_nm256_writel(chip, NM_RBUFFER_START, s->buf);
  448. snd_nm256_writel(chip, NM_RBUFFER_END, s->buf + s->dma_size);
  449. snd_nm256_writel(chip, NM_RBUFFER_CURRP, s->buf);
  450. snd_nm256_capture_mark(chip, s);
  451. /* Enable playback engine and interrupts. */
  452. snd_nm256_writeb(chip, NM_RECORD_ENABLE_REG,
  453. NM_RECORD_ENABLE_FLAG | NM_RECORD_FREERUN);
  454. }
  455. /* Stop the play engine. */
  456. static void
  457. snd_nm256_playback_stop(struct nm256 *chip)
  458. {
  459. /* Shut off sound from both channels. */
  460. snd_nm256_writew(chip, NM_AUDIO_MUTE_REG,
  461. NM_AUDIO_MUTE_LEFT | NM_AUDIO_MUTE_RIGHT);
  462. /* Disable play engine. */
  463. snd_nm256_writeb(chip, NM_PLAYBACK_ENABLE_REG, 0);
  464. }
  465. static void
  466. snd_nm256_capture_stop(struct nm256 *chip)
  467. {
  468. /* Disable recording engine. */
  469. snd_nm256_writeb(chip, NM_RECORD_ENABLE_REG, 0);
  470. }
  471. static int
  472. snd_nm256_playback_trigger(struct snd_pcm_substream *substream, int cmd)
  473. {
  474. struct nm256 *chip = snd_pcm_substream_chip(substream);
  475. struct nm256_stream *s = substream->runtime->private_data;
  476. int err = 0;
  477. if (snd_BUG_ON(!s))
  478. return -ENXIO;
  479. spin_lock(&chip->reg_lock);
  480. switch (cmd) {
  481. case SNDRV_PCM_TRIGGER_RESUME:
  482. s->suspended = 0;
  483. /* fallthru */
  484. case SNDRV_PCM_TRIGGER_START:
  485. if (! s->running) {
  486. snd_nm256_playback_start(chip, s, substream);
  487. s->running = 1;
  488. }
  489. break;
  490. case SNDRV_PCM_TRIGGER_SUSPEND:
  491. s->suspended = 1;
  492. /* fallthru */
  493. case SNDRV_PCM_TRIGGER_STOP:
  494. if (s->running) {
  495. snd_nm256_playback_stop(chip);
  496. s->running = 0;
  497. }
  498. break;
  499. default:
  500. err = -EINVAL;
  501. break;
  502. }
  503. spin_unlock(&chip->reg_lock);
  504. return err;
  505. }
  506. static int
  507. snd_nm256_capture_trigger(struct snd_pcm_substream *substream, int cmd)
  508. {
  509. struct nm256 *chip = snd_pcm_substream_chip(substream);
  510. struct nm256_stream *s = substream->runtime->private_data;
  511. int err = 0;
  512. if (snd_BUG_ON(!s))
  513. return -ENXIO;
  514. spin_lock(&chip->reg_lock);
  515. switch (cmd) {
  516. case SNDRV_PCM_TRIGGER_START:
  517. case SNDRV_PCM_TRIGGER_RESUME:
  518. if (! s->running) {
  519. snd_nm256_capture_start(chip, s, substream);
  520. s->running = 1;
  521. }
  522. break;
  523. case SNDRV_PCM_TRIGGER_STOP:
  524. case SNDRV_PCM_TRIGGER_SUSPEND:
  525. if (s->running) {
  526. snd_nm256_capture_stop(chip);
  527. s->running = 0;
  528. }
  529. break;
  530. default:
  531. err = -EINVAL;
  532. break;
  533. }
  534. spin_unlock(&chip->reg_lock);
  535. return err;
  536. }
  537. /*
  538. * prepare playback/capture channel
  539. */
  540. static int snd_nm256_pcm_prepare(struct snd_pcm_substream *substream)
  541. {
  542. struct nm256 *chip = snd_pcm_substream_chip(substream);
  543. struct snd_pcm_runtime *runtime = substream->runtime;
  544. struct nm256_stream *s = runtime->private_data;
  545. if (snd_BUG_ON(!s))
  546. return -ENXIO;
  547. s->dma_size = frames_to_bytes(runtime, substream->runtime->buffer_size);
  548. s->period_size = frames_to_bytes(runtime, substream->runtime->period_size);
  549. s->periods = substream->runtime->periods;
  550. s->cur_period = 0;
  551. spin_lock_irq(&chip->reg_lock);
  552. s->running = 0;
  553. snd_nm256_set_format(chip, s, substream);
  554. spin_unlock_irq(&chip->reg_lock);
  555. return 0;
  556. }
  557. /*
  558. * get the current pointer
  559. */
  560. static snd_pcm_uframes_t
  561. snd_nm256_playback_pointer(struct snd_pcm_substream *substream)
  562. {
  563. struct nm256 *chip = snd_pcm_substream_chip(substream);
  564. struct nm256_stream *s = substream->runtime->private_data;
  565. unsigned long curp;
  566. if (snd_BUG_ON(!s))
  567. return 0;
  568. curp = snd_nm256_readl(chip, NM_PBUFFER_CURRP) - (unsigned long)s->buf;
  569. curp %= s->dma_size;
  570. return bytes_to_frames(substream->runtime, curp);
  571. }
  572. static snd_pcm_uframes_t
  573. snd_nm256_capture_pointer(struct snd_pcm_substream *substream)
  574. {
  575. struct nm256 *chip = snd_pcm_substream_chip(substream);
  576. struct nm256_stream *s = substream->runtime->private_data;
  577. unsigned long curp;
  578. if (snd_BUG_ON(!s))
  579. return 0;
  580. curp = snd_nm256_readl(chip, NM_RBUFFER_CURRP) - (unsigned long)s->buf;
  581. curp %= s->dma_size;
  582. return bytes_to_frames(substream->runtime, curp);
  583. }
  584. /* Remapped I/O space can be accessible as pointer on i386 */
  585. /* This might be changed in the future */
  586. #ifndef __i386__
  587. /*
  588. * silence / copy for playback
  589. */
  590. static int
  591. snd_nm256_playback_silence(struct snd_pcm_substream *substream,
  592. int channel, /* not used (interleaved data) */
  593. snd_pcm_uframes_t pos,
  594. snd_pcm_uframes_t count)
  595. {
  596. struct snd_pcm_runtime *runtime = substream->runtime;
  597. struct nm256_stream *s = runtime->private_data;
  598. count = frames_to_bytes(runtime, count);
  599. pos = frames_to_bytes(runtime, pos);
  600. memset_io(s->bufptr + pos, 0, count);
  601. return 0;
  602. }
  603. static int
  604. snd_nm256_playback_copy(struct snd_pcm_substream *substream,
  605. int channel, /* not used (interleaved data) */
  606. snd_pcm_uframes_t pos,
  607. void __user *src,
  608. snd_pcm_uframes_t count)
  609. {
  610. struct snd_pcm_runtime *runtime = substream->runtime;
  611. struct nm256_stream *s = runtime->private_data;
  612. count = frames_to_bytes(runtime, count);
  613. pos = frames_to_bytes(runtime, pos);
  614. if (copy_from_user_toio(s->bufptr + pos, src, count))
  615. return -EFAULT;
  616. return 0;
  617. }
  618. /*
  619. * copy to user
  620. */
  621. static int
  622. snd_nm256_capture_copy(struct snd_pcm_substream *substream,
  623. int channel, /* not used (interleaved data) */
  624. snd_pcm_uframes_t pos,
  625. void __user *dst,
  626. snd_pcm_uframes_t count)
  627. {
  628. struct snd_pcm_runtime *runtime = substream->runtime;
  629. struct nm256_stream *s = runtime->private_data;
  630. count = frames_to_bytes(runtime, count);
  631. pos = frames_to_bytes(runtime, pos);
  632. if (copy_to_user_fromio(dst, s->bufptr + pos, count))
  633. return -EFAULT;
  634. return 0;
  635. }
  636. #endif /* !__i386__ */
  637. /*
  638. * update playback/capture watermarks
  639. */
  640. /* spinlock held! */
  641. static void
  642. snd_nm256_playback_update(struct nm256 *chip)
  643. {
  644. struct nm256_stream *s;
  645. s = &chip->streams[SNDRV_PCM_STREAM_PLAYBACK];
  646. if (s->running && s->substream) {
  647. spin_unlock(&chip->reg_lock);
  648. snd_pcm_period_elapsed(s->substream);
  649. spin_lock(&chip->reg_lock);
  650. snd_nm256_playback_mark(chip, s);
  651. }
  652. }
  653. /* spinlock held! */
  654. static void
  655. snd_nm256_capture_update(struct nm256 *chip)
  656. {
  657. struct nm256_stream *s;
  658. s = &chip->streams[SNDRV_PCM_STREAM_CAPTURE];
  659. if (s->running && s->substream) {
  660. spin_unlock(&chip->reg_lock);
  661. snd_pcm_period_elapsed(s->substream);
  662. spin_lock(&chip->reg_lock);
  663. snd_nm256_capture_mark(chip, s);
  664. }
  665. }
  666. /*
  667. * hardware info
  668. */
  669. static struct snd_pcm_hardware snd_nm256_playback =
  670. {
  671. .info = SNDRV_PCM_INFO_MMAP_IOMEM |SNDRV_PCM_INFO_MMAP_VALID |
  672. SNDRV_PCM_INFO_INTERLEAVED |
  673. /*SNDRV_PCM_INFO_PAUSE |*/
  674. SNDRV_PCM_INFO_RESUME,
  675. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  676. .rates = SNDRV_PCM_RATE_KNOT/*24k*/ | SNDRV_PCM_RATE_8000_48000,
  677. .rate_min = 8000,
  678. .rate_max = 48000,
  679. .channels_min = 1,
  680. .channels_max = 2,
  681. .periods_min = 2,
  682. .periods_max = 1024,
  683. .buffer_bytes_max = 128 * 1024,
  684. .period_bytes_min = 256,
  685. .period_bytes_max = 128 * 1024,
  686. };
  687. static struct snd_pcm_hardware snd_nm256_capture =
  688. {
  689. .info = SNDRV_PCM_INFO_MMAP_IOMEM | SNDRV_PCM_INFO_MMAP_VALID |
  690. SNDRV_PCM_INFO_INTERLEAVED |
  691. /*SNDRV_PCM_INFO_PAUSE |*/
  692. SNDRV_PCM_INFO_RESUME,
  693. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  694. .rates = SNDRV_PCM_RATE_KNOT/*24k*/ | SNDRV_PCM_RATE_8000_48000,
  695. .rate_min = 8000,
  696. .rate_max = 48000,
  697. .channels_min = 1,
  698. .channels_max = 2,
  699. .periods_min = 2,
  700. .periods_max = 1024,
  701. .buffer_bytes_max = 128 * 1024,
  702. .period_bytes_min = 256,
  703. .period_bytes_max = 128 * 1024,
  704. };
  705. /* set dma transfer size */
  706. static int snd_nm256_pcm_hw_params(struct snd_pcm_substream *substream,
  707. struct snd_pcm_hw_params *hw_params)
  708. {
  709. /* area and addr are already set and unchanged */
  710. substream->runtime->dma_bytes = params_buffer_bytes(hw_params);
  711. return 0;
  712. }
  713. /*
  714. * open
  715. */
  716. static void snd_nm256_setup_stream(struct nm256 *chip, struct nm256_stream *s,
  717. struct snd_pcm_substream *substream,
  718. struct snd_pcm_hardware *hw_ptr)
  719. {
  720. struct snd_pcm_runtime *runtime = substream->runtime;
  721. s->running = 0;
  722. runtime->hw = *hw_ptr;
  723. runtime->hw.buffer_bytes_max = s->bufsize;
  724. runtime->hw.period_bytes_max = s->bufsize / 2;
  725. runtime->dma_area = (void __force *) s->bufptr;
  726. runtime->dma_addr = s->bufptr_addr;
  727. runtime->dma_bytes = s->bufsize;
  728. runtime->private_data = s;
  729. s->substream = substream;
  730. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  731. &constraints_rates);
  732. }
  733. static int
  734. snd_nm256_playback_open(struct snd_pcm_substream *substream)
  735. {
  736. struct nm256 *chip = snd_pcm_substream_chip(substream);
  737. if (snd_nm256_acquire_irq(chip) < 0)
  738. return -EBUSY;
  739. snd_nm256_setup_stream(chip, &chip->streams[SNDRV_PCM_STREAM_PLAYBACK],
  740. substream, &snd_nm256_playback);
  741. return 0;
  742. }
  743. static int
  744. snd_nm256_capture_open(struct snd_pcm_substream *substream)
  745. {
  746. struct nm256 *chip = snd_pcm_substream_chip(substream);
  747. if (snd_nm256_acquire_irq(chip) < 0)
  748. return -EBUSY;
  749. snd_nm256_setup_stream(chip, &chip->streams[SNDRV_PCM_STREAM_CAPTURE],
  750. substream, &snd_nm256_capture);
  751. return 0;
  752. }
  753. /*
  754. * close - we don't have to do special..
  755. */
  756. static int
  757. snd_nm256_playback_close(struct snd_pcm_substream *substream)
  758. {
  759. struct nm256 *chip = snd_pcm_substream_chip(substream);
  760. snd_nm256_release_irq(chip);
  761. return 0;
  762. }
  763. static int
  764. snd_nm256_capture_close(struct snd_pcm_substream *substream)
  765. {
  766. struct nm256 *chip = snd_pcm_substream_chip(substream);
  767. snd_nm256_release_irq(chip);
  768. return 0;
  769. }
  770. /*
  771. * create a pcm instance
  772. */
  773. static struct snd_pcm_ops snd_nm256_playback_ops = {
  774. .open = snd_nm256_playback_open,
  775. .close = snd_nm256_playback_close,
  776. .ioctl = snd_pcm_lib_ioctl,
  777. .hw_params = snd_nm256_pcm_hw_params,
  778. .prepare = snd_nm256_pcm_prepare,
  779. .trigger = snd_nm256_playback_trigger,
  780. .pointer = snd_nm256_playback_pointer,
  781. #ifndef __i386__
  782. .copy = snd_nm256_playback_copy,
  783. .silence = snd_nm256_playback_silence,
  784. #endif
  785. .mmap = snd_pcm_lib_mmap_iomem,
  786. };
  787. static struct snd_pcm_ops snd_nm256_capture_ops = {
  788. .open = snd_nm256_capture_open,
  789. .close = snd_nm256_capture_close,
  790. .ioctl = snd_pcm_lib_ioctl,
  791. .hw_params = snd_nm256_pcm_hw_params,
  792. .prepare = snd_nm256_pcm_prepare,
  793. .trigger = snd_nm256_capture_trigger,
  794. .pointer = snd_nm256_capture_pointer,
  795. #ifndef __i386__
  796. .copy = snd_nm256_capture_copy,
  797. #endif
  798. .mmap = snd_pcm_lib_mmap_iomem,
  799. };
  800. static int
  801. snd_nm256_pcm(struct nm256 *chip, int device)
  802. {
  803. struct snd_pcm *pcm;
  804. int i, err;
  805. for (i = 0; i < 2; i++) {
  806. struct nm256_stream *s = &chip->streams[i];
  807. s->bufptr = chip->buffer + (s->buf - chip->buffer_start);
  808. s->bufptr_addr = chip->buffer_addr + (s->buf - chip->buffer_start);
  809. }
  810. err = snd_pcm_new(chip->card, chip->card->driver, device,
  811. 1, 1, &pcm);
  812. if (err < 0)
  813. return err;
  814. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_nm256_playback_ops);
  815. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_nm256_capture_ops);
  816. pcm->private_data = chip;
  817. pcm->info_flags = 0;
  818. chip->pcm = pcm;
  819. return 0;
  820. }
  821. /*
  822. * Initialize the hardware.
  823. */
  824. static void
  825. snd_nm256_init_chip(struct nm256 *chip)
  826. {
  827. /* Reset everything. */
  828. snd_nm256_writeb(chip, 0x0, 0x11);
  829. snd_nm256_writew(chip, 0x214, 0);
  830. /* stop sounds.. */
  831. //snd_nm256_playback_stop(chip);
  832. //snd_nm256_capture_stop(chip);
  833. }
  834. static irqreturn_t
  835. snd_nm256_intr_check(struct nm256 *chip)
  836. {
  837. if (chip->badintrcount++ > 1000) {
  838. /*
  839. * I'm not sure if the best thing is to stop the card from
  840. * playing or just release the interrupt (after all, we're in
  841. * a bad situation, so doing fancy stuff may not be such a good
  842. * idea).
  843. *
  844. * I worry about the card engine continuing to play noise
  845. * over and over, however--that could become a very
  846. * obnoxious problem. And we know that when this usually
  847. * happens things are fairly safe, it just means the user's
  848. * inserted a PCMCIA card and someone's spamming us with IRQ 9s.
  849. */
  850. if (chip->streams[SNDRV_PCM_STREAM_PLAYBACK].running)
  851. snd_nm256_playback_stop(chip);
  852. if (chip->streams[SNDRV_PCM_STREAM_CAPTURE].running)
  853. snd_nm256_capture_stop(chip);
  854. chip->badintrcount = 0;
  855. return IRQ_HANDLED;
  856. }
  857. return IRQ_NONE;
  858. }
  859. /*
  860. * Handle a potential interrupt for the device referred to by DEV_ID.
  861. *
  862. * I don't like the cut-n-paste job here either between the two routines,
  863. * but there are sufficient differences between the two interrupt handlers
  864. * that parameterizing it isn't all that great either. (Could use a macro,
  865. * I suppose...yucky bleah.)
  866. */
  867. static irqreturn_t
  868. snd_nm256_interrupt(int irq, void *dev_id)
  869. {
  870. struct nm256 *chip = dev_id;
  871. u16 status;
  872. u8 cbyte;
  873. status = snd_nm256_readw(chip, NM_INT_REG);
  874. /* Not ours. */
  875. if (status == 0)
  876. return snd_nm256_intr_check(chip);
  877. chip->badintrcount = 0;
  878. /* Rather boring; check for individual interrupts and process them. */
  879. spin_lock(&chip->reg_lock);
  880. if (status & NM_PLAYBACK_INT) {
  881. status &= ~NM_PLAYBACK_INT;
  882. NM_ACK_INT(chip, NM_PLAYBACK_INT);
  883. snd_nm256_playback_update(chip);
  884. }
  885. if (status & NM_RECORD_INT) {
  886. status &= ~NM_RECORD_INT;
  887. NM_ACK_INT(chip, NM_RECORD_INT);
  888. snd_nm256_capture_update(chip);
  889. }
  890. if (status & NM_MISC_INT_1) {
  891. status &= ~NM_MISC_INT_1;
  892. NM_ACK_INT(chip, NM_MISC_INT_1);
  893. dev_dbg(chip->card->dev, "NM256: Got misc interrupt #1\n");
  894. snd_nm256_writew(chip, NM_INT_REG, 0x8000);
  895. cbyte = snd_nm256_readb(chip, 0x400);
  896. snd_nm256_writeb(chip, 0x400, cbyte | 2);
  897. }
  898. if (status & NM_MISC_INT_2) {
  899. status &= ~NM_MISC_INT_2;
  900. NM_ACK_INT(chip, NM_MISC_INT_2);
  901. dev_dbg(chip->card->dev, "NM256: Got misc interrupt #2\n");
  902. cbyte = snd_nm256_readb(chip, 0x400);
  903. snd_nm256_writeb(chip, 0x400, cbyte & ~2);
  904. }
  905. /* Unknown interrupt. */
  906. if (status) {
  907. dev_dbg(chip->card->dev,
  908. "NM256: Fire in the hole! Unknown status 0x%x\n",
  909. status);
  910. /* Pray. */
  911. NM_ACK_INT(chip, status);
  912. }
  913. spin_unlock(&chip->reg_lock);
  914. return IRQ_HANDLED;
  915. }
  916. /*
  917. * Handle a potential interrupt for the device referred to by DEV_ID.
  918. * This handler is for the 256ZX, and is very similar to the non-ZX
  919. * routine.
  920. */
  921. static irqreturn_t
  922. snd_nm256_interrupt_zx(int irq, void *dev_id)
  923. {
  924. struct nm256 *chip = dev_id;
  925. u32 status;
  926. u8 cbyte;
  927. status = snd_nm256_readl(chip, NM_INT_REG);
  928. /* Not ours. */
  929. if (status == 0)
  930. return snd_nm256_intr_check(chip);
  931. chip->badintrcount = 0;
  932. /* Rather boring; check for individual interrupts and process them. */
  933. spin_lock(&chip->reg_lock);
  934. if (status & NM2_PLAYBACK_INT) {
  935. status &= ~NM2_PLAYBACK_INT;
  936. NM2_ACK_INT(chip, NM2_PLAYBACK_INT);
  937. snd_nm256_playback_update(chip);
  938. }
  939. if (status & NM2_RECORD_INT) {
  940. status &= ~NM2_RECORD_INT;
  941. NM2_ACK_INT(chip, NM2_RECORD_INT);
  942. snd_nm256_capture_update(chip);
  943. }
  944. if (status & NM2_MISC_INT_1) {
  945. status &= ~NM2_MISC_INT_1;
  946. NM2_ACK_INT(chip, NM2_MISC_INT_1);
  947. dev_dbg(chip->card->dev, "NM256: Got misc interrupt #1\n");
  948. cbyte = snd_nm256_readb(chip, 0x400);
  949. snd_nm256_writeb(chip, 0x400, cbyte | 2);
  950. }
  951. if (status & NM2_MISC_INT_2) {
  952. status &= ~NM2_MISC_INT_2;
  953. NM2_ACK_INT(chip, NM2_MISC_INT_2);
  954. dev_dbg(chip->card->dev, "NM256: Got misc interrupt #2\n");
  955. cbyte = snd_nm256_readb(chip, 0x400);
  956. snd_nm256_writeb(chip, 0x400, cbyte & ~2);
  957. }
  958. /* Unknown interrupt. */
  959. if (status) {
  960. dev_dbg(chip->card->dev,
  961. "NM256: Fire in the hole! Unknown status 0x%x\n",
  962. status);
  963. /* Pray. */
  964. NM2_ACK_INT(chip, status);
  965. }
  966. spin_unlock(&chip->reg_lock);
  967. return IRQ_HANDLED;
  968. }
  969. /*
  970. * AC97 interface
  971. */
  972. /*
  973. * Waits for the mixer to become ready to be written; returns a zero value
  974. * if it timed out.
  975. */
  976. static int
  977. snd_nm256_ac97_ready(struct nm256 *chip)
  978. {
  979. int timeout = 10;
  980. u32 testaddr;
  981. u16 testb;
  982. testaddr = chip->mixer_status_offset;
  983. testb = chip->mixer_status_mask;
  984. /*
  985. * Loop around waiting for the mixer to become ready.
  986. */
  987. while (timeout-- > 0) {
  988. if ((snd_nm256_readw(chip, testaddr) & testb) == 0)
  989. return 1;
  990. udelay(100);
  991. }
  992. return 0;
  993. }
  994. /*
  995. * Initial register values to be written to the AC97 mixer.
  996. * While most of these are identical to the reset values, we do this
  997. * so that we have most of the register contents cached--this avoids
  998. * reading from the mixer directly (which seems to be problematic,
  999. * probably due to ignorance).
  1000. */
  1001. struct initialValues {
  1002. unsigned short reg;
  1003. unsigned short value;
  1004. };
  1005. static struct initialValues nm256_ac97_init_val[] =
  1006. {
  1007. { AC97_MASTER, 0x8000 },
  1008. { AC97_HEADPHONE, 0x8000 },
  1009. { AC97_MASTER_MONO, 0x8000 },
  1010. { AC97_PC_BEEP, 0x8000 },
  1011. { AC97_PHONE, 0x8008 },
  1012. { AC97_MIC, 0x8000 },
  1013. { AC97_LINE, 0x8808 },
  1014. { AC97_CD, 0x8808 },
  1015. { AC97_VIDEO, 0x8808 },
  1016. { AC97_AUX, 0x8808 },
  1017. { AC97_PCM, 0x8808 },
  1018. { AC97_REC_SEL, 0x0000 },
  1019. { AC97_REC_GAIN, 0x0B0B },
  1020. { AC97_GENERAL_PURPOSE, 0x0000 },
  1021. { AC97_3D_CONTROL, 0x8000 },
  1022. { AC97_VENDOR_ID1, 0x8384 },
  1023. { AC97_VENDOR_ID2, 0x7609 },
  1024. };
  1025. static int nm256_ac97_idx(unsigned short reg)
  1026. {
  1027. int i;
  1028. for (i = 0; i < ARRAY_SIZE(nm256_ac97_init_val); i++)
  1029. if (nm256_ac97_init_val[i].reg == reg)
  1030. return i;
  1031. return -1;
  1032. }
  1033. /*
  1034. * some nm256 easily crash when reading from mixer registers
  1035. * thus we're treating it as a write-only mixer and cache the
  1036. * written values
  1037. */
  1038. static unsigned short
  1039. snd_nm256_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
  1040. {
  1041. struct nm256 *chip = ac97->private_data;
  1042. int idx = nm256_ac97_idx(reg);
  1043. if (idx < 0)
  1044. return 0;
  1045. return chip->ac97_regs[idx];
  1046. }
  1047. /*
  1048. */
  1049. static void
  1050. snd_nm256_ac97_write(struct snd_ac97 *ac97,
  1051. unsigned short reg, unsigned short val)
  1052. {
  1053. struct nm256 *chip = ac97->private_data;
  1054. int tries = 2;
  1055. int idx = nm256_ac97_idx(reg);
  1056. u32 base;
  1057. if (idx < 0)
  1058. return;
  1059. base = chip->mixer_base;
  1060. snd_nm256_ac97_ready(chip);
  1061. /* Wait for the write to take, too. */
  1062. while (tries-- > 0) {
  1063. snd_nm256_writew(chip, base + reg, val);
  1064. msleep(1); /* a little delay here seems better.. */
  1065. if (snd_nm256_ac97_ready(chip)) {
  1066. /* successful write: set cache */
  1067. chip->ac97_regs[idx] = val;
  1068. return;
  1069. }
  1070. }
  1071. dev_dbg(chip->card->dev, "nm256: ac97 codec not ready..\n");
  1072. }
  1073. /* static resolution table */
  1074. static struct snd_ac97_res_table nm256_res_table[] = {
  1075. { AC97_MASTER, 0x1f1f },
  1076. { AC97_HEADPHONE, 0x1f1f },
  1077. { AC97_MASTER_MONO, 0x001f },
  1078. { AC97_PC_BEEP, 0x001f },
  1079. { AC97_PHONE, 0x001f },
  1080. { AC97_MIC, 0x001f },
  1081. { AC97_LINE, 0x1f1f },
  1082. { AC97_CD, 0x1f1f },
  1083. { AC97_VIDEO, 0x1f1f },
  1084. { AC97_AUX, 0x1f1f },
  1085. { AC97_PCM, 0x1f1f },
  1086. { AC97_REC_GAIN, 0x0f0f },
  1087. { } /* terminator */
  1088. };
  1089. /* initialize the ac97 into a known state */
  1090. static void
  1091. snd_nm256_ac97_reset(struct snd_ac97 *ac97)
  1092. {
  1093. struct nm256 *chip = ac97->private_data;
  1094. /* Reset the mixer. 'Tis magic! */
  1095. snd_nm256_writeb(chip, 0x6c0, 1);
  1096. if (! chip->reset_workaround) {
  1097. /* Dell latitude LS will lock up by this */
  1098. snd_nm256_writeb(chip, 0x6cc, 0x87);
  1099. }
  1100. if (! chip->reset_workaround_2) {
  1101. /* Dell latitude CSx will lock up by this */
  1102. snd_nm256_writeb(chip, 0x6cc, 0x80);
  1103. snd_nm256_writeb(chip, 0x6cc, 0x0);
  1104. }
  1105. if (! chip->in_resume) {
  1106. int i;
  1107. for (i = 0; i < ARRAY_SIZE(nm256_ac97_init_val); i++) {
  1108. /* preload the cache, so as to avoid even a single
  1109. * read of the mixer regs
  1110. */
  1111. snd_nm256_ac97_write(ac97, nm256_ac97_init_val[i].reg,
  1112. nm256_ac97_init_val[i].value);
  1113. }
  1114. }
  1115. }
  1116. /* create an ac97 mixer interface */
  1117. static int
  1118. snd_nm256_mixer(struct nm256 *chip)
  1119. {
  1120. struct snd_ac97_bus *pbus;
  1121. struct snd_ac97_template ac97;
  1122. int err;
  1123. static struct snd_ac97_bus_ops ops = {
  1124. .reset = snd_nm256_ac97_reset,
  1125. .write = snd_nm256_ac97_write,
  1126. .read = snd_nm256_ac97_read,
  1127. };
  1128. chip->ac97_regs = kcalloc(ARRAY_SIZE(nm256_ac97_init_val),
  1129. sizeof(short), GFP_KERNEL);
  1130. if (! chip->ac97_regs)
  1131. return -ENOMEM;
  1132. if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
  1133. return err;
  1134. memset(&ac97, 0, sizeof(ac97));
  1135. ac97.scaps = AC97_SCAP_AUDIO; /* we support audio! */
  1136. ac97.private_data = chip;
  1137. ac97.res_table = nm256_res_table;
  1138. pbus->no_vra = 1;
  1139. err = snd_ac97_mixer(pbus, &ac97, &chip->ac97);
  1140. if (err < 0)
  1141. return err;
  1142. if (! (chip->ac97->id & (0xf0000000))) {
  1143. /* looks like an invalid id */
  1144. sprintf(chip->card->mixername, "%s AC97", chip->card->driver);
  1145. }
  1146. return 0;
  1147. }
  1148. /*
  1149. * See if the signature left by the NM256 BIOS is intact; if so, we use
  1150. * the associated address as the end of our audio buffer in the video
  1151. * RAM.
  1152. */
  1153. static int
  1154. snd_nm256_peek_for_sig(struct nm256 *chip)
  1155. {
  1156. /* The signature is located 1K below the end of video RAM. */
  1157. void __iomem *temp;
  1158. /* Default buffer end is 5120 bytes below the top of RAM. */
  1159. unsigned long pointer_found = chip->buffer_end - 0x1400;
  1160. u32 sig;
  1161. temp = ioremap_nocache(chip->buffer_addr + chip->buffer_end - 0x400, 16);
  1162. if (temp == NULL) {
  1163. dev_err(chip->card->dev,
  1164. "Unable to scan for card signature in video RAM\n");
  1165. return -EBUSY;
  1166. }
  1167. sig = readl(temp);
  1168. if ((sig & NM_SIG_MASK) == NM_SIGNATURE) {
  1169. u32 pointer = readl(temp + 4);
  1170. /*
  1171. * If it's obviously invalid, don't use it
  1172. */
  1173. if (pointer == 0xffffffff ||
  1174. pointer < chip->buffer_size ||
  1175. pointer > chip->buffer_end) {
  1176. dev_err(chip->card->dev,
  1177. "invalid signature found: 0x%x\n", pointer);
  1178. iounmap(temp);
  1179. return -ENODEV;
  1180. } else {
  1181. pointer_found = pointer;
  1182. dev_info(chip->card->dev,
  1183. "found card signature in video RAM: 0x%x\n",
  1184. pointer);
  1185. }
  1186. }
  1187. iounmap(temp);
  1188. chip->buffer_end = pointer_found;
  1189. return 0;
  1190. }
  1191. #ifdef CONFIG_PM_SLEEP
  1192. /*
  1193. * APM event handler, so the card is properly reinitialized after a power
  1194. * event.
  1195. */
  1196. static int nm256_suspend(struct device *dev)
  1197. {
  1198. struct snd_card *card = dev_get_drvdata(dev);
  1199. struct nm256 *chip = card->private_data;
  1200. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  1201. snd_pcm_suspend_all(chip->pcm);
  1202. snd_ac97_suspend(chip->ac97);
  1203. chip->coeffs_current = 0;
  1204. return 0;
  1205. }
  1206. static int nm256_resume(struct device *dev)
  1207. {
  1208. struct snd_card *card = dev_get_drvdata(dev);
  1209. struct nm256 *chip = card->private_data;
  1210. int i;
  1211. /* Perform a full reset on the hardware */
  1212. chip->in_resume = 1;
  1213. snd_nm256_init_chip(chip);
  1214. /* restore ac97 */
  1215. snd_ac97_resume(chip->ac97);
  1216. for (i = 0; i < 2; i++) {
  1217. struct nm256_stream *s = &chip->streams[i];
  1218. if (s->substream && s->suspended) {
  1219. spin_lock_irq(&chip->reg_lock);
  1220. snd_nm256_set_format(chip, s, s->substream);
  1221. spin_unlock_irq(&chip->reg_lock);
  1222. }
  1223. }
  1224. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  1225. chip->in_resume = 0;
  1226. return 0;
  1227. }
  1228. static SIMPLE_DEV_PM_OPS(nm256_pm, nm256_suspend, nm256_resume);
  1229. #define NM256_PM_OPS &nm256_pm
  1230. #else
  1231. #define NM256_PM_OPS NULL
  1232. #endif /* CONFIG_PM_SLEEP */
  1233. static int snd_nm256_free(struct nm256 *chip)
  1234. {
  1235. if (chip->streams[SNDRV_PCM_STREAM_PLAYBACK].running)
  1236. snd_nm256_playback_stop(chip);
  1237. if (chip->streams[SNDRV_PCM_STREAM_CAPTURE].running)
  1238. snd_nm256_capture_stop(chip);
  1239. if (chip->irq >= 0)
  1240. free_irq(chip->irq, chip);
  1241. iounmap(chip->cport);
  1242. iounmap(chip->buffer);
  1243. release_and_free_resource(chip->res_cport);
  1244. release_and_free_resource(chip->res_buffer);
  1245. pci_disable_device(chip->pci);
  1246. kfree(chip->ac97_regs);
  1247. kfree(chip);
  1248. return 0;
  1249. }
  1250. static int snd_nm256_dev_free(struct snd_device *device)
  1251. {
  1252. struct nm256 *chip = device->device_data;
  1253. return snd_nm256_free(chip);
  1254. }
  1255. static int
  1256. snd_nm256_create(struct snd_card *card, struct pci_dev *pci,
  1257. struct nm256 **chip_ret)
  1258. {
  1259. struct nm256 *chip;
  1260. int err, pval;
  1261. static struct snd_device_ops ops = {
  1262. .dev_free = snd_nm256_dev_free,
  1263. };
  1264. u32 addr;
  1265. *chip_ret = NULL;
  1266. if ((err = pci_enable_device(pci)) < 0)
  1267. return err;
  1268. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  1269. if (chip == NULL) {
  1270. pci_disable_device(pci);
  1271. return -ENOMEM;
  1272. }
  1273. chip->card = card;
  1274. chip->pci = pci;
  1275. chip->use_cache = use_cache;
  1276. spin_lock_init(&chip->reg_lock);
  1277. chip->irq = -1;
  1278. mutex_init(&chip->irq_mutex);
  1279. /* store buffer sizes in bytes */
  1280. chip->streams[SNDRV_PCM_STREAM_PLAYBACK].bufsize = playback_bufsize * 1024;
  1281. chip->streams[SNDRV_PCM_STREAM_CAPTURE].bufsize = capture_bufsize * 1024;
  1282. /*
  1283. * The NM256 has two memory ports. The first port is nothing
  1284. * more than a chunk of video RAM, which is used as the I/O ring
  1285. * buffer. The second port has the actual juicy stuff (like the
  1286. * mixer and the playback engine control registers).
  1287. */
  1288. chip->buffer_addr = pci_resource_start(pci, 0);
  1289. chip->cport_addr = pci_resource_start(pci, 1);
  1290. /* Init the memory port info. */
  1291. /* remap control port (#2) */
  1292. chip->res_cport = request_mem_region(chip->cport_addr, NM_PORT2_SIZE,
  1293. card->driver);
  1294. if (chip->res_cport == NULL) {
  1295. dev_err(card->dev, "memory region 0x%lx (size 0x%x) busy\n",
  1296. chip->cport_addr, NM_PORT2_SIZE);
  1297. err = -EBUSY;
  1298. goto __error;
  1299. }
  1300. chip->cport = ioremap_nocache(chip->cport_addr, NM_PORT2_SIZE);
  1301. if (chip->cport == NULL) {
  1302. dev_err(card->dev, "unable to map control port %lx\n",
  1303. chip->cport_addr);
  1304. err = -ENOMEM;
  1305. goto __error;
  1306. }
  1307. if (!strcmp(card->driver, "NM256AV")) {
  1308. /* Ok, try to see if this is a non-AC97 version of the hardware. */
  1309. pval = snd_nm256_readw(chip, NM_MIXER_PRESENCE);
  1310. if ((pval & NM_PRESENCE_MASK) != NM_PRESENCE_VALUE) {
  1311. if (! force_ac97) {
  1312. dev_err(card->dev,
  1313. "no ac97 is found!\n");
  1314. dev_err(card->dev,
  1315. "force the driver to load by passing in the module parameter\n");
  1316. dev_err(card->dev,
  1317. " force_ac97=1\n");
  1318. dev_err(card->dev,
  1319. "or try sb16, opl3sa2, or cs423x drivers instead.\n");
  1320. err = -ENXIO;
  1321. goto __error;
  1322. }
  1323. }
  1324. chip->buffer_end = 2560 * 1024;
  1325. chip->interrupt = snd_nm256_interrupt;
  1326. chip->mixer_status_offset = NM_MIXER_STATUS_OFFSET;
  1327. chip->mixer_status_mask = NM_MIXER_READY_MASK;
  1328. } else {
  1329. /* Not sure if there is any relevant detect for the ZX or not. */
  1330. if (snd_nm256_readb(chip, 0xa0b) != 0)
  1331. chip->buffer_end = 6144 * 1024;
  1332. else
  1333. chip->buffer_end = 4096 * 1024;
  1334. chip->interrupt = snd_nm256_interrupt_zx;
  1335. chip->mixer_status_offset = NM2_MIXER_STATUS_OFFSET;
  1336. chip->mixer_status_mask = NM2_MIXER_READY_MASK;
  1337. }
  1338. chip->buffer_size = chip->streams[SNDRV_PCM_STREAM_PLAYBACK].bufsize +
  1339. chip->streams[SNDRV_PCM_STREAM_CAPTURE].bufsize;
  1340. if (chip->use_cache)
  1341. chip->buffer_size += NM_TOTAL_COEFF_COUNT * 4;
  1342. else
  1343. chip->buffer_size += NM_MAX_PLAYBACK_COEF_SIZE + NM_MAX_RECORD_COEF_SIZE;
  1344. if (buffer_top >= chip->buffer_size && buffer_top < chip->buffer_end)
  1345. chip->buffer_end = buffer_top;
  1346. else {
  1347. /* get buffer end pointer from signature */
  1348. if ((err = snd_nm256_peek_for_sig(chip)) < 0)
  1349. goto __error;
  1350. }
  1351. chip->buffer_start = chip->buffer_end - chip->buffer_size;
  1352. chip->buffer_addr += chip->buffer_start;
  1353. dev_info(card->dev, "Mapping port 1 from 0x%x - 0x%x\n",
  1354. chip->buffer_start, chip->buffer_end);
  1355. chip->res_buffer = request_mem_region(chip->buffer_addr,
  1356. chip->buffer_size,
  1357. card->driver);
  1358. if (chip->res_buffer == NULL) {
  1359. dev_err(card->dev, "buffer 0x%lx (size 0x%x) busy\n",
  1360. chip->buffer_addr, chip->buffer_size);
  1361. err = -EBUSY;
  1362. goto __error;
  1363. }
  1364. chip->buffer = ioremap_nocache(chip->buffer_addr, chip->buffer_size);
  1365. if (chip->buffer == NULL) {
  1366. err = -ENOMEM;
  1367. dev_err(card->dev, "unable to map ring buffer at %lx\n",
  1368. chip->buffer_addr);
  1369. goto __error;
  1370. }
  1371. /* set offsets */
  1372. addr = chip->buffer_start;
  1373. chip->streams[SNDRV_PCM_STREAM_PLAYBACK].buf = addr;
  1374. addr += chip->streams[SNDRV_PCM_STREAM_PLAYBACK].bufsize;
  1375. chip->streams[SNDRV_PCM_STREAM_CAPTURE].buf = addr;
  1376. addr += chip->streams[SNDRV_PCM_STREAM_CAPTURE].bufsize;
  1377. if (chip->use_cache) {
  1378. chip->all_coeff_buf = addr;
  1379. } else {
  1380. chip->coeff_buf[SNDRV_PCM_STREAM_PLAYBACK] = addr;
  1381. addr += NM_MAX_PLAYBACK_COEF_SIZE;
  1382. chip->coeff_buf[SNDRV_PCM_STREAM_CAPTURE] = addr;
  1383. }
  1384. /* Fixed setting. */
  1385. chip->mixer_base = NM_MIXER_OFFSET;
  1386. chip->coeffs_current = 0;
  1387. snd_nm256_init_chip(chip);
  1388. // pci_set_master(pci); /* needed? */
  1389. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0)
  1390. goto __error;
  1391. *chip_ret = chip;
  1392. return 0;
  1393. __error:
  1394. snd_nm256_free(chip);
  1395. return err;
  1396. }
  1397. enum { NM_BLACKLISTED, NM_RESET_WORKAROUND, NM_RESET_WORKAROUND_2 };
  1398. static struct snd_pci_quirk nm256_quirks[] = {
  1399. /* HP omnibook 4150 has cs4232 codec internally */
  1400. SND_PCI_QUIRK(0x103c, 0x0007, "HP omnibook 4150", NM_BLACKLISTED),
  1401. /* Reset workarounds to avoid lock-ups */
  1402. SND_PCI_QUIRK(0x104d, 0x8041, "Sony PCG-F305", NM_RESET_WORKAROUND),
  1403. SND_PCI_QUIRK(0x1028, 0x0080, "Dell Latitude LS", NM_RESET_WORKAROUND),
  1404. SND_PCI_QUIRK(0x1028, 0x0091, "Dell Latitude CSx", NM_RESET_WORKAROUND_2),
  1405. { } /* terminator */
  1406. };
  1407. static int snd_nm256_probe(struct pci_dev *pci,
  1408. const struct pci_device_id *pci_id)
  1409. {
  1410. struct snd_card *card;
  1411. struct nm256 *chip;
  1412. int err;
  1413. const struct snd_pci_quirk *q;
  1414. q = snd_pci_quirk_lookup(pci, nm256_quirks);
  1415. if (q) {
  1416. dev_dbg(&pci->dev, "Enabled quirk for %s.\n",
  1417. snd_pci_quirk_name(q));
  1418. switch (q->value) {
  1419. case NM_BLACKLISTED:
  1420. dev_info(&pci->dev,
  1421. "The device is blacklisted. Loading stopped\n");
  1422. return -ENODEV;
  1423. case NM_RESET_WORKAROUND_2:
  1424. reset_workaround_2 = 1;
  1425. /* Fall-through */
  1426. case NM_RESET_WORKAROUND:
  1427. reset_workaround = 1;
  1428. break;
  1429. }
  1430. }
  1431. err = snd_card_new(&pci->dev, index, id, THIS_MODULE, 0, &card);
  1432. if (err < 0)
  1433. return err;
  1434. switch (pci->device) {
  1435. case PCI_DEVICE_ID_NEOMAGIC_NM256AV_AUDIO:
  1436. strcpy(card->driver, "NM256AV");
  1437. break;
  1438. case PCI_DEVICE_ID_NEOMAGIC_NM256ZX_AUDIO:
  1439. strcpy(card->driver, "NM256ZX");
  1440. break;
  1441. case PCI_DEVICE_ID_NEOMAGIC_NM256XL_PLUS_AUDIO:
  1442. strcpy(card->driver, "NM256XL+");
  1443. break;
  1444. default:
  1445. dev_err(&pci->dev, "invalid device id 0x%x\n", pci->device);
  1446. snd_card_free(card);
  1447. return -EINVAL;
  1448. }
  1449. if (vaio_hack)
  1450. buffer_top = 0x25a800; /* this avoids conflicts with XFree86 server */
  1451. if (playback_bufsize < 4)
  1452. playback_bufsize = 4;
  1453. if (playback_bufsize > 128)
  1454. playback_bufsize = 128;
  1455. if (capture_bufsize < 4)
  1456. capture_bufsize = 4;
  1457. if (capture_bufsize > 128)
  1458. capture_bufsize = 128;
  1459. if ((err = snd_nm256_create(card, pci, &chip)) < 0) {
  1460. snd_card_free(card);
  1461. return err;
  1462. }
  1463. card->private_data = chip;
  1464. if (reset_workaround) {
  1465. dev_dbg(&pci->dev, "reset_workaround activated\n");
  1466. chip->reset_workaround = 1;
  1467. }
  1468. if (reset_workaround_2) {
  1469. dev_dbg(&pci->dev, "reset_workaround_2 activated\n");
  1470. chip->reset_workaround_2 = 1;
  1471. }
  1472. if ((err = snd_nm256_pcm(chip, 0)) < 0 ||
  1473. (err = snd_nm256_mixer(chip)) < 0) {
  1474. snd_card_free(card);
  1475. return err;
  1476. }
  1477. sprintf(card->shortname, "NeoMagic %s", card->driver);
  1478. sprintf(card->longname, "%s at 0x%lx & 0x%lx, irq %d",
  1479. card->shortname,
  1480. chip->buffer_addr, chip->cport_addr, chip->irq);
  1481. if ((err = snd_card_register(card)) < 0) {
  1482. snd_card_free(card);
  1483. return err;
  1484. }
  1485. pci_set_drvdata(pci, card);
  1486. return 0;
  1487. }
  1488. static void snd_nm256_remove(struct pci_dev *pci)
  1489. {
  1490. snd_card_free(pci_get_drvdata(pci));
  1491. }
  1492. static struct pci_driver nm256_driver = {
  1493. .name = KBUILD_MODNAME,
  1494. .id_table = snd_nm256_ids,
  1495. .probe = snd_nm256_probe,
  1496. .remove = snd_nm256_remove,
  1497. .driver = {
  1498. .pm = NM256_PM_OPS,
  1499. },
  1500. };
  1501. module_pci_driver(nm256_driver);