fsi.c 46 KB

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  1. /*
  2. * Fifo-attached Serial Interface (FSI) support for SH7724
  3. *
  4. * Copyright (C) 2009 Renesas Solutions Corp.
  5. * Kuninori Morimoto <morimoto.kuninori@renesas.com>
  6. *
  7. * Based on ssi.c
  8. * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/delay.h>
  15. #include <linux/dma-mapping.h>
  16. #include <linux/pm_runtime.h>
  17. #include <linux/io.h>
  18. #include <linux/of.h>
  19. #include <linux/of_device.h>
  20. #include <linux/scatterlist.h>
  21. #include <linux/sh_dma.h>
  22. #include <linux/slab.h>
  23. #include <linux/module.h>
  24. #include <linux/workqueue.h>
  25. #include <sound/soc.h>
  26. #include <sound/pcm_params.h>
  27. #include <sound/sh_fsi.h>
  28. /* PortA/PortB register */
  29. #define REG_DO_FMT 0x0000
  30. #define REG_DOFF_CTL 0x0004
  31. #define REG_DOFF_ST 0x0008
  32. #define REG_DI_FMT 0x000C
  33. #define REG_DIFF_CTL 0x0010
  34. #define REG_DIFF_ST 0x0014
  35. #define REG_CKG1 0x0018
  36. #define REG_CKG2 0x001C
  37. #define REG_DIDT 0x0020
  38. #define REG_DODT 0x0024
  39. #define REG_MUTE_ST 0x0028
  40. #define REG_OUT_DMAC 0x002C
  41. #define REG_OUT_SEL 0x0030
  42. #define REG_IN_DMAC 0x0038
  43. /* master register */
  44. #define MST_CLK_RST 0x0210
  45. #define MST_SOFT_RST 0x0214
  46. #define MST_FIFO_SZ 0x0218
  47. /* core register (depend on FSI version) */
  48. #define A_MST_CTLR 0x0180
  49. #define B_MST_CTLR 0x01A0
  50. #define CPU_INT_ST 0x01F4
  51. #define CPU_IEMSK 0x01F8
  52. #define CPU_IMSK 0x01FC
  53. #define INT_ST 0x0200
  54. #define IEMSK 0x0204
  55. #define IMSK 0x0208
  56. /* DO_FMT */
  57. /* DI_FMT */
  58. #define CR_BWS_MASK (0x3 << 20) /* FSI2 */
  59. #define CR_BWS_24 (0x0 << 20) /* FSI2 */
  60. #define CR_BWS_16 (0x1 << 20) /* FSI2 */
  61. #define CR_BWS_20 (0x2 << 20) /* FSI2 */
  62. #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */
  63. #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */
  64. #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */
  65. #define CR_MONO (0x0 << 4)
  66. #define CR_MONO_D (0x1 << 4)
  67. #define CR_PCM (0x2 << 4)
  68. #define CR_I2S (0x3 << 4)
  69. #define CR_TDM (0x4 << 4)
  70. #define CR_TDM_D (0x5 << 4)
  71. /* OUT_DMAC */
  72. /* IN_DMAC */
  73. #define VDMD_MASK (0x3 << 4)
  74. #define VDMD_FRONT (0x0 << 4) /* Package in front */
  75. #define VDMD_BACK (0x1 << 4) /* Package in back */
  76. #define VDMD_STREAM (0x2 << 4) /* Stream mode(16bit * 2) */
  77. #define DMA_ON (0x1 << 0)
  78. /* DOFF_CTL */
  79. /* DIFF_CTL */
  80. #define IRQ_HALF 0x00100000
  81. #define FIFO_CLR 0x00000001
  82. /* DOFF_ST */
  83. #define ERR_OVER 0x00000010
  84. #define ERR_UNDER 0x00000001
  85. #define ST_ERR (ERR_OVER | ERR_UNDER)
  86. /* CKG1 */
  87. #define ACKMD_MASK 0x00007000
  88. #define BPFMD_MASK 0x00000700
  89. #define DIMD (1 << 4)
  90. #define DOMD (1 << 0)
  91. /* A/B MST_CTLR */
  92. #define BP (1 << 4) /* Fix the signal of Biphase output */
  93. #define SE (1 << 0) /* Fix the master clock */
  94. /* CLK_RST */
  95. #define CRB (1 << 4)
  96. #define CRA (1 << 0)
  97. /* IO SHIFT / MACRO */
  98. #define BI_SHIFT 12
  99. #define BO_SHIFT 8
  100. #define AI_SHIFT 4
  101. #define AO_SHIFT 0
  102. #define AB_IO(param, shift) (param << shift)
  103. /* SOFT_RST */
  104. #define PBSR (1 << 12) /* Port B Software Reset */
  105. #define PASR (1 << 8) /* Port A Software Reset */
  106. #define IR (1 << 4) /* Interrupt Reset */
  107. #define FSISR (1 << 0) /* Software Reset */
  108. /* OUT_SEL (FSI2) */
  109. #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */
  110. /* 1: Biphase and serial */
  111. /* FIFO_SZ */
  112. #define FIFO_SZ_MASK 0x7
  113. #define FSI_RATES SNDRV_PCM_RATE_8000_96000
  114. #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
  115. /*
  116. * bus options
  117. *
  118. * 0x000000BA
  119. *
  120. * A : sample widtht 16bit setting
  121. * B : sample widtht 24bit setting
  122. */
  123. #define SHIFT_16DATA 0
  124. #define SHIFT_24DATA 4
  125. #define PACKAGE_24BITBUS_BACK 0
  126. #define PACKAGE_24BITBUS_FRONT 1
  127. #define PACKAGE_16BITBUS_STREAM 2
  128. #define BUSOP_SET(s, a) ((a) << SHIFT_ ## s ## DATA)
  129. #define BUSOP_GET(s, a) (((a) >> SHIFT_ ## s ## DATA) & 0xF)
  130. /*
  131. * FSI driver use below type name for variable
  132. *
  133. * xxx_num : number of data
  134. * xxx_pos : position of data
  135. * xxx_capa : capacity of data
  136. */
  137. /*
  138. * period/frame/sample image
  139. *
  140. * ex) PCM (2ch)
  141. *
  142. * period pos period pos
  143. * [n] [n + 1]
  144. * |<-------------------- period--------------------->|
  145. * ==|============================================ ... =|==
  146. * | |
  147. * ||<----- frame ----->|<------ frame ----->| ... |
  148. * |+--------------------+--------------------+- ... |
  149. * ||[ sample ][ sample ]|[ sample ][ sample ]| ... |
  150. * |+--------------------+--------------------+- ... |
  151. * ==|============================================ ... =|==
  152. */
  153. /*
  154. * FSI FIFO image
  155. *
  156. * | |
  157. * | |
  158. * | [ sample ] |
  159. * | [ sample ] |
  160. * | [ sample ] |
  161. * | [ sample ] |
  162. * --> go to codecs
  163. */
  164. /*
  165. * FSI clock
  166. *
  167. * FSIxCLK [CPG] (ick) -------> |
  168. * |-> FSI_DIV (div)-> FSI2
  169. * FSIxCK [external] (xck) ---> |
  170. */
  171. /*
  172. * struct
  173. */
  174. struct fsi_stream_handler;
  175. struct fsi_stream {
  176. /*
  177. * these are initialized by fsi_stream_init()
  178. */
  179. struct snd_pcm_substream *substream;
  180. int fifo_sample_capa; /* sample capacity of FSI FIFO */
  181. int buff_sample_capa; /* sample capacity of ALSA buffer */
  182. int buff_sample_pos; /* sample position of ALSA buffer */
  183. int period_samples; /* sample number / 1 period */
  184. int period_pos; /* current period position */
  185. int sample_width; /* sample width */
  186. int uerr_num;
  187. int oerr_num;
  188. /*
  189. * bus options
  190. */
  191. u32 bus_option;
  192. /*
  193. * thse are initialized by fsi_handler_init()
  194. */
  195. struct fsi_stream_handler *handler;
  196. struct fsi_priv *priv;
  197. /*
  198. * these are for DMAEngine
  199. */
  200. struct dma_chan *chan;
  201. int dma_id;
  202. };
  203. struct fsi_clk {
  204. /* see [FSI clock] */
  205. struct clk *own;
  206. struct clk *xck;
  207. struct clk *ick;
  208. struct clk *div;
  209. int (*set_rate)(struct device *dev,
  210. struct fsi_priv *fsi);
  211. unsigned long rate;
  212. unsigned int count;
  213. };
  214. struct fsi_priv {
  215. void __iomem *base;
  216. phys_addr_t phys;
  217. struct fsi_master *master;
  218. struct fsi_stream playback;
  219. struct fsi_stream capture;
  220. struct fsi_clk clock;
  221. u32 fmt;
  222. int chan_num:16;
  223. unsigned int clk_master:1;
  224. unsigned int clk_cpg:1;
  225. unsigned int spdif:1;
  226. unsigned int enable_stream:1;
  227. unsigned int bit_clk_inv:1;
  228. unsigned int lr_clk_inv:1;
  229. };
  230. struct fsi_stream_handler {
  231. int (*init)(struct fsi_priv *fsi, struct fsi_stream *io);
  232. int (*quit)(struct fsi_priv *fsi, struct fsi_stream *io);
  233. int (*probe)(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev);
  234. int (*transfer)(struct fsi_priv *fsi, struct fsi_stream *io);
  235. int (*remove)(struct fsi_priv *fsi, struct fsi_stream *io);
  236. int (*start_stop)(struct fsi_priv *fsi, struct fsi_stream *io,
  237. int enable);
  238. };
  239. #define fsi_stream_handler_call(io, func, args...) \
  240. (!(io) ? -ENODEV : \
  241. !((io)->handler->func) ? 0 : \
  242. (io)->handler->func(args))
  243. struct fsi_core {
  244. int ver;
  245. u32 int_st;
  246. u32 iemsk;
  247. u32 imsk;
  248. u32 a_mclk;
  249. u32 b_mclk;
  250. };
  251. struct fsi_master {
  252. void __iomem *base;
  253. struct fsi_priv fsia;
  254. struct fsi_priv fsib;
  255. const struct fsi_core *core;
  256. spinlock_t lock;
  257. };
  258. static int fsi_stream_is_play(struct fsi_priv *fsi, struct fsi_stream *io);
  259. /*
  260. * basic read write function
  261. */
  262. static void __fsi_reg_write(u32 __iomem *reg, u32 data)
  263. {
  264. /* valid data area is 24bit */
  265. data &= 0x00ffffff;
  266. __raw_writel(data, reg);
  267. }
  268. static u32 __fsi_reg_read(u32 __iomem *reg)
  269. {
  270. return __raw_readl(reg);
  271. }
  272. static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data)
  273. {
  274. u32 val = __fsi_reg_read(reg);
  275. val &= ~mask;
  276. val |= data & mask;
  277. __fsi_reg_write(reg, val);
  278. }
  279. #define fsi_reg_write(p, r, d)\
  280. __fsi_reg_write((p->base + REG_##r), d)
  281. #define fsi_reg_read(p, r)\
  282. __fsi_reg_read((p->base + REG_##r))
  283. #define fsi_reg_mask_set(p, r, m, d)\
  284. __fsi_reg_mask_set((p->base + REG_##r), m, d)
  285. #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r)
  286. #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r)
  287. static u32 _fsi_master_read(struct fsi_master *master, u32 reg)
  288. {
  289. u32 ret;
  290. unsigned long flags;
  291. spin_lock_irqsave(&master->lock, flags);
  292. ret = __fsi_reg_read(master->base + reg);
  293. spin_unlock_irqrestore(&master->lock, flags);
  294. return ret;
  295. }
  296. #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d)
  297. #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d)
  298. static void _fsi_master_mask_set(struct fsi_master *master,
  299. u32 reg, u32 mask, u32 data)
  300. {
  301. unsigned long flags;
  302. spin_lock_irqsave(&master->lock, flags);
  303. __fsi_reg_mask_set(master->base + reg, mask, data);
  304. spin_unlock_irqrestore(&master->lock, flags);
  305. }
  306. /*
  307. * basic function
  308. */
  309. static int fsi_version(struct fsi_master *master)
  310. {
  311. return master->core->ver;
  312. }
  313. static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
  314. {
  315. return fsi->master;
  316. }
  317. static int fsi_is_clk_master(struct fsi_priv *fsi)
  318. {
  319. return fsi->clk_master;
  320. }
  321. static int fsi_is_port_a(struct fsi_priv *fsi)
  322. {
  323. return fsi->master->base == fsi->base;
  324. }
  325. static int fsi_is_spdif(struct fsi_priv *fsi)
  326. {
  327. return fsi->spdif;
  328. }
  329. static int fsi_is_enable_stream(struct fsi_priv *fsi)
  330. {
  331. return fsi->enable_stream;
  332. }
  333. static int fsi_is_play(struct snd_pcm_substream *substream)
  334. {
  335. return substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
  336. }
  337. static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
  338. {
  339. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  340. return rtd->cpu_dai;
  341. }
  342. static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai)
  343. {
  344. struct fsi_master *master = snd_soc_dai_get_drvdata(dai);
  345. if (dai->id == 0)
  346. return &master->fsia;
  347. else
  348. return &master->fsib;
  349. }
  350. static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
  351. {
  352. return fsi_get_priv_frm_dai(fsi_get_dai(substream));
  353. }
  354. static u32 fsi_get_port_shift(struct fsi_priv *fsi, struct fsi_stream *io)
  355. {
  356. int is_play = fsi_stream_is_play(fsi, io);
  357. int is_porta = fsi_is_port_a(fsi);
  358. u32 shift;
  359. if (is_porta)
  360. shift = is_play ? AO_SHIFT : AI_SHIFT;
  361. else
  362. shift = is_play ? BO_SHIFT : BI_SHIFT;
  363. return shift;
  364. }
  365. static int fsi_frame2sample(struct fsi_priv *fsi, int frames)
  366. {
  367. return frames * fsi->chan_num;
  368. }
  369. static int fsi_sample2frame(struct fsi_priv *fsi, int samples)
  370. {
  371. return samples / fsi->chan_num;
  372. }
  373. static int fsi_get_current_fifo_samples(struct fsi_priv *fsi,
  374. struct fsi_stream *io)
  375. {
  376. int is_play = fsi_stream_is_play(fsi, io);
  377. u32 status;
  378. int frames;
  379. status = is_play ?
  380. fsi_reg_read(fsi, DOFF_ST) :
  381. fsi_reg_read(fsi, DIFF_ST);
  382. frames = 0x1ff & (status >> 8);
  383. return fsi_frame2sample(fsi, frames);
  384. }
  385. static void fsi_count_fifo_err(struct fsi_priv *fsi)
  386. {
  387. u32 ostatus = fsi_reg_read(fsi, DOFF_ST);
  388. u32 istatus = fsi_reg_read(fsi, DIFF_ST);
  389. if (ostatus & ERR_OVER)
  390. fsi->playback.oerr_num++;
  391. if (ostatus & ERR_UNDER)
  392. fsi->playback.uerr_num++;
  393. if (istatus & ERR_OVER)
  394. fsi->capture.oerr_num++;
  395. if (istatus & ERR_UNDER)
  396. fsi->capture.uerr_num++;
  397. fsi_reg_write(fsi, DOFF_ST, 0);
  398. fsi_reg_write(fsi, DIFF_ST, 0);
  399. }
  400. /*
  401. * fsi_stream_xx() function
  402. */
  403. static inline int fsi_stream_is_play(struct fsi_priv *fsi,
  404. struct fsi_stream *io)
  405. {
  406. return &fsi->playback == io;
  407. }
  408. static inline struct fsi_stream *fsi_stream_get(struct fsi_priv *fsi,
  409. struct snd_pcm_substream *substream)
  410. {
  411. return fsi_is_play(substream) ? &fsi->playback : &fsi->capture;
  412. }
  413. static int fsi_stream_is_working(struct fsi_priv *fsi,
  414. struct fsi_stream *io)
  415. {
  416. struct fsi_master *master = fsi_get_master(fsi);
  417. unsigned long flags;
  418. int ret;
  419. spin_lock_irqsave(&master->lock, flags);
  420. ret = !!(io->substream && io->substream->runtime);
  421. spin_unlock_irqrestore(&master->lock, flags);
  422. return ret;
  423. }
  424. static struct fsi_priv *fsi_stream_to_priv(struct fsi_stream *io)
  425. {
  426. return io->priv;
  427. }
  428. static void fsi_stream_init(struct fsi_priv *fsi,
  429. struct fsi_stream *io,
  430. struct snd_pcm_substream *substream)
  431. {
  432. struct snd_pcm_runtime *runtime = substream->runtime;
  433. struct fsi_master *master = fsi_get_master(fsi);
  434. unsigned long flags;
  435. spin_lock_irqsave(&master->lock, flags);
  436. io->substream = substream;
  437. io->buff_sample_capa = fsi_frame2sample(fsi, runtime->buffer_size);
  438. io->buff_sample_pos = 0;
  439. io->period_samples = fsi_frame2sample(fsi, runtime->period_size);
  440. io->period_pos = 0;
  441. io->sample_width = samples_to_bytes(runtime, 1);
  442. io->bus_option = 0;
  443. io->oerr_num = -1; /* ignore 1st err */
  444. io->uerr_num = -1; /* ignore 1st err */
  445. fsi_stream_handler_call(io, init, fsi, io);
  446. spin_unlock_irqrestore(&master->lock, flags);
  447. }
  448. static void fsi_stream_quit(struct fsi_priv *fsi, struct fsi_stream *io)
  449. {
  450. struct snd_soc_dai *dai = fsi_get_dai(io->substream);
  451. struct fsi_master *master = fsi_get_master(fsi);
  452. unsigned long flags;
  453. spin_lock_irqsave(&master->lock, flags);
  454. if (io->oerr_num > 0)
  455. dev_err(dai->dev, "over_run = %d\n", io->oerr_num);
  456. if (io->uerr_num > 0)
  457. dev_err(dai->dev, "under_run = %d\n", io->uerr_num);
  458. fsi_stream_handler_call(io, quit, fsi, io);
  459. io->substream = NULL;
  460. io->buff_sample_capa = 0;
  461. io->buff_sample_pos = 0;
  462. io->period_samples = 0;
  463. io->period_pos = 0;
  464. io->sample_width = 0;
  465. io->bus_option = 0;
  466. io->oerr_num = 0;
  467. io->uerr_num = 0;
  468. spin_unlock_irqrestore(&master->lock, flags);
  469. }
  470. static int fsi_stream_transfer(struct fsi_stream *io)
  471. {
  472. struct fsi_priv *fsi = fsi_stream_to_priv(io);
  473. if (!fsi)
  474. return -EIO;
  475. return fsi_stream_handler_call(io, transfer, fsi, io);
  476. }
  477. #define fsi_stream_start(fsi, io)\
  478. fsi_stream_handler_call(io, start_stop, fsi, io, 1)
  479. #define fsi_stream_stop(fsi, io)\
  480. fsi_stream_handler_call(io, start_stop, fsi, io, 0)
  481. static int fsi_stream_probe(struct fsi_priv *fsi, struct device *dev)
  482. {
  483. struct fsi_stream *io;
  484. int ret1, ret2;
  485. io = &fsi->playback;
  486. ret1 = fsi_stream_handler_call(io, probe, fsi, io, dev);
  487. io = &fsi->capture;
  488. ret2 = fsi_stream_handler_call(io, probe, fsi, io, dev);
  489. if (ret1 < 0)
  490. return ret1;
  491. if (ret2 < 0)
  492. return ret2;
  493. return 0;
  494. }
  495. static int fsi_stream_remove(struct fsi_priv *fsi)
  496. {
  497. struct fsi_stream *io;
  498. int ret1, ret2;
  499. io = &fsi->playback;
  500. ret1 = fsi_stream_handler_call(io, remove, fsi, io);
  501. io = &fsi->capture;
  502. ret2 = fsi_stream_handler_call(io, remove, fsi, io);
  503. if (ret1 < 0)
  504. return ret1;
  505. if (ret2 < 0)
  506. return ret2;
  507. return 0;
  508. }
  509. /*
  510. * format/bus/dma setting
  511. */
  512. static void fsi_format_bus_setup(struct fsi_priv *fsi, struct fsi_stream *io,
  513. u32 bus, struct device *dev)
  514. {
  515. struct fsi_master *master = fsi_get_master(fsi);
  516. int is_play = fsi_stream_is_play(fsi, io);
  517. u32 fmt = fsi->fmt;
  518. if (fsi_version(master) >= 2) {
  519. u32 dma = 0;
  520. /*
  521. * FSI2 needs DMA/Bus setting
  522. */
  523. switch (bus) {
  524. case PACKAGE_24BITBUS_FRONT:
  525. fmt |= CR_BWS_24;
  526. dma |= VDMD_FRONT;
  527. dev_dbg(dev, "24bit bus / package in front\n");
  528. break;
  529. case PACKAGE_16BITBUS_STREAM:
  530. fmt |= CR_BWS_16;
  531. dma |= VDMD_STREAM;
  532. dev_dbg(dev, "16bit bus / stream mode\n");
  533. break;
  534. case PACKAGE_24BITBUS_BACK:
  535. default:
  536. fmt |= CR_BWS_24;
  537. dma |= VDMD_BACK;
  538. dev_dbg(dev, "24bit bus / package in back\n");
  539. break;
  540. }
  541. if (is_play)
  542. fsi_reg_write(fsi, OUT_DMAC, dma);
  543. else
  544. fsi_reg_write(fsi, IN_DMAC, dma);
  545. }
  546. if (is_play)
  547. fsi_reg_write(fsi, DO_FMT, fmt);
  548. else
  549. fsi_reg_write(fsi, DI_FMT, fmt);
  550. }
  551. /*
  552. * irq function
  553. */
  554. static void fsi_irq_enable(struct fsi_priv *fsi, struct fsi_stream *io)
  555. {
  556. u32 data = AB_IO(1, fsi_get_port_shift(fsi, io));
  557. struct fsi_master *master = fsi_get_master(fsi);
  558. fsi_core_mask_set(master, imsk, data, data);
  559. fsi_core_mask_set(master, iemsk, data, data);
  560. }
  561. static void fsi_irq_disable(struct fsi_priv *fsi, struct fsi_stream *io)
  562. {
  563. u32 data = AB_IO(1, fsi_get_port_shift(fsi, io));
  564. struct fsi_master *master = fsi_get_master(fsi);
  565. fsi_core_mask_set(master, imsk, data, 0);
  566. fsi_core_mask_set(master, iemsk, data, 0);
  567. }
  568. static u32 fsi_irq_get_status(struct fsi_master *master)
  569. {
  570. return fsi_core_read(master, int_st);
  571. }
  572. static void fsi_irq_clear_status(struct fsi_priv *fsi)
  573. {
  574. u32 data = 0;
  575. struct fsi_master *master = fsi_get_master(fsi);
  576. data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->playback));
  577. data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->capture));
  578. /* clear interrupt factor */
  579. fsi_core_mask_set(master, int_st, data, 0);
  580. }
  581. /*
  582. * SPDIF master clock function
  583. *
  584. * These functions are used later FSI2
  585. */
  586. static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable)
  587. {
  588. struct fsi_master *master = fsi_get_master(fsi);
  589. u32 mask, val;
  590. mask = BP | SE;
  591. val = enable ? mask : 0;
  592. fsi_is_port_a(fsi) ?
  593. fsi_core_mask_set(master, a_mclk, mask, val) :
  594. fsi_core_mask_set(master, b_mclk, mask, val);
  595. }
  596. /*
  597. * clock function
  598. */
  599. static int fsi_clk_init(struct device *dev,
  600. struct fsi_priv *fsi,
  601. int xck,
  602. int ick,
  603. int div,
  604. int (*set_rate)(struct device *dev,
  605. struct fsi_priv *fsi))
  606. {
  607. struct fsi_clk *clock = &fsi->clock;
  608. int is_porta = fsi_is_port_a(fsi);
  609. clock->xck = NULL;
  610. clock->ick = NULL;
  611. clock->div = NULL;
  612. clock->rate = 0;
  613. clock->count = 0;
  614. clock->set_rate = set_rate;
  615. clock->own = devm_clk_get(dev, NULL);
  616. if (IS_ERR(clock->own))
  617. return -EINVAL;
  618. /* external clock */
  619. if (xck) {
  620. clock->xck = devm_clk_get(dev, is_porta ? "xcka" : "xckb");
  621. if (IS_ERR(clock->xck)) {
  622. dev_err(dev, "can't get xck clock\n");
  623. return -EINVAL;
  624. }
  625. if (clock->xck == clock->own) {
  626. dev_err(dev, "cpu doesn't support xck clock\n");
  627. return -EINVAL;
  628. }
  629. }
  630. /* FSIACLK/FSIBCLK */
  631. if (ick) {
  632. clock->ick = devm_clk_get(dev, is_porta ? "icka" : "ickb");
  633. if (IS_ERR(clock->ick)) {
  634. dev_err(dev, "can't get ick clock\n");
  635. return -EINVAL;
  636. }
  637. if (clock->ick == clock->own) {
  638. dev_err(dev, "cpu doesn't support ick clock\n");
  639. return -EINVAL;
  640. }
  641. }
  642. /* FSI-DIV */
  643. if (div) {
  644. clock->div = devm_clk_get(dev, is_porta ? "diva" : "divb");
  645. if (IS_ERR(clock->div)) {
  646. dev_err(dev, "can't get div clock\n");
  647. return -EINVAL;
  648. }
  649. if (clock->div == clock->own) {
  650. dev_err(dev, "cpu doens't support div clock\n");
  651. return -EINVAL;
  652. }
  653. }
  654. return 0;
  655. }
  656. #define fsi_clk_invalid(fsi) fsi_clk_valid(fsi, 0)
  657. static void fsi_clk_valid(struct fsi_priv *fsi, unsigned long rate)
  658. {
  659. fsi->clock.rate = rate;
  660. }
  661. static int fsi_clk_is_valid(struct fsi_priv *fsi)
  662. {
  663. return fsi->clock.set_rate &&
  664. fsi->clock.rate;
  665. }
  666. static int fsi_clk_enable(struct device *dev,
  667. struct fsi_priv *fsi)
  668. {
  669. struct fsi_clk *clock = &fsi->clock;
  670. int ret = -EINVAL;
  671. if (!fsi_clk_is_valid(fsi))
  672. return ret;
  673. if (0 == clock->count) {
  674. ret = clock->set_rate(dev, fsi);
  675. if (ret < 0) {
  676. fsi_clk_invalid(fsi);
  677. return ret;
  678. }
  679. clk_enable(clock->xck);
  680. clk_enable(clock->ick);
  681. clk_enable(clock->div);
  682. clock->count++;
  683. }
  684. return ret;
  685. }
  686. static int fsi_clk_disable(struct device *dev,
  687. struct fsi_priv *fsi)
  688. {
  689. struct fsi_clk *clock = &fsi->clock;
  690. if (!fsi_clk_is_valid(fsi))
  691. return -EINVAL;
  692. if (1 == clock->count--) {
  693. clk_disable(clock->xck);
  694. clk_disable(clock->ick);
  695. clk_disable(clock->div);
  696. }
  697. return 0;
  698. }
  699. static int fsi_clk_set_ackbpf(struct device *dev,
  700. struct fsi_priv *fsi,
  701. int ackmd, int bpfmd)
  702. {
  703. u32 data = 0;
  704. /* check ackmd/bpfmd relationship */
  705. if (bpfmd > ackmd) {
  706. dev_err(dev, "unsupported rate (%d/%d)\n", ackmd, bpfmd);
  707. return -EINVAL;
  708. }
  709. /* ACKMD */
  710. switch (ackmd) {
  711. case 512:
  712. data |= (0x0 << 12);
  713. break;
  714. case 256:
  715. data |= (0x1 << 12);
  716. break;
  717. case 128:
  718. data |= (0x2 << 12);
  719. break;
  720. case 64:
  721. data |= (0x3 << 12);
  722. break;
  723. case 32:
  724. data |= (0x4 << 12);
  725. break;
  726. default:
  727. dev_err(dev, "unsupported ackmd (%d)\n", ackmd);
  728. return -EINVAL;
  729. }
  730. /* BPFMD */
  731. switch (bpfmd) {
  732. case 32:
  733. data |= (0x0 << 8);
  734. break;
  735. case 64:
  736. data |= (0x1 << 8);
  737. break;
  738. case 128:
  739. data |= (0x2 << 8);
  740. break;
  741. case 256:
  742. data |= (0x3 << 8);
  743. break;
  744. case 512:
  745. data |= (0x4 << 8);
  746. break;
  747. case 16:
  748. data |= (0x7 << 8);
  749. break;
  750. default:
  751. dev_err(dev, "unsupported bpfmd (%d)\n", bpfmd);
  752. return -EINVAL;
  753. }
  754. dev_dbg(dev, "ACKMD/BPFMD = %d/%d\n", ackmd, bpfmd);
  755. fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data);
  756. udelay(10);
  757. return 0;
  758. }
  759. static int fsi_clk_set_rate_external(struct device *dev,
  760. struct fsi_priv *fsi)
  761. {
  762. struct clk *xck = fsi->clock.xck;
  763. struct clk *ick = fsi->clock.ick;
  764. unsigned long rate = fsi->clock.rate;
  765. unsigned long xrate;
  766. int ackmd, bpfmd;
  767. int ret = 0;
  768. /* check clock rate */
  769. xrate = clk_get_rate(xck);
  770. if (xrate % rate) {
  771. dev_err(dev, "unsupported clock rate\n");
  772. return -EINVAL;
  773. }
  774. clk_set_parent(ick, xck);
  775. clk_set_rate(ick, xrate);
  776. bpfmd = fsi->chan_num * 32;
  777. ackmd = xrate / rate;
  778. dev_dbg(dev, "external/rate = %ld/%ld\n", xrate, rate);
  779. ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd);
  780. if (ret < 0)
  781. dev_err(dev, "%s failed", __func__);
  782. return ret;
  783. }
  784. static int fsi_clk_set_rate_cpg(struct device *dev,
  785. struct fsi_priv *fsi)
  786. {
  787. struct clk *ick = fsi->clock.ick;
  788. struct clk *div = fsi->clock.div;
  789. unsigned long rate = fsi->clock.rate;
  790. unsigned long target = 0; /* 12288000 or 11289600 */
  791. unsigned long actual, cout;
  792. unsigned long diff, min;
  793. unsigned long best_cout, best_act;
  794. int adj;
  795. int ackmd, bpfmd;
  796. int ret = -EINVAL;
  797. if (!(12288000 % rate))
  798. target = 12288000;
  799. if (!(11289600 % rate))
  800. target = 11289600;
  801. if (!target) {
  802. dev_err(dev, "unsupported rate\n");
  803. return ret;
  804. }
  805. bpfmd = fsi->chan_num * 32;
  806. ackmd = target / rate;
  807. ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd);
  808. if (ret < 0) {
  809. dev_err(dev, "%s failed", __func__);
  810. return ret;
  811. }
  812. /*
  813. * The clock flow is
  814. *
  815. * [CPG] = cout => [FSI_DIV] = audio => [FSI] => [codec]
  816. *
  817. * But, it needs to find best match of CPG and FSI_DIV
  818. * combination, since it is difficult to generate correct
  819. * frequency of audio clock from ick clock only.
  820. * Because ick is created from its parent clock.
  821. *
  822. * target = rate x [512/256/128/64]fs
  823. * cout = round(target x adjustment)
  824. * actual = cout / adjustment (by FSI-DIV) ~= target
  825. * audio = actual
  826. */
  827. min = ~0;
  828. best_cout = 0;
  829. best_act = 0;
  830. for (adj = 1; adj < 0xffff; adj++) {
  831. cout = target * adj;
  832. if (cout > 100000000) /* max clock = 100MHz */
  833. break;
  834. /* cout/actual audio clock */
  835. cout = clk_round_rate(ick, cout);
  836. actual = cout / adj;
  837. /* find best frequency */
  838. diff = abs(actual - target);
  839. if (diff < min) {
  840. min = diff;
  841. best_cout = cout;
  842. best_act = actual;
  843. }
  844. }
  845. ret = clk_set_rate(ick, best_cout);
  846. if (ret < 0) {
  847. dev_err(dev, "ick clock failed\n");
  848. return -EIO;
  849. }
  850. ret = clk_set_rate(div, clk_round_rate(div, best_act));
  851. if (ret < 0) {
  852. dev_err(dev, "div clock failed\n");
  853. return -EIO;
  854. }
  855. dev_dbg(dev, "ick/div = %ld/%ld\n",
  856. clk_get_rate(ick), clk_get_rate(div));
  857. return ret;
  858. }
  859. static void fsi_pointer_update(struct fsi_stream *io, int size)
  860. {
  861. io->buff_sample_pos += size;
  862. if (io->buff_sample_pos >=
  863. io->period_samples * (io->period_pos + 1)) {
  864. struct snd_pcm_substream *substream = io->substream;
  865. struct snd_pcm_runtime *runtime = substream->runtime;
  866. io->period_pos++;
  867. if (io->period_pos >= runtime->periods) {
  868. io->buff_sample_pos = 0;
  869. io->period_pos = 0;
  870. }
  871. snd_pcm_period_elapsed(substream);
  872. }
  873. }
  874. /*
  875. * pio data transfer handler
  876. */
  877. static void fsi_pio_push16(struct fsi_priv *fsi, u8 *_buf, int samples)
  878. {
  879. int i;
  880. if (fsi_is_enable_stream(fsi)) {
  881. /*
  882. * stream mode
  883. * see
  884. * fsi_pio_push_init()
  885. */
  886. u32 *buf = (u32 *)_buf;
  887. for (i = 0; i < samples / 2; i++)
  888. fsi_reg_write(fsi, DODT, buf[i]);
  889. } else {
  890. /* normal mode */
  891. u16 *buf = (u16 *)_buf;
  892. for (i = 0; i < samples; i++)
  893. fsi_reg_write(fsi, DODT, ((u32)*(buf + i) << 8));
  894. }
  895. }
  896. static void fsi_pio_pop16(struct fsi_priv *fsi, u8 *_buf, int samples)
  897. {
  898. u16 *buf = (u16 *)_buf;
  899. int i;
  900. for (i = 0; i < samples; i++)
  901. *(buf + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8);
  902. }
  903. static void fsi_pio_push32(struct fsi_priv *fsi, u8 *_buf, int samples)
  904. {
  905. u32 *buf = (u32 *)_buf;
  906. int i;
  907. for (i = 0; i < samples; i++)
  908. fsi_reg_write(fsi, DODT, *(buf + i));
  909. }
  910. static void fsi_pio_pop32(struct fsi_priv *fsi, u8 *_buf, int samples)
  911. {
  912. u32 *buf = (u32 *)_buf;
  913. int i;
  914. for (i = 0; i < samples; i++)
  915. *(buf + i) = fsi_reg_read(fsi, DIDT);
  916. }
  917. static u8 *fsi_pio_get_area(struct fsi_priv *fsi, struct fsi_stream *io)
  918. {
  919. struct snd_pcm_runtime *runtime = io->substream->runtime;
  920. return runtime->dma_area +
  921. samples_to_bytes(runtime, io->buff_sample_pos);
  922. }
  923. static int fsi_pio_transfer(struct fsi_priv *fsi, struct fsi_stream *io,
  924. void (*run16)(struct fsi_priv *fsi, u8 *buf, int samples),
  925. void (*run32)(struct fsi_priv *fsi, u8 *buf, int samples),
  926. int samples)
  927. {
  928. u8 *buf;
  929. if (!fsi_stream_is_working(fsi, io))
  930. return -EINVAL;
  931. buf = fsi_pio_get_area(fsi, io);
  932. switch (io->sample_width) {
  933. case 2:
  934. run16(fsi, buf, samples);
  935. break;
  936. case 4:
  937. run32(fsi, buf, samples);
  938. break;
  939. default:
  940. return -EINVAL;
  941. }
  942. fsi_pointer_update(io, samples);
  943. return 0;
  944. }
  945. static int fsi_pio_pop(struct fsi_priv *fsi, struct fsi_stream *io)
  946. {
  947. int sample_residues; /* samples in FSI fifo */
  948. int sample_space; /* ALSA free samples space */
  949. int samples;
  950. sample_residues = fsi_get_current_fifo_samples(fsi, io);
  951. sample_space = io->buff_sample_capa - io->buff_sample_pos;
  952. samples = min(sample_residues, sample_space);
  953. return fsi_pio_transfer(fsi, io,
  954. fsi_pio_pop16,
  955. fsi_pio_pop32,
  956. samples);
  957. }
  958. static int fsi_pio_push(struct fsi_priv *fsi, struct fsi_stream *io)
  959. {
  960. int sample_residues; /* ALSA residue samples */
  961. int sample_space; /* FSI fifo free samples space */
  962. int samples;
  963. sample_residues = io->buff_sample_capa - io->buff_sample_pos;
  964. sample_space = io->fifo_sample_capa -
  965. fsi_get_current_fifo_samples(fsi, io);
  966. samples = min(sample_residues, sample_space);
  967. return fsi_pio_transfer(fsi, io,
  968. fsi_pio_push16,
  969. fsi_pio_push32,
  970. samples);
  971. }
  972. static int fsi_pio_start_stop(struct fsi_priv *fsi, struct fsi_stream *io,
  973. int enable)
  974. {
  975. struct fsi_master *master = fsi_get_master(fsi);
  976. u32 clk = fsi_is_port_a(fsi) ? CRA : CRB;
  977. if (enable)
  978. fsi_irq_enable(fsi, io);
  979. else
  980. fsi_irq_disable(fsi, io);
  981. if (fsi_is_clk_master(fsi))
  982. fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0);
  983. return 0;
  984. }
  985. static int fsi_pio_push_init(struct fsi_priv *fsi, struct fsi_stream *io)
  986. {
  987. /*
  988. * we can use 16bit stream mode
  989. * when "playback" and "16bit data"
  990. * and platform allows "stream mode"
  991. * see
  992. * fsi_pio_push16()
  993. */
  994. if (fsi_is_enable_stream(fsi))
  995. io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
  996. BUSOP_SET(16, PACKAGE_16BITBUS_STREAM);
  997. else
  998. io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
  999. BUSOP_SET(16, PACKAGE_24BITBUS_BACK);
  1000. return 0;
  1001. }
  1002. static int fsi_pio_pop_init(struct fsi_priv *fsi, struct fsi_stream *io)
  1003. {
  1004. /*
  1005. * always 24bit bus, package back when "capture"
  1006. */
  1007. io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
  1008. BUSOP_SET(16, PACKAGE_24BITBUS_BACK);
  1009. return 0;
  1010. }
  1011. static struct fsi_stream_handler fsi_pio_push_handler = {
  1012. .init = fsi_pio_push_init,
  1013. .transfer = fsi_pio_push,
  1014. .start_stop = fsi_pio_start_stop,
  1015. };
  1016. static struct fsi_stream_handler fsi_pio_pop_handler = {
  1017. .init = fsi_pio_pop_init,
  1018. .transfer = fsi_pio_pop,
  1019. .start_stop = fsi_pio_start_stop,
  1020. };
  1021. static irqreturn_t fsi_interrupt(int irq, void *data)
  1022. {
  1023. struct fsi_master *master = data;
  1024. u32 int_st = fsi_irq_get_status(master);
  1025. /* clear irq status */
  1026. fsi_master_mask_set(master, SOFT_RST, IR, 0);
  1027. fsi_master_mask_set(master, SOFT_RST, IR, IR);
  1028. if (int_st & AB_IO(1, AO_SHIFT))
  1029. fsi_stream_transfer(&master->fsia.playback);
  1030. if (int_st & AB_IO(1, BO_SHIFT))
  1031. fsi_stream_transfer(&master->fsib.playback);
  1032. if (int_st & AB_IO(1, AI_SHIFT))
  1033. fsi_stream_transfer(&master->fsia.capture);
  1034. if (int_st & AB_IO(1, BI_SHIFT))
  1035. fsi_stream_transfer(&master->fsib.capture);
  1036. fsi_count_fifo_err(&master->fsia);
  1037. fsi_count_fifo_err(&master->fsib);
  1038. fsi_irq_clear_status(&master->fsia);
  1039. fsi_irq_clear_status(&master->fsib);
  1040. return IRQ_HANDLED;
  1041. }
  1042. /*
  1043. * dma data transfer handler
  1044. */
  1045. static int fsi_dma_init(struct fsi_priv *fsi, struct fsi_stream *io)
  1046. {
  1047. /*
  1048. * 24bit data : 24bit bus / package in back
  1049. * 16bit data : 16bit bus / stream mode
  1050. */
  1051. io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
  1052. BUSOP_SET(16, PACKAGE_16BITBUS_STREAM);
  1053. return 0;
  1054. }
  1055. static void fsi_dma_complete(void *data)
  1056. {
  1057. struct fsi_stream *io = (struct fsi_stream *)data;
  1058. struct fsi_priv *fsi = fsi_stream_to_priv(io);
  1059. fsi_pointer_update(io, io->period_samples);
  1060. fsi_count_fifo_err(fsi);
  1061. }
  1062. static int fsi_dma_transfer(struct fsi_priv *fsi, struct fsi_stream *io)
  1063. {
  1064. struct snd_soc_dai *dai = fsi_get_dai(io->substream);
  1065. struct snd_pcm_substream *substream = io->substream;
  1066. struct dma_async_tx_descriptor *desc;
  1067. int is_play = fsi_stream_is_play(fsi, io);
  1068. enum dma_transfer_direction dir;
  1069. int ret = -EIO;
  1070. if (is_play)
  1071. dir = DMA_MEM_TO_DEV;
  1072. else
  1073. dir = DMA_DEV_TO_MEM;
  1074. desc = dmaengine_prep_dma_cyclic(io->chan,
  1075. substream->runtime->dma_addr,
  1076. snd_pcm_lib_buffer_bytes(substream),
  1077. snd_pcm_lib_period_bytes(substream),
  1078. dir,
  1079. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  1080. if (!desc) {
  1081. dev_err(dai->dev, "dmaengine_prep_dma_cyclic() fail\n");
  1082. goto fsi_dma_transfer_err;
  1083. }
  1084. desc->callback = fsi_dma_complete;
  1085. desc->callback_param = io;
  1086. if (dmaengine_submit(desc) < 0) {
  1087. dev_err(dai->dev, "tx_submit() fail\n");
  1088. goto fsi_dma_transfer_err;
  1089. }
  1090. dma_async_issue_pending(io->chan);
  1091. /*
  1092. * FIXME
  1093. *
  1094. * In DMAEngine case, codec and FSI cannot be started simultaneously
  1095. * since FSI is using the scheduler work queue.
  1096. * Therefore, in capture case, probably FSI FIFO will have got
  1097. * overflow error in this point.
  1098. * in that case, DMA cannot start transfer until error was cleared.
  1099. */
  1100. if (!is_play) {
  1101. if (ERR_OVER & fsi_reg_read(fsi, DIFF_ST)) {
  1102. fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
  1103. fsi_reg_write(fsi, DIFF_ST, 0);
  1104. }
  1105. }
  1106. ret = 0;
  1107. fsi_dma_transfer_err:
  1108. return ret;
  1109. }
  1110. static int fsi_dma_push_start_stop(struct fsi_priv *fsi, struct fsi_stream *io,
  1111. int start)
  1112. {
  1113. struct fsi_master *master = fsi_get_master(fsi);
  1114. u32 clk = fsi_is_port_a(fsi) ? CRA : CRB;
  1115. u32 enable = start ? DMA_ON : 0;
  1116. fsi_reg_mask_set(fsi, OUT_DMAC, DMA_ON, enable);
  1117. dmaengine_terminate_all(io->chan);
  1118. if (fsi_is_clk_master(fsi))
  1119. fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0);
  1120. return 0;
  1121. }
  1122. static int fsi_dma_probe(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev)
  1123. {
  1124. dma_cap_mask_t mask;
  1125. int is_play = fsi_stream_is_play(fsi, io);
  1126. dma_cap_zero(mask);
  1127. dma_cap_set(DMA_SLAVE, mask);
  1128. io->chan = dma_request_slave_channel_compat(mask,
  1129. shdma_chan_filter, (void *)io->dma_id,
  1130. dev, is_play ? "tx" : "rx");
  1131. if (io->chan) {
  1132. struct dma_slave_config cfg = {};
  1133. int ret;
  1134. if (is_play) {
  1135. cfg.dst_addr = fsi->phys + REG_DODT;
  1136. cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  1137. cfg.direction = DMA_MEM_TO_DEV;
  1138. } else {
  1139. cfg.src_addr = fsi->phys + REG_DIDT;
  1140. cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  1141. cfg.direction = DMA_DEV_TO_MEM;
  1142. }
  1143. ret = dmaengine_slave_config(io->chan, &cfg);
  1144. if (ret < 0) {
  1145. dma_release_channel(io->chan);
  1146. io->chan = NULL;
  1147. }
  1148. }
  1149. if (!io->chan) {
  1150. /* switch to PIO handler */
  1151. if (is_play)
  1152. fsi->playback.handler = &fsi_pio_push_handler;
  1153. else
  1154. fsi->capture.handler = &fsi_pio_pop_handler;
  1155. dev_info(dev, "switch handler (dma => pio)\n");
  1156. /* probe again */
  1157. return fsi_stream_probe(fsi, dev);
  1158. }
  1159. return 0;
  1160. }
  1161. static int fsi_dma_remove(struct fsi_priv *fsi, struct fsi_stream *io)
  1162. {
  1163. fsi_stream_stop(fsi, io);
  1164. if (io->chan)
  1165. dma_release_channel(io->chan);
  1166. io->chan = NULL;
  1167. return 0;
  1168. }
  1169. static struct fsi_stream_handler fsi_dma_push_handler = {
  1170. .init = fsi_dma_init,
  1171. .probe = fsi_dma_probe,
  1172. .transfer = fsi_dma_transfer,
  1173. .remove = fsi_dma_remove,
  1174. .start_stop = fsi_dma_push_start_stop,
  1175. };
  1176. /*
  1177. * dai ops
  1178. */
  1179. static void fsi_fifo_init(struct fsi_priv *fsi,
  1180. struct fsi_stream *io,
  1181. struct device *dev)
  1182. {
  1183. struct fsi_master *master = fsi_get_master(fsi);
  1184. int is_play = fsi_stream_is_play(fsi, io);
  1185. u32 shift, i;
  1186. int frame_capa;
  1187. /* get on-chip RAM capacity */
  1188. shift = fsi_master_read(master, FIFO_SZ);
  1189. shift >>= fsi_get_port_shift(fsi, io);
  1190. shift &= FIFO_SZ_MASK;
  1191. frame_capa = 256 << shift;
  1192. dev_dbg(dev, "fifo = %d words\n", frame_capa);
  1193. /*
  1194. * The maximum number of sample data varies depending
  1195. * on the number of channels selected for the format.
  1196. *
  1197. * FIFOs are used in 4-channel units in 3-channel mode
  1198. * and in 8-channel units in 5- to 7-channel mode
  1199. * meaning that more FIFOs than the required size of DPRAM
  1200. * are used.
  1201. *
  1202. * ex) if 256 words of DP-RAM is connected
  1203. * 1 channel: 256 (256 x 1 = 256)
  1204. * 2 channels: 128 (128 x 2 = 256)
  1205. * 3 channels: 64 ( 64 x 3 = 192)
  1206. * 4 channels: 64 ( 64 x 4 = 256)
  1207. * 5 channels: 32 ( 32 x 5 = 160)
  1208. * 6 channels: 32 ( 32 x 6 = 192)
  1209. * 7 channels: 32 ( 32 x 7 = 224)
  1210. * 8 channels: 32 ( 32 x 8 = 256)
  1211. */
  1212. for (i = 1; i < fsi->chan_num; i <<= 1)
  1213. frame_capa >>= 1;
  1214. dev_dbg(dev, "%d channel %d store\n",
  1215. fsi->chan_num, frame_capa);
  1216. io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa);
  1217. /*
  1218. * set interrupt generation factor
  1219. * clear FIFO
  1220. */
  1221. if (is_play) {
  1222. fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF);
  1223. fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR);
  1224. } else {
  1225. fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF);
  1226. fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
  1227. }
  1228. }
  1229. static int fsi_hw_startup(struct fsi_priv *fsi,
  1230. struct fsi_stream *io,
  1231. struct device *dev)
  1232. {
  1233. u32 data = 0;
  1234. /* clock setting */
  1235. if (fsi_is_clk_master(fsi))
  1236. data = DIMD | DOMD;
  1237. fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data);
  1238. /* clock inversion (CKG2) */
  1239. data = 0;
  1240. if (fsi->bit_clk_inv)
  1241. data |= (1 << 0);
  1242. if (fsi->lr_clk_inv)
  1243. data |= (1 << 4);
  1244. if (fsi_is_clk_master(fsi))
  1245. data <<= 8;
  1246. fsi_reg_write(fsi, CKG2, data);
  1247. /* spdif ? */
  1248. if (fsi_is_spdif(fsi)) {
  1249. fsi_spdif_clk_ctrl(fsi, 1);
  1250. fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD);
  1251. }
  1252. /*
  1253. * get bus settings
  1254. */
  1255. data = 0;
  1256. switch (io->sample_width) {
  1257. case 2:
  1258. data = BUSOP_GET(16, io->bus_option);
  1259. break;
  1260. case 4:
  1261. data = BUSOP_GET(24, io->bus_option);
  1262. break;
  1263. }
  1264. fsi_format_bus_setup(fsi, io, data, dev);
  1265. /* irq clear */
  1266. fsi_irq_disable(fsi, io);
  1267. fsi_irq_clear_status(fsi);
  1268. /* fifo init */
  1269. fsi_fifo_init(fsi, io, dev);
  1270. /* start master clock */
  1271. if (fsi_is_clk_master(fsi))
  1272. return fsi_clk_enable(dev, fsi);
  1273. return 0;
  1274. }
  1275. static int fsi_hw_shutdown(struct fsi_priv *fsi,
  1276. struct device *dev)
  1277. {
  1278. /* stop master clock */
  1279. if (fsi_is_clk_master(fsi))
  1280. return fsi_clk_disable(dev, fsi);
  1281. return 0;
  1282. }
  1283. static int fsi_dai_startup(struct snd_pcm_substream *substream,
  1284. struct snd_soc_dai *dai)
  1285. {
  1286. struct fsi_priv *fsi = fsi_get_priv(substream);
  1287. fsi_clk_invalid(fsi);
  1288. return 0;
  1289. }
  1290. static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
  1291. struct snd_soc_dai *dai)
  1292. {
  1293. struct fsi_priv *fsi = fsi_get_priv(substream);
  1294. fsi_clk_invalid(fsi);
  1295. }
  1296. static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
  1297. struct snd_soc_dai *dai)
  1298. {
  1299. struct fsi_priv *fsi = fsi_get_priv(substream);
  1300. struct fsi_stream *io = fsi_stream_get(fsi, substream);
  1301. int ret = 0;
  1302. switch (cmd) {
  1303. case SNDRV_PCM_TRIGGER_START:
  1304. fsi_stream_init(fsi, io, substream);
  1305. if (!ret)
  1306. ret = fsi_hw_startup(fsi, io, dai->dev);
  1307. if (!ret)
  1308. ret = fsi_stream_start(fsi, io);
  1309. if (!ret)
  1310. ret = fsi_stream_transfer(io);
  1311. break;
  1312. case SNDRV_PCM_TRIGGER_STOP:
  1313. if (!ret)
  1314. ret = fsi_hw_shutdown(fsi, dai->dev);
  1315. fsi_stream_stop(fsi, io);
  1316. fsi_stream_quit(fsi, io);
  1317. break;
  1318. }
  1319. return ret;
  1320. }
  1321. static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt)
  1322. {
  1323. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1324. case SND_SOC_DAIFMT_I2S:
  1325. fsi->fmt = CR_I2S;
  1326. fsi->chan_num = 2;
  1327. break;
  1328. case SND_SOC_DAIFMT_LEFT_J:
  1329. fsi->fmt = CR_PCM;
  1330. fsi->chan_num = 2;
  1331. break;
  1332. default:
  1333. return -EINVAL;
  1334. }
  1335. return 0;
  1336. }
  1337. static int fsi_set_fmt_spdif(struct fsi_priv *fsi)
  1338. {
  1339. struct fsi_master *master = fsi_get_master(fsi);
  1340. if (fsi_version(master) < 2)
  1341. return -EINVAL;
  1342. fsi->fmt = CR_DTMD_SPDIF_PCM | CR_PCM;
  1343. fsi->chan_num = 2;
  1344. return 0;
  1345. }
  1346. static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  1347. {
  1348. struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai);
  1349. int ret;
  1350. /* set master/slave audio interface */
  1351. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1352. case SND_SOC_DAIFMT_CBM_CFM:
  1353. break;
  1354. case SND_SOC_DAIFMT_CBS_CFS:
  1355. fsi->clk_master = 1; /* codec is slave, cpu is master */
  1356. break;
  1357. default:
  1358. return -EINVAL;
  1359. }
  1360. /* set clock inversion */
  1361. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1362. case SND_SOC_DAIFMT_NB_IF:
  1363. fsi->bit_clk_inv = 0;
  1364. fsi->lr_clk_inv = 1;
  1365. break;
  1366. case SND_SOC_DAIFMT_IB_NF:
  1367. fsi->bit_clk_inv = 1;
  1368. fsi->lr_clk_inv = 0;
  1369. break;
  1370. case SND_SOC_DAIFMT_IB_IF:
  1371. fsi->bit_clk_inv = 1;
  1372. fsi->lr_clk_inv = 1;
  1373. break;
  1374. case SND_SOC_DAIFMT_NB_NF:
  1375. default:
  1376. fsi->bit_clk_inv = 0;
  1377. fsi->lr_clk_inv = 0;
  1378. break;
  1379. }
  1380. if (fsi_is_clk_master(fsi)) {
  1381. if (fsi->clk_cpg)
  1382. fsi_clk_init(dai->dev, fsi, 0, 1, 1,
  1383. fsi_clk_set_rate_cpg);
  1384. else
  1385. fsi_clk_init(dai->dev, fsi, 1, 1, 0,
  1386. fsi_clk_set_rate_external);
  1387. }
  1388. /* set format */
  1389. if (fsi_is_spdif(fsi))
  1390. ret = fsi_set_fmt_spdif(fsi);
  1391. else
  1392. ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK);
  1393. return ret;
  1394. }
  1395. static int fsi_dai_hw_params(struct snd_pcm_substream *substream,
  1396. struct snd_pcm_hw_params *params,
  1397. struct snd_soc_dai *dai)
  1398. {
  1399. struct fsi_priv *fsi = fsi_get_priv(substream);
  1400. if (fsi_is_clk_master(fsi))
  1401. fsi_clk_valid(fsi, params_rate(params));
  1402. return 0;
  1403. }
  1404. static const struct snd_soc_dai_ops fsi_dai_ops = {
  1405. .startup = fsi_dai_startup,
  1406. .shutdown = fsi_dai_shutdown,
  1407. .trigger = fsi_dai_trigger,
  1408. .set_fmt = fsi_dai_set_fmt,
  1409. .hw_params = fsi_dai_hw_params,
  1410. };
  1411. /*
  1412. * pcm ops
  1413. */
  1414. static struct snd_pcm_hardware fsi_pcm_hardware = {
  1415. .info = SNDRV_PCM_INFO_INTERLEAVED |
  1416. SNDRV_PCM_INFO_MMAP |
  1417. SNDRV_PCM_INFO_MMAP_VALID,
  1418. .buffer_bytes_max = 64 * 1024,
  1419. .period_bytes_min = 32,
  1420. .period_bytes_max = 8192,
  1421. .periods_min = 1,
  1422. .periods_max = 32,
  1423. .fifo_size = 256,
  1424. };
  1425. static int fsi_pcm_open(struct snd_pcm_substream *substream)
  1426. {
  1427. struct snd_pcm_runtime *runtime = substream->runtime;
  1428. int ret = 0;
  1429. snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
  1430. ret = snd_pcm_hw_constraint_integer(runtime,
  1431. SNDRV_PCM_HW_PARAM_PERIODS);
  1432. return ret;
  1433. }
  1434. static int fsi_hw_params(struct snd_pcm_substream *substream,
  1435. struct snd_pcm_hw_params *hw_params)
  1436. {
  1437. return snd_pcm_lib_malloc_pages(substream,
  1438. params_buffer_bytes(hw_params));
  1439. }
  1440. static int fsi_hw_free(struct snd_pcm_substream *substream)
  1441. {
  1442. return snd_pcm_lib_free_pages(substream);
  1443. }
  1444. static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream)
  1445. {
  1446. struct fsi_priv *fsi = fsi_get_priv(substream);
  1447. struct fsi_stream *io = fsi_stream_get(fsi, substream);
  1448. return fsi_sample2frame(fsi, io->buff_sample_pos);
  1449. }
  1450. static struct snd_pcm_ops fsi_pcm_ops = {
  1451. .open = fsi_pcm_open,
  1452. .ioctl = snd_pcm_lib_ioctl,
  1453. .hw_params = fsi_hw_params,
  1454. .hw_free = fsi_hw_free,
  1455. .pointer = fsi_pointer,
  1456. };
  1457. /*
  1458. * snd_soc_platform
  1459. */
  1460. #define PREALLOC_BUFFER (32 * 1024)
  1461. #define PREALLOC_BUFFER_MAX (32 * 1024)
  1462. static int fsi_pcm_new(struct snd_soc_pcm_runtime *rtd)
  1463. {
  1464. return snd_pcm_lib_preallocate_pages_for_all(
  1465. rtd->pcm,
  1466. SNDRV_DMA_TYPE_DEV,
  1467. rtd->card->snd_card->dev,
  1468. PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
  1469. }
  1470. /*
  1471. * alsa struct
  1472. */
  1473. static struct snd_soc_dai_driver fsi_soc_dai[] = {
  1474. {
  1475. .name = "fsia-dai",
  1476. .playback = {
  1477. .rates = FSI_RATES,
  1478. .formats = FSI_FMTS,
  1479. .channels_min = 2,
  1480. .channels_max = 2,
  1481. },
  1482. .capture = {
  1483. .rates = FSI_RATES,
  1484. .formats = FSI_FMTS,
  1485. .channels_min = 2,
  1486. .channels_max = 2,
  1487. },
  1488. .ops = &fsi_dai_ops,
  1489. },
  1490. {
  1491. .name = "fsib-dai",
  1492. .playback = {
  1493. .rates = FSI_RATES,
  1494. .formats = FSI_FMTS,
  1495. .channels_min = 2,
  1496. .channels_max = 2,
  1497. },
  1498. .capture = {
  1499. .rates = FSI_RATES,
  1500. .formats = FSI_FMTS,
  1501. .channels_min = 2,
  1502. .channels_max = 2,
  1503. },
  1504. .ops = &fsi_dai_ops,
  1505. },
  1506. };
  1507. static struct snd_soc_platform_driver fsi_soc_platform = {
  1508. .ops = &fsi_pcm_ops,
  1509. .pcm_new = fsi_pcm_new,
  1510. };
  1511. static const struct snd_soc_component_driver fsi_soc_component = {
  1512. .name = "fsi",
  1513. };
  1514. /*
  1515. * platform function
  1516. */
  1517. static void fsi_of_parse(char *name,
  1518. struct device_node *np,
  1519. struct sh_fsi_port_info *info,
  1520. struct device *dev)
  1521. {
  1522. int i;
  1523. char prop[128];
  1524. unsigned long flags = 0;
  1525. struct {
  1526. char *name;
  1527. unsigned int val;
  1528. } of_parse_property[] = {
  1529. { "spdif-connection", SH_FSI_FMT_SPDIF },
  1530. { "stream-mode-support", SH_FSI_ENABLE_STREAM_MODE },
  1531. { "use-internal-clock", SH_FSI_CLK_CPG },
  1532. };
  1533. for (i = 0; i < ARRAY_SIZE(of_parse_property); i++) {
  1534. sprintf(prop, "%s,%s", name, of_parse_property[i].name);
  1535. if (of_get_property(np, prop, NULL))
  1536. flags |= of_parse_property[i].val;
  1537. }
  1538. info->flags = flags;
  1539. dev_dbg(dev, "%s flags : %lx\n", name, info->flags);
  1540. }
  1541. static void fsi_port_info_init(struct fsi_priv *fsi,
  1542. struct sh_fsi_port_info *info)
  1543. {
  1544. if (info->flags & SH_FSI_FMT_SPDIF)
  1545. fsi->spdif = 1;
  1546. if (info->flags & SH_FSI_CLK_CPG)
  1547. fsi->clk_cpg = 1;
  1548. if (info->flags & SH_FSI_ENABLE_STREAM_MODE)
  1549. fsi->enable_stream = 1;
  1550. }
  1551. static void fsi_handler_init(struct fsi_priv *fsi,
  1552. struct sh_fsi_port_info *info)
  1553. {
  1554. fsi->playback.handler = &fsi_pio_push_handler; /* default PIO */
  1555. fsi->playback.priv = fsi;
  1556. fsi->capture.handler = &fsi_pio_pop_handler; /* default PIO */
  1557. fsi->capture.priv = fsi;
  1558. if (info->tx_id) {
  1559. fsi->playback.dma_id = info->tx_id;
  1560. fsi->playback.handler = &fsi_dma_push_handler;
  1561. }
  1562. }
  1563. static const struct fsi_core fsi1_core = {
  1564. .ver = 1,
  1565. /* Interrupt */
  1566. .int_st = INT_ST,
  1567. .iemsk = IEMSK,
  1568. .imsk = IMSK,
  1569. };
  1570. static const struct fsi_core fsi2_core = {
  1571. .ver = 2,
  1572. /* Interrupt */
  1573. .int_st = CPU_INT_ST,
  1574. .iemsk = CPU_IEMSK,
  1575. .imsk = CPU_IMSK,
  1576. .a_mclk = A_MST_CTLR,
  1577. .b_mclk = B_MST_CTLR,
  1578. };
  1579. static const struct of_device_id fsi_of_match[] = {
  1580. { .compatible = "renesas,sh_fsi", .data = &fsi1_core},
  1581. { .compatible = "renesas,sh_fsi2", .data = &fsi2_core},
  1582. {},
  1583. };
  1584. MODULE_DEVICE_TABLE(of, fsi_of_match);
  1585. static const struct platform_device_id fsi_id_table[] = {
  1586. { "sh_fsi", (kernel_ulong_t)&fsi1_core },
  1587. {},
  1588. };
  1589. MODULE_DEVICE_TABLE(platform, fsi_id_table);
  1590. static int fsi_probe(struct platform_device *pdev)
  1591. {
  1592. struct fsi_master *master;
  1593. struct device_node *np = pdev->dev.of_node;
  1594. struct sh_fsi_platform_info info;
  1595. const struct fsi_core *core;
  1596. struct fsi_priv *fsi;
  1597. struct resource *res;
  1598. unsigned int irq;
  1599. int ret;
  1600. memset(&info, 0, sizeof(info));
  1601. core = NULL;
  1602. if (np) {
  1603. const struct of_device_id *of_id;
  1604. of_id = of_match_device(fsi_of_match, &pdev->dev);
  1605. if (of_id) {
  1606. core = of_id->data;
  1607. fsi_of_parse("fsia", np, &info.port_a, &pdev->dev);
  1608. fsi_of_parse("fsib", np, &info.port_b, &pdev->dev);
  1609. }
  1610. } else {
  1611. const struct platform_device_id *id_entry = pdev->id_entry;
  1612. if (id_entry)
  1613. core = (struct fsi_core *)id_entry->driver_data;
  1614. if (pdev->dev.platform_data)
  1615. memcpy(&info, pdev->dev.platform_data, sizeof(info));
  1616. }
  1617. if (!core) {
  1618. dev_err(&pdev->dev, "unknown fsi device\n");
  1619. return -ENODEV;
  1620. }
  1621. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1622. irq = platform_get_irq(pdev, 0);
  1623. if (!res || (int)irq <= 0) {
  1624. dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
  1625. return -ENODEV;
  1626. }
  1627. master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL);
  1628. if (!master) {
  1629. dev_err(&pdev->dev, "Could not allocate master\n");
  1630. return -ENOMEM;
  1631. }
  1632. master->base = devm_ioremap_nocache(&pdev->dev,
  1633. res->start, resource_size(res));
  1634. if (!master->base) {
  1635. dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
  1636. return -ENXIO;
  1637. }
  1638. /* master setting */
  1639. master->core = core;
  1640. spin_lock_init(&master->lock);
  1641. /* FSI A setting */
  1642. fsi = &master->fsia;
  1643. fsi->base = master->base;
  1644. fsi->phys = res->start;
  1645. fsi->master = master;
  1646. fsi_port_info_init(fsi, &info.port_a);
  1647. fsi_handler_init(fsi, &info.port_a);
  1648. ret = fsi_stream_probe(fsi, &pdev->dev);
  1649. if (ret < 0) {
  1650. dev_err(&pdev->dev, "FSIA stream probe failed\n");
  1651. return ret;
  1652. }
  1653. /* FSI B setting */
  1654. fsi = &master->fsib;
  1655. fsi->base = master->base + 0x40;
  1656. fsi->phys = res->start + 0x40;
  1657. fsi->master = master;
  1658. fsi_port_info_init(fsi, &info.port_b);
  1659. fsi_handler_init(fsi, &info.port_b);
  1660. ret = fsi_stream_probe(fsi, &pdev->dev);
  1661. if (ret < 0) {
  1662. dev_err(&pdev->dev, "FSIB stream probe failed\n");
  1663. goto exit_fsia;
  1664. }
  1665. pm_runtime_enable(&pdev->dev);
  1666. dev_set_drvdata(&pdev->dev, master);
  1667. ret = devm_request_irq(&pdev->dev, irq, &fsi_interrupt, 0,
  1668. dev_name(&pdev->dev), master);
  1669. if (ret) {
  1670. dev_err(&pdev->dev, "irq request err\n");
  1671. goto exit_fsib;
  1672. }
  1673. ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform);
  1674. if (ret < 0) {
  1675. dev_err(&pdev->dev, "cannot snd soc register\n");
  1676. goto exit_fsib;
  1677. }
  1678. ret = snd_soc_register_component(&pdev->dev, &fsi_soc_component,
  1679. fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai));
  1680. if (ret < 0) {
  1681. dev_err(&pdev->dev, "cannot snd component register\n");
  1682. goto exit_snd_soc;
  1683. }
  1684. return ret;
  1685. exit_snd_soc:
  1686. snd_soc_unregister_platform(&pdev->dev);
  1687. exit_fsib:
  1688. pm_runtime_disable(&pdev->dev);
  1689. fsi_stream_remove(&master->fsib);
  1690. exit_fsia:
  1691. fsi_stream_remove(&master->fsia);
  1692. return ret;
  1693. }
  1694. static int fsi_remove(struct platform_device *pdev)
  1695. {
  1696. struct fsi_master *master;
  1697. master = dev_get_drvdata(&pdev->dev);
  1698. pm_runtime_disable(&pdev->dev);
  1699. snd_soc_unregister_component(&pdev->dev);
  1700. snd_soc_unregister_platform(&pdev->dev);
  1701. fsi_stream_remove(&master->fsia);
  1702. fsi_stream_remove(&master->fsib);
  1703. return 0;
  1704. }
  1705. static void __fsi_suspend(struct fsi_priv *fsi,
  1706. struct fsi_stream *io,
  1707. struct device *dev)
  1708. {
  1709. if (!fsi_stream_is_working(fsi, io))
  1710. return;
  1711. fsi_stream_stop(fsi, io);
  1712. fsi_hw_shutdown(fsi, dev);
  1713. }
  1714. static void __fsi_resume(struct fsi_priv *fsi,
  1715. struct fsi_stream *io,
  1716. struct device *dev)
  1717. {
  1718. if (!fsi_stream_is_working(fsi, io))
  1719. return;
  1720. fsi_hw_startup(fsi, io, dev);
  1721. fsi_stream_start(fsi, io);
  1722. }
  1723. static int fsi_suspend(struct device *dev)
  1724. {
  1725. struct fsi_master *master = dev_get_drvdata(dev);
  1726. struct fsi_priv *fsia = &master->fsia;
  1727. struct fsi_priv *fsib = &master->fsib;
  1728. __fsi_suspend(fsia, &fsia->playback, dev);
  1729. __fsi_suspend(fsia, &fsia->capture, dev);
  1730. __fsi_suspend(fsib, &fsib->playback, dev);
  1731. __fsi_suspend(fsib, &fsib->capture, dev);
  1732. return 0;
  1733. }
  1734. static int fsi_resume(struct device *dev)
  1735. {
  1736. struct fsi_master *master = dev_get_drvdata(dev);
  1737. struct fsi_priv *fsia = &master->fsia;
  1738. struct fsi_priv *fsib = &master->fsib;
  1739. __fsi_resume(fsia, &fsia->playback, dev);
  1740. __fsi_resume(fsia, &fsia->capture, dev);
  1741. __fsi_resume(fsib, &fsib->playback, dev);
  1742. __fsi_resume(fsib, &fsib->capture, dev);
  1743. return 0;
  1744. }
  1745. static struct dev_pm_ops fsi_pm_ops = {
  1746. .suspend = fsi_suspend,
  1747. .resume = fsi_resume,
  1748. };
  1749. static struct platform_driver fsi_driver = {
  1750. .driver = {
  1751. .name = "fsi-pcm-audio",
  1752. .pm = &fsi_pm_ops,
  1753. .of_match_table = fsi_of_match,
  1754. },
  1755. .probe = fsi_probe,
  1756. .remove = fsi_remove,
  1757. .id_table = fsi_id_table,
  1758. };
  1759. module_platform_driver(fsi_driver);
  1760. MODULE_LICENSE("GPL v2");
  1761. MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
  1762. MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
  1763. MODULE_ALIAS("platform:fsi-pcm-audio");