alphascale,acc.txt 2.7 KB

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  1. Alphascale Clock Controller
  2. The ACC (Alphascale Clock Controller) is responsible of choising proper
  3. clock source, setting deviders and clock gates.
  4. Required properties for the ACC node:
  5. - compatible: must be "alphascale,asm9260-clock-controller"
  6. - reg: must contain the ACC register base and size
  7. - #clock-cells : shall be set to 1.
  8. Simple one-cell clock specifier format is used, where the only cell is used
  9. as an index of the clock inside the provider.
  10. It is encouraged to use dt-binding for clock index definitions. SoC specific
  11. dt-binding should be included to the device tree descriptor. For example
  12. Alphascale ASM9260:
  13. #include <dt-bindings/clock/alphascale,asm9260.h>
  14. This binding contains two types of clock providers:
  15. _AHB_ - AHB gate;
  16. _SYS_ - adjustable clock source. Not all peripheral have _SYS_ clock provider.
  17. All clock specific details can be found in the SoC documentation.
  18. CLKID_AHB_ROM 0
  19. CLKID_AHB_RAM 1
  20. CLKID_AHB_GPIO 2
  21. CLKID_AHB_MAC 3
  22. CLKID_AHB_EMI 4
  23. CLKID_AHB_USB0 5
  24. CLKID_AHB_USB1 6
  25. CLKID_AHB_DMA0 7
  26. CLKID_AHB_DMA1 8
  27. CLKID_AHB_UART0 9
  28. CLKID_AHB_UART1 10
  29. CLKID_AHB_UART2 11
  30. CLKID_AHB_UART3 12
  31. CLKID_AHB_UART4 13
  32. CLKID_AHB_UART5 14
  33. CLKID_AHB_UART6 15
  34. CLKID_AHB_UART7 16
  35. CLKID_AHB_UART8 17
  36. CLKID_AHB_UART9 18
  37. CLKID_AHB_I2S0 19
  38. CLKID_AHB_I2C0 20
  39. CLKID_AHB_I2C1 21
  40. CLKID_AHB_SSP0 22
  41. CLKID_AHB_IOCONFIG 23
  42. CLKID_AHB_WDT 24
  43. CLKID_AHB_CAN0 25
  44. CLKID_AHB_CAN1 26
  45. CLKID_AHB_MPWM 27
  46. CLKID_AHB_SPI0 28
  47. CLKID_AHB_SPI1 29
  48. CLKID_AHB_QEI 30
  49. CLKID_AHB_QUADSPI0 31
  50. CLKID_AHB_CAMIF 32
  51. CLKID_AHB_LCDIF 33
  52. CLKID_AHB_TIMER0 34
  53. CLKID_AHB_TIMER1 35
  54. CLKID_AHB_TIMER2 36
  55. CLKID_AHB_TIMER3 37
  56. CLKID_AHB_IRQ 38
  57. CLKID_AHB_RTC 39
  58. CLKID_AHB_NAND 40
  59. CLKID_AHB_ADC0 41
  60. CLKID_AHB_LED 42
  61. CLKID_AHB_DAC0 43
  62. CLKID_AHB_LCD 44
  63. CLKID_AHB_I2S1 45
  64. CLKID_AHB_MAC1 46
  65. CLKID_SYS_CPU 47
  66. CLKID_SYS_AHB 48
  67. CLKID_SYS_I2S0M 49
  68. CLKID_SYS_I2S0S 50
  69. CLKID_SYS_I2S1M 51
  70. CLKID_SYS_I2S1S 52
  71. CLKID_SYS_UART0 53
  72. CLKID_SYS_UART1 54
  73. CLKID_SYS_UART2 55
  74. CLKID_SYS_UART3 56
  75. CLKID_SYS_UART4 56
  76. CLKID_SYS_UART5 57
  77. CLKID_SYS_UART6 58
  78. CLKID_SYS_UART7 59
  79. CLKID_SYS_UART8 60
  80. CLKID_SYS_UART9 61
  81. CLKID_SYS_SPI0 62
  82. CLKID_SYS_SPI1 63
  83. CLKID_SYS_QUADSPI 64
  84. CLKID_SYS_SSP0 65
  85. CLKID_SYS_NAND 66
  86. CLKID_SYS_TRACE 67
  87. CLKID_SYS_CAMM 68
  88. CLKID_SYS_WDT 69
  89. CLKID_SYS_CLKOUT 70
  90. CLKID_SYS_MAC 71
  91. CLKID_SYS_LCD 72
  92. CLKID_SYS_ADCANA 73
  93. Example of clock consumer with _SYS_ and _AHB_ sinks.
  94. uart4: serial@80010000 {
  95. compatible = "alphascale,asm9260-uart";
  96. reg = <0x80010000 0x4000>;
  97. clocks = <&acc CLKID_SYS_UART4>, <&acc CLKID_AHB_UART4>;
  98. interrupts = <19>;
  99. status = "disabled";
  100. };
  101. Clock consumer with only one, _AHB_ sink.
  102. timer0: timer@80088000 {
  103. compatible = "alphascale,asm9260-timer";
  104. reg = <0x80088000 0x4000>;
  105. clocks = <&acc CLKID_AHB_TIMER0>;
  106. interrupts = <29>;
  107. };