emev2-clock.txt 2.6 KB

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  1. Device tree Clock bindings for Renesas EMMA Mobile EV2
  2. This binding uses the common clock binding.
  3. * SMU
  4. System Management Unit described in user's manual R19UH0037EJ1000_SMU.
  5. This is not a clock provider, but clocks under SMU depend on it.
  6. Required properties:
  7. - compatible: Should be "renesas,emev2-smu"
  8. - reg: Address and Size of SMU registers
  9. * SMU_CLKDIV
  10. Function block with an input mux and a divider, which corresponds to
  11. "Serial clock generator" in fig."Clock System Overview" of the manual,
  12. and "xxx frequency division setting register" (XXXCLKDIV) registers.
  13. This makes internal (neither input nor output) clock that is provided
  14. to input of xxxGCLK block.
  15. Required properties:
  16. - compatible: Should be "renesas,emev2-smu-clkdiv"
  17. - reg: Byte offset from SMU base and Bit position in the register
  18. - clocks: Parent clocks. Input clocks as described in clock-bindings.txt
  19. - #clock-cells: Should be <0>
  20. * SMU_GCLK
  21. Clock gating node shown as "Clock stop processing block" in the
  22. fig."Clock System Overview" of the manual.
  23. Registers are "xxx clock gate control register" (XXXGCLKCTRL).
  24. Required properties:
  25. - compatible: Should be "renesas,emev2-smu-gclk"
  26. - reg: Byte offset from SMU base and Bit position in the register
  27. - clocks: Input clock as described in clock-bindings.txt
  28. - #clock-cells: Should be <0>
  29. Example of provider:
  30. usia_u0_sclkdiv: usia_u0_sclkdiv {
  31. compatible = "renesas,emev2-smu-clkdiv";
  32. reg = <0x610 0>;
  33. clocks = <&pll3_fo>, <&pll4_fo>, <&pll1_fo>, <&osc1_fo>;
  34. #clock-cells = <0>;
  35. };
  36. usia_u0_sclk: usia_u0_sclk {
  37. compatible = "renesas,emev2-smu-gclk";
  38. reg = <0x4a0 1>;
  39. clocks = <&usia_u0_sclkdiv>;
  40. #clock-cells = <0>;
  41. };
  42. Example of consumer:
  43. serial@e1020000 {
  44. compatible = "renesas,em-uart";
  45. reg = <0xe1020000 0x38>;
  46. interrupts = <0 8 0>;
  47. clocks = <&usia_u0_sclk>;
  48. clock-names = "sclk";
  49. };
  50. Example of clock-tree description:
  51. This describes a clock path in the clock tree
  52. c32ki -> pll3_fo -> usia_u0_sclkdiv -> usia_u0_sclk
  53. smu@e0110000 {
  54. compatible = "renesas,emev2-smu";
  55. reg = <0xe0110000 0x10000>;
  56. #address-cells = <2>;
  57. #size-cells = <0>;
  58. c32ki: c32ki {
  59. compatible = "fixed-clock";
  60. clock-frequency = <32768>;
  61. #clock-cells = <0>;
  62. };
  63. pll3_fo: pll3_fo {
  64. compatible = "fixed-factor-clock";
  65. clocks = <&c32ki>;
  66. clock-div = <1>;
  67. clock-mult = <7000>;
  68. #clock-cells = <0>;
  69. };
  70. usia_u0_sclkdiv: usia_u0_sclkdiv {
  71. compatible = "renesas,emev2-smu-clkdiv";
  72. reg = <0x610 0>;
  73. clocks = <&pll3_fo>;
  74. #clock-cells = <0>;
  75. };
  76. usia_u0_sclk: usia_u0_sclk {
  77. compatible = "renesas,emev2-smu-gclk";
  78. reg = <0x4a0 1>;
  79. clocks = <&usia_u0_sclkdiv>;
  80. #clock-cells = <0>;
  81. };
  82. };