nvidia,tegra20-car.txt 1.5 KB

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  1. NVIDIA Tegra20 Clock And Reset Controller
  2. This binding uses the common clock binding:
  3. Documentation/devicetree/bindings/clock/clock-bindings.txt
  4. The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
  5. for muxing and gating Tegra's clocks, and setting their rates.
  6. Required properties :
  7. - compatible : Should be "nvidia,tegra20-car"
  8. - reg : Should contain CAR registers location and length
  9. - clocks : Should contain phandle and clock specifiers for two clocks:
  10. the 32 KHz "32k_in", and the board-specific oscillator "osc".
  11. - #clock-cells : Should be 1.
  12. In clock consumers, this cell represents the clock ID exposed by the
  13. CAR. The assignments may be found in header file
  14. <dt-bindings/clock/tegra20-car.h>.
  15. - #reset-cells : Should be 1.
  16. In clock consumers, this cell represents the bit number in the CAR's
  17. array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
  18. Example SoC include file:
  19. / {
  20. tegra_car: clock {
  21. compatible = "nvidia,tegra20-car";
  22. reg = <0x60006000 0x1000>;
  23. #clock-cells = <1>;
  24. #reset-cells = <1>;
  25. };
  26. usb@c5004000 {
  27. clocks = <&tegra_car TEGRA20_CLK_USB2>;
  28. };
  29. };
  30. Example board file:
  31. / {
  32. clocks {
  33. compatible = "simple-bus";
  34. #address-cells = <1>;
  35. #size-cells = <0>;
  36. osc: clock@0 {
  37. compatible = "fixed-clock";
  38. reg = <0>;
  39. #clock-cells = <0>;
  40. clock-frequency = <12000000>;
  41. };
  42. clk_32k: clock@1 {
  43. compatible = "fixed-clock";
  44. reg = <1>;
  45. #clock-cells = <0>;
  46. clock-frequency = <32768>;
  47. };
  48. };
  49. &tegra_car {
  50. clocks = <&clk_32k> <&osc>;
  51. };
  52. };