qca,ath79-pll.txt 877 B

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  1. Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller
  2. The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.
  3. Required Properties:
  4. - compatible: has to be "qca,<soctype>-cpu-intc" and one of the following
  5. fallbacks:
  6. - "qca,ar7100-pll"
  7. - "qca,ar7240-pll"
  8. - "qca,ar9130-pll"
  9. - "qca,ar9330-pll"
  10. - "qca,ar9340-pll"
  11. - "qca,qca9550-pll"
  12. - reg: Base address and size of the controllers memory area
  13. - clock-names: Name of the input clock, has to be "ref"
  14. - clocks: phandle of the external reference clock
  15. - #clock-cells: has to be one
  16. Optional properties:
  17. - clock-output-names: should be "cpu", "ddr", "ahb"
  18. Example:
  19. memory-controller@18050000 {
  20. compatible = "qca,ar9132-ppl", "qca,ar9130-pll";
  21. reg = <0x18050000 0x20>;
  22. clock-names = "ref";
  23. clocks = <&extosc>;
  24. #clock-cells = <1>;
  25. clock-output-names = "cpu", "ddr", "ahb";
  26. };