renesas,cpg-mssr.txt 2.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869
  1. * Renesas Clock Pulse Generator / Module Standby and Software Reset
  2. On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
  3. and MSSR (Module Standby and Software Reset) blocks are intimately connected,
  4. and share the same register block.
  5. They provide the following functionalities:
  6. - The CPG block generates various core clocks,
  7. - The MSSR block provides two functions:
  8. 1. Module Standby, providing a Clock Domain to control the clock supply
  9. to individual SoC devices,
  10. 2. Reset Control, to perform a software reset of individual SoC devices.
  11. Required Properties:
  12. - compatible: Must be one of:
  13. - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC
  14. - reg: Base address and length of the memory resource used by the CPG/MSSR
  15. block
  16. - clocks: References to external parent clocks, one entry for each entry in
  17. clock-names
  18. - clock-names: List of external parent clock names. Valid names are:
  19. - "extal" (r8a7795)
  20. - "extalr" (r8a7795)
  21. - #clock-cells: Must be 2
  22. - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
  23. and a core clock reference, as defined in
  24. <dt-bindings/clock/*-cpg-mssr.h>.
  25. - For module clocks, the two clock specifier cells must be "CPG_MOD" and
  26. a module number, as defined in the datasheet.
  27. - #power-domain-cells: Must be 0
  28. - SoC devices that are part of the CPG/MSSR Clock Domain and can be
  29. power-managed through Module Standby should refer to the CPG device
  30. node in their "power-domains" property, as documented by the generic PM
  31. Domain bindings in
  32. Documentation/devicetree/bindings/power/power_domain.txt.
  33. Examples
  34. --------
  35. - CPG device node:
  36. cpg: clock-controller@e6150000 {
  37. compatible = "renesas,r8a7795-cpg-mssr";
  38. reg = <0 0xe6150000 0 0x1000>;
  39. clocks = <&extal_clk>, <&extalr_clk>;
  40. clock-names = "extal", "extalr";
  41. #clock-cells = <2>;
  42. #power-domain-cells = <0>;
  43. };
  44. - CPG/MSSR Clock Domain member device node:
  45. scif2: serial@e6e88000 {
  46. compatible = "renesas,scif-r8a7795", "renesas,scif";
  47. reg = <0 0xe6e88000 0 64>;
  48. interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
  49. clocks = <&cpg CPG_MOD 310>;
  50. clock-names = "sci_ick";
  51. dmas = <&dmac1 0x13>, <&dmac1 0x12>;
  52. dma-names = "tx", "rx";
  53. power-domains = <&cpg>;
  54. status = "disabled";
  55. };