renesas,cpg-mstp-clocks.txt 2.5 KB

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  1. * Renesas CPG Module Stop (MSTP) Clocks
  2. The CPG can gate SoC device clocks. The gates are organized in groups of up to
  3. 32 gates.
  4. This device tree binding describes a single 32 gate clocks group per node.
  5. Clocks are referenced by user nodes by the MSTP node phandle and the clock
  6. index in the group, from 0 to 31.
  7. Required Properties:
  8. - compatible: Must be one of the following
  9. - "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks
  10. - "renesas,r8a73a4-mstp-clocks" for R8A73A4 (R-Mobile APE6) MSTP gate clocks
  11. - "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks
  12. - "renesas,r8a7778-mstp-clocks" for R8A7778 (R-Car M1) MSTP gate clocks
  13. - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
  14. - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
  15. - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2-W) MSTP gate clocks
  16. - "renesas,r8a7793-mstp-clocks" for R8A7793 (R-Car M2-N) MSTP gate clocks
  17. - "renesas,r8a7794-mstp-clocks" for R8A7794 (R-Car E2) MSTP gate clocks
  18. - "renesas,sh73a0-mstp-clocks" for SH73A0 (SH-MobileAG5) MSTP gate clocks
  19. and "renesas,cpg-mstp-clocks" as a fallback.
  20. - reg: Base address and length of the I/O mapped registers used by the MSTP
  21. clocks. The first register is the clock control register and is mandatory.
  22. The second register is the clock status register and is optional when not
  23. implemented in hardware.
  24. - clocks: Reference to the parent clocks, one per output clock. The parents
  25. must appear in the same order as the output clocks.
  26. - #clock-cells: Must be 1
  27. - clock-output-names: The name of the clocks as free-form strings
  28. - clock-indices: Indices of the gate clocks into the group (0 to 31)
  29. The clocks, clock-output-names and clock-indices properties contain one entry
  30. per gate clock. The MSTP groups are sparsely populated. Unimplemented gate
  31. clocks must not be declared.
  32. Example
  33. -------
  34. #include <dt-bindings/clock/r8a7790-clock.h>
  35. mstp3_clks: mstp3_clks@e615013c {
  36. compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
  37. reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
  38. clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>,
  39. <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>,
  40. <&mmc0_clk>;
  41. #clock-cells = <1>;
  42. clock-output-names =
  43. "tpu0", "mmcif1", "sdhi3", "sdhi2",
  44. "sdhi1", "sdhi0", "mmcif0";
  45. clock-indices = <
  46. R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
  47. R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0
  48. R8A7790_CLK_MMCIF0
  49. >;
  50. };