silabs,si5351.txt 3.5 KB

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  1. Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator.
  2. Reference
  3. [1] Si5351A/B/C Data Sheet
  4. http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf
  5. The Si5351a/b/c are programmable i2c clock generators with up to 8 output
  6. clocks. Si5351a also has a reduced pin-count package (MSOP10) where only
  7. 3 output clocks are accessible. The internal structure of the clock
  8. generators can be found in [1].
  9. ==I2C device node==
  10. Required properties:
  11. - compatible: shall be one of "silabs,si5351{a,a-msop,b,c}".
  12. - reg: i2c device address, shall be 0x60 or 0x61.
  13. - #clock-cells: from common clock binding; shall be set to 1.
  14. - clocks: from common clock binding; list of parent clock
  15. handles, shall be xtal reference clock or xtal and clkin for
  16. si5351c only. Corresponding clock input names are "xtal" and
  17. "clkin" respectively.
  18. - #address-cells: shall be set to 1.
  19. - #size-cells: shall be set to 0.
  20. Optional properties:
  21. - silabs,pll-source: pair of (number, source) for each pll. Allows
  22. to overwrite clock source of pll A (number=0) or B (number=1).
  23. ==Child nodes==
  24. Each of the clock outputs can be overwritten individually by
  25. using a child node to the I2C device node. If a child node for a clock
  26. output is not set, the eeprom configuration is not overwritten.
  27. Required child node properties:
  28. - reg: number of clock output.
  29. Optional child node properties:
  30. - silabs,clock-source: source clock of the output divider stage N, shall be
  31. 0 = multisynth N
  32. 1 = multisynth 0 for output clocks 0-3, else multisynth4
  33. 2 = xtal
  34. 3 = clkin (si5351c only)
  35. - silabs,drive-strength: output drive strength in mA, shall be one of {2,4,6,8}.
  36. - silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth
  37. divider.
  38. - silabs,pll-master: boolean, multisynth can change pll frequency.
  39. - silabs,disable-state : clock output disable state, shall be
  40. 0 = clock output is driven LOW when disabled
  41. 1 = clock output is driven HIGH when disabled
  42. 2 = clock output is FLOATING (HIGH-Z) when disabled
  43. 3 = clock output is NEVER disabled
  44. ==Example==
  45. /* 25MHz reference crystal */
  46. ref25: ref25M {
  47. compatible = "fixed-clock";
  48. #clock-cells = <0>;
  49. clock-frequency = <25000000>;
  50. };
  51. i2c-master-node {
  52. /* Si5351a msop10 i2c clock generator */
  53. si5351a: clock-generator@60 {
  54. compatible = "silabs,si5351a-msop";
  55. reg = <0x60>;
  56. #address-cells = <1>;
  57. #size-cells = <0>;
  58. #clock-cells = <1>;
  59. /* connect xtal input to 25MHz reference */
  60. clocks = <&ref25>;
  61. clock-names = "xtal";
  62. /* connect xtal input as source of pll0 and pll1 */
  63. silabs,pll-source = <0 0>, <1 0>;
  64. /*
  65. * overwrite clkout0 configuration with:
  66. * - 8mA output drive strength
  67. * - pll0 as clock source of multisynth0
  68. * - multisynth0 as clock source of output divider
  69. * - multisynth0 can change pll0
  70. * - set initial clock frequency of 74.25MHz
  71. */
  72. clkout0 {
  73. reg = <0>;
  74. silabs,drive-strength = <8>;
  75. silabs,multisynth-source = <0>;
  76. silabs,clock-source = <0>;
  77. silabs,pll-master;
  78. clock-frequency = <74250000>;
  79. };
  80. /*
  81. * overwrite clkout1 configuration with:
  82. * - 4mA output drive strength
  83. * - pll1 as clock source of multisynth1
  84. * - multisynth1 as clock source of output divider
  85. * - multisynth1 can change pll1
  86. */
  87. clkout1 {
  88. reg = <1>;
  89. silabs,drive-strength = <4>;
  90. silabs,multisynth-source = <1>;
  91. silabs,clock-source = <0>;
  92. pll-master;
  93. };
  94. /*
  95. * overwrite clkout2 configuration with:
  96. * - xtal as clock source of output divider
  97. */
  98. clkout2 {
  99. reg = <2>;
  100. silabs,clock-source = <2>;
  101. };
  102. };
  103. };