st,clkgen-prediv.txt 861 B

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  1. Binding for a ST pre-divider clock driver.
  2. This binding uses the common clock binding[1].
  3. Base address is located to the parent node. See clock binding[2]
  4. [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
  5. [2] Documentation/devicetree/bindings/clock/st/st,clkgen.txt
  6. Required properties:
  7. - compatible : shall be:
  8. "st,clkgena-prediv-c65", "st,clkgena-prediv"
  9. "st,clkgena-prediv-c32", "st,clkgena-prediv"
  10. - #clock-cells : From common clock binding; shall be set to 0.
  11. - clocks : From common clock binding
  12. - clock-output-names : From common clock binding.
  13. Example:
  14. clockgen-a@fd345000 {
  15. reg = <0xfd345000 0xb50>;
  16. clk_m_a2_osc_prediv: clk-m-a2-osc-prediv {
  17. #clock-cells = <0>;
  18. compatible = "st,clkgena-prediv-c32",
  19. "st,clkgena-prediv";
  20. clocks = <&clk_sysin>;
  21. clock-output-names = "clk-m-a2-osc-prediv";
  22. };
  23. };