zx296702-clk.txt 1.0 KB

1234567891011121314151617181920212223242526272829303132333435
  1. Device Tree Clock bindings for ZTE zx296702
  2. This binding uses the common clock binding[1].
  3. [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
  4. Required properties:
  5. - compatible : shall be one of the following:
  6. "zte,zx296702-topcrm-clk":
  7. zx296702 top clock selection, divider and gating
  8. "zte,zx296702-lsp0crpm-clk" and
  9. "zte,zx296702-lsp1crpm-clk":
  10. zx296702 device level clock selection and gating
  11. - reg: Address and length of the register set
  12. The clock consumer should specify the desired clock by having the clock
  13. ID in its "clocks" phandle cell. See include/dt-bindings/clock/zx296702-clock.h
  14. for the full list of zx296702 clock IDs.
  15. topclk: topcrm@0x09800000 {
  16. compatible = "zte,zx296702-topcrm-clk";
  17. reg = <0x09800000 0x1000>;
  18. #clock-cells = <1>;
  19. };
  20. uart0: serial@0x09405000 {
  21. compatible = "zte,zx296702-uart";
  22. reg = <0x09405000 0x1000>;
  23. interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
  24. clocks = <&lsp1clk ZX296702_UART0_PCLK>;
  25. status = "disabled";
  26. };