adi,axi-dmac.txt 2.0 KB

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  1. Analog Device AXI-DMAC DMA controller
  2. Required properties:
  3. - compatible: Must be "adi,axi-dmac-1.00.a".
  4. - reg: Specification for the controllers memory mapped register map.
  5. - interrupts: Specification for the controllers interrupt.
  6. - clocks: Phandle and specifier to the controllers AXI interface clock
  7. - #dma-cells: Must be 1.
  8. Required sub-nodes:
  9. - adi,channels: This sub-node must contain a sub-node for each DMA channel. For
  10. the channel sub-nodes the following bindings apply. They must match the
  11. configuration options of the peripheral as it was instantiated.
  12. Required properties for adi,channels sub-node:
  13. - #size-cells: Must be 0
  14. - #address-cells: Must be 1
  15. Required channel sub-node properties:
  16. - reg: Which channel this node refers to.
  17. - adi,length-width: Width of the DMA transfer length register.
  18. - adi,source-bus-width,
  19. adi,destination-bus-width: Width of the source or destination bus in bits.
  20. - adi,source-bus-type,
  21. adi,destination-bus-type: Type of the source or destination bus. Must be one
  22. of the following:
  23. 0 (AXI_DMAC_TYPE_AXI_MM): Memory mapped AXI interface
  24. 1 (AXI_DMAC_TYPE_AXI_STREAM): Streaming AXI interface
  25. 2 (AXI_DMAC_TYPE_AXI_FIFO): FIFO interface
  26. Optional channel properties:
  27. - adi,cyclic: Must be set if the channel supports hardware cyclic DMA
  28. transfers.
  29. - adi,2d: Must be set if the channel supports hardware 2D DMA transfers.
  30. DMA clients connected to the AXI-DMAC DMA controller must use the format
  31. described in the dma.txt file using a one-cell specifier. The value of the
  32. specifier refers to the DMA channel index.
  33. Example:
  34. dma: dma@7c420000 {
  35. compatible = "adi,axi-dmac-1.00.a";
  36. reg = <0x7c420000 0x10000>;
  37. interrupts = <0 57 0>;
  38. clocks = <&clkc 16>;
  39. #dma-cells = <1>;
  40. adi,channels {
  41. #size-cells = <0>;
  42. #address-cells = <1>;
  43. dma-channel@0 {
  44. reg = <0>;
  45. adi,source-bus-width = <32>;
  46. adi,source-bus-type = <ADI_AXI_DMAC_TYPE_MM_AXI>;
  47. adi,destination-bus-width = <64>;
  48. adi,destination-bus-type = <ADI_AXI_DMAC_TYPE_FIFO>;
  49. };
  50. };
  51. };