arm-pl08x.txt 1.8 KB

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  1. * ARM PrimeCells PL080 and PL081 and derivatives DMA controller
  2. Required properties:
  3. - compatible: "arm,pl080", "arm,primecell";
  4. "arm,pl081", "arm,primecell";
  5. - reg: Address range of the PL08x registers
  6. - interrupt: The PL08x interrupt number
  7. - clocks: The clock running the IP core clock
  8. - clock-names: Must contain "apb_pclk"
  9. - lli-bus-interface-ahb1: if AHB master 1 is eligible for fetching LLIs
  10. - lli-bus-interface-ahb2: if AHB master 2 is eligible for fetching LLIs
  11. - mem-bus-interface-ahb1: if AHB master 1 is eligible for fetching memory contents
  12. - mem-bus-interface-ahb2: if AHB master 2 is eligible for fetching memory contents
  13. - #dma-cells: must be <2>. First cell should contain the DMA request,
  14. second cell should contain either 1 or 2 depending on
  15. which AHB master that is used.
  16. Optional properties:
  17. - dma-channels: contains the total number of DMA channels supported by the DMAC
  18. - dma-requests: contains the total number of DMA requests supported by the DMAC
  19. - memcpy-burst-size: the size of the bursts for memcpy: 1, 4, 8, 16, 32
  20. 64, 128 or 256 bytes are legal values
  21. - memcpy-bus-width: the bus width used for memcpy: 8, 16 or 32 are legal
  22. values
  23. Clients
  24. Required properties:
  25. - dmas: List of DMA controller phandle, request channel and AHB master id
  26. - dma-names: Names of the aforementioned requested channels
  27. Example:
  28. dmac0: dma-controller@10130000 {
  29. compatible = "arm,pl080", "arm,primecell";
  30. reg = <0x10130000 0x1000>;
  31. interrupt-parent = <&vica>;
  32. interrupts = <15>;
  33. clocks = <&hclkdma0>;
  34. clock-names = "apb_pclk";
  35. lli-bus-interface-ahb1;
  36. lli-bus-interface-ahb2;
  37. mem-bus-interface-ahb2;
  38. memcpy-burst-size = <256>;
  39. memcpy-bus-width = <32>;
  40. #dma-cells = <2>;
  41. };
  42. device@40008000 {
  43. ...
  44. dmas = <&dmac0 0 2
  45. &dmac0 1 2>;
  46. dma-names = "tx", "rx";
  47. ...
  48. };