lpc1850-dmamux.txt 1.4 KB

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  1. NXP LPC18xx/43xx DMA MUX (DMA request router)
  2. Required properties:
  3. - compatible: "nxp,lpc1850-dmamux"
  4. - reg: Memory map for accessing module
  5. - #dma-cells: Should be set to <3>.
  6. * 1st cell contain the master dma request signal
  7. * 2nd cell contain the mux value (0-3) for the peripheral
  8. * 3rd cell contain either 1 or 2 depending on the AHB
  9. master used.
  10. - dma-requests: Number of DMA requests for the mux
  11. - dma-masters: phandle pointing to the DMA controller
  12. The DMA controller node need to have the following poroperties:
  13. - dma-requests: Number of DMA requests the controller can handle
  14. Example:
  15. dmac: dma@40002000 {
  16. compatible = "nxp,lpc1850-gpdma", "arm,pl080", "arm,primecell";
  17. arm,primecell-periphid = <0x00041080>;
  18. reg = <0x40002000 0x1000>;
  19. interrupts = <2>;
  20. clocks = <&ccu1 CLK_CPU_DMA>;
  21. clock-names = "apb_pclk";
  22. #dma-cells = <2>;
  23. dma-channels = <8>;
  24. dma-requests = <16>;
  25. lli-bus-interface-ahb1;
  26. lli-bus-interface-ahb2;
  27. mem-bus-interface-ahb1;
  28. mem-bus-interface-ahb2;
  29. memcpy-burst-size = <256>;
  30. memcpy-bus-width = <32>;
  31. };
  32. dmamux: dma-mux {
  33. compatible = "nxp,lpc1850-dmamux";
  34. #dma-cells = <3>;
  35. dma-requests = <64>;
  36. dma-masters = <&dmac>;
  37. };
  38. uart0: serial@40081000 {
  39. compatible = "nxp,lpc1850-uart", "ns16550a";
  40. reg = <0x40081000 0x1000>;
  41. reg-shift = <2>;
  42. interrupts = <24>;
  43. clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>;
  44. clock-names = "uartclk", "reg";
  45. dmas = <&dmamux 1 1 2
  46. &dmamux 2 1 2>;
  47. dma-names = "tx", "rx";
  48. };