open-pic.txt 3.1 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798
  1. * Open PIC Binding
  2. This binding specifies what properties must be available in the device tree
  3. representation of an Open PIC compliant interrupt controller. This binding is
  4. based on the binding defined for Open PIC in [1] and is a superset of that
  5. binding.
  6. Required properties:
  7. NOTE: Many of these descriptions were paraphrased here from [1] to aid
  8. readability.
  9. - compatible: Specifies the compatibility list for the PIC. The type
  10. shall be <string> and the value shall include "open-pic".
  11. - reg: Specifies the base physical address(s) and size(s) of this
  12. PIC's addressable register space. The type shall be <prop-encoded-array>.
  13. - interrupt-controller: The presence of this property identifies the node
  14. as an Open PIC. No property value shall be defined.
  15. - #interrupt-cells: Specifies the number of cells needed to encode an
  16. interrupt source. The type shall be a <u32> and the value shall be 2.
  17. - #address-cells: Specifies the number of cells needed to encode an
  18. address. The type shall be <u32> and the value shall be 0. As such,
  19. 'interrupt-map' nodes do not have to specify a parent unit address.
  20. Optional properties:
  21. - pic-no-reset: The presence of this property indicates that the PIC
  22. shall not be reset during runtime initialization. No property value shall
  23. be defined. The presence of this property also mandates that any
  24. initialization related to interrupt sources shall be limited to sources
  25. explicitly referenced in the device tree.
  26. * Interrupt Specifier Definition
  27. Interrupt specifiers consists of 2 cells encoded as
  28. follows:
  29. - <1st-cell>: The interrupt-number that identifies the interrupt source.
  30. - <2nd-cell>: The level-sense information, encoded as follows:
  31. 0 = low-to-high edge triggered
  32. 1 = active low level-sensitive
  33. 2 = active high level-sensitive
  34. 3 = high-to-low edge triggered
  35. * Examples
  36. Example 1:
  37. /*
  38. * An Open PIC interrupt controller
  39. */
  40. mpic: pic@40000 {
  41. // This is an interrupt controller node.
  42. interrupt-controller;
  43. // No address cells so that 'interrupt-map' nodes which reference
  44. // this Open PIC node do not need a parent address specifier.
  45. #address-cells = <0>;
  46. // Two cells to encode interrupt sources.
  47. #interrupt-cells = <2>;
  48. // Offset address of 0x40000 and size of 0x40000.
  49. reg = <0x40000 0x40000>;
  50. // Compatible with Open PIC.
  51. compatible = "open-pic";
  52. // The PIC shall not be reset.
  53. pic-no-reset;
  54. };
  55. Example 2:
  56. /*
  57. * An interrupt generating device that is wired to an Open PIC.
  58. */
  59. serial0: serial@4500 {
  60. // Interrupt source '42' that is active high level-sensitive.
  61. // Note that there are only two cells as specified in the interrupt
  62. // parent's '#interrupt-cells' property.
  63. interrupts = <42 2>;
  64. // The interrupt controller that this device is wired to.
  65. interrupt-parent = <&mpic>;
  66. };
  67. * References
  68. [1] Power.org (TM) Standard for Embedded Power Architecture (TM) Platform
  69. Requirements (ePAPR), Version 1.0, July 2008.
  70. (http://www.power.org/resources/downloads/Power_ePAPR_APPROVED_v1.0.pdf)