st,spear3xx-shirq.txt 1.9 KB

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  1. * SPEAr Shared IRQ layer (shirq)
  2. SPEAr3xx architecture includes shared/multiplexed irqs for certain set
  3. of devices. The multiplexor provides a single interrupt to parent
  4. interrupt controller (VIC) on behalf of a group of devices.
  5. There can be multiple groups available on SPEAr3xx variants but not
  6. exceeding 4. The number of devices in a group can differ, further they
  7. may share same set of status/mask registers spanning across different
  8. bit masks. Also in some cases the group may not have enable or other
  9. registers. This makes software little complex.
  10. A single node in the device tree is used to describe the shared
  11. interrupt multiplexor (one node for all groups). A group in the
  12. interrupt controller shares config/control registers with other groups.
  13. For example, a 32-bit interrupt enable/disable config register can
  14. accommodate up to 4 interrupt groups.
  15. Required properties:
  16. - compatible: should be, either of
  17. - "st,spear300-shirq"
  18. - "st,spear310-shirq"
  19. - "st,spear320-shirq"
  20. - interrupt-controller: Identifies the node as an interrupt controller.
  21. - #interrupt-cells: should be <1> which basically contains the offset
  22. (starting from 0) of interrupts for all the groups.
  23. - reg: Base address and size of shirq registers.
  24. - interrupts: The list of interrupts generated by the groups which are
  25. then connected to a parent interrupt controller. Each group is
  26. associated with one of the interrupts, hence number of interrupts (to
  27. parent) is equal to number of groups. The format of the interrupt
  28. specifier depends in the interrupt parent controller.
  29. Optional properties:
  30. - interrupt-parent: pHandle of the parent interrupt controller, if not
  31. inherited from the parent node.
  32. Example:
  33. The following is an example from the SPEAr320 SoC dtsi file.
  34. shirq: interrupt-controller@0xb3000000 {
  35. compatible = "st,spear320-shirq";
  36. reg = <0xb3000000 0x1000>;
  37. interrupts = <28 29 30 1>;
  38. #interrupt-cells = <1>;
  39. interrupt-controller;
  40. };