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- * SPEAr Shared IRQ layer (shirq)
- SPEAr3xx architecture includes shared/multiplexed irqs for certain set
- of devices. The multiplexor provides a single interrupt to parent
- interrupt controller (VIC) on behalf of a group of devices.
- There can be multiple groups available on SPEAr3xx variants but not
- exceeding 4. The number of devices in a group can differ, further they
- may share same set of status/mask registers spanning across different
- bit masks. Also in some cases the group may not have enable or other
- registers. This makes software little complex.
- A single node in the device tree is used to describe the shared
- interrupt multiplexor (one node for all groups). A group in the
- interrupt controller shares config/control registers with other groups.
- For example, a 32-bit interrupt enable/disable config register can
- accommodate up to 4 interrupt groups.
- Required properties:
- - compatible: should be, either of
- - "st,spear300-shirq"
- - "st,spear310-shirq"
- - "st,spear320-shirq"
- - interrupt-controller: Identifies the node as an interrupt controller.
- - #interrupt-cells: should be <1> which basically contains the offset
- (starting from 0) of interrupts for all the groups.
- - reg: Base address and size of shirq registers.
- - interrupts: The list of interrupts generated by the groups which are
- then connected to a parent interrupt controller. Each group is
- associated with one of the interrupts, hence number of interrupts (to
- parent) is equal to number of groups. The format of the interrupt
- specifier depends in the interrupt parent controller.
- Optional properties:
- - interrupt-parent: pHandle of the parent interrupt controller, if not
- inherited from the parent node.
- Example:
- The following is an example from the SPEAr320 SoC dtsi file.
- shirq: interrupt-controller@0xb3000000 {
- compatible = "st,spear320-shirq";
- reg = <0xb3000000 0x1000>;
- interrupts = <28 29 30 1>;
- #interrupt-cells = <1>;
- interrupt-controller;
- };
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