ti,c64x+megamod-pic.txt 4.0 KB

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  1. C6X Interrupt Chips
  2. -------------------
  3. * C64X+ Core Interrupt Controller
  4. The core interrupt controller provides 16 prioritized interrupts to the
  5. C64X+ core. Priority 0 and 1 are used for reset and NMI respectively.
  6. Priority 2 and 3 are reserved. Priority 4-15 are used for interrupt
  7. sources coming from outside the core.
  8. Required properties:
  9. --------------------
  10. - compatible: Should be "ti,c64x+core-pic";
  11. - #interrupt-cells: <1>
  12. Interrupt Specifier Definition
  13. ------------------------------
  14. Single cell specifying the core interrupt priority level (4-15) where
  15. 4 is highest priority and 15 is lowest priority.
  16. Example
  17. -------
  18. core_pic: interrupt-controller@0 {
  19. interrupt-controller;
  20. #interrupt-cells = <1>;
  21. compatible = "ti,c64x+core-pic";
  22. };
  23. * C64x+ Megamodule Interrupt Controller
  24. The megamodule PIC consists of four interrupt mupliplexers each of which
  25. combine up to 32 interrupt inputs into a single interrupt output which
  26. may be cascaded into the core interrupt controller. The megamodule PIC
  27. has a total of 12 outputs cascading into the core interrupt controller.
  28. One for each core interrupt priority level. In addition to the combined
  29. interrupt sources, individual megamodule interrupts may be cascaded to
  30. the core interrupt controller. When an individual interrupt is cascaded,
  31. it is no longer handled through a megamodule interrupt combiner and is
  32. considered to have the core interrupt controller as the parent.
  33. Required properties:
  34. --------------------
  35. - compatible: "ti,c64x+megamod-pic"
  36. - interrupt-controller
  37. - #interrupt-cells: <1>
  38. - reg: base address and size of register area
  39. - interrupt-parent: must be core interrupt controller
  40. - interrupts: This should have four cells; one for each interrupt combiner.
  41. The cells contain the core priority interrupt to which the
  42. corresponding combiner output is wired.
  43. Optional properties:
  44. --------------------
  45. - ti,c64x+megamod-pic-mux: Array of 12 cells correspnding to the 12 core
  46. priority interrupts. The first cell corresponds to
  47. core priority 4 and the last cell corresponds to
  48. core priority 15. The value of each cell is the
  49. megamodule interrupt source which is MUXed to
  50. the core interrupt corresponding to the cell
  51. position. Allowed values are 4 - 127. Mapping for
  52. interrupts 0 - 3 (combined interrupt sources) are
  53. ignored.
  54. Interrupt Specifier Definition
  55. ------------------------------
  56. Single cell specifying the megamodule interrupt source (4-127). Note that
  57. interrupts mapped directly to the core with "ti,c64x+megamod-pic-mux" will
  58. use the core interrupt controller as their parent and the specifier will
  59. be the core priority level, not the megamodule interrupt number.
  60. Examples
  61. --------
  62. megamod_pic: interrupt-controller@1800000 {
  63. compatible = "ti,c64x+megamod-pic";
  64. interrupt-controller;
  65. #interrupt-cells = <1>;
  66. reg = <0x1800000 0x1000>;
  67. interrupt-parent = <&core_pic>;
  68. interrupts = < 12 13 14 15 >;
  69. };
  70. This is a minimal example where all individual interrupts go through a
  71. combiner. Combiner-0 is mapped to core interrupt 12, combiner-1 is mapped
  72. to interrupt 13, etc.
  73. megamod_pic: interrupt-controller@1800000 {
  74. compatible = "ti,c64x+megamod-pic";
  75. interrupt-controller;
  76. #interrupt-cells = <1>;
  77. reg = <0x1800000 0x1000>;
  78. interrupt-parent = <&core_pic>;
  79. interrupts = < 12 13 14 15 >;
  80. ti,c64x+megamod-pic-mux = < 0 0 0 0
  81. 32 0 0 0
  82. 0 0 0 0 >;
  83. };
  84. This the same as the first example except that megamodule interrupt 32 is
  85. mapped directly to core priority interrupt 8. The node using this interrupt
  86. must set the core controller as its interrupt parent and use 8 in the
  87. interrupt specifier value.