tegra-emc.txt 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374
  1. NVIDIA Tegra124 SoC EMC (external memory controller)
  2. ====================================================
  3. Required properties :
  4. - compatible : Should be "nvidia,tegra124-emc".
  5. - reg : physical base address and length of the controller's registers.
  6. - nvidia,memory-controller : phandle of the MC driver.
  7. The node should contain a "emc-timings" subnode for each supported RAM type
  8. (see field RAM_CODE in register PMC_STRAPPING_OPT_A), with its unit address
  9. being its RAM_CODE.
  10. Required properties for "emc-timings" nodes :
  11. - nvidia,ram-code : Should contain the value of RAM_CODE this timing set is
  12. used for.
  13. Each "emc-timings" node should contain a "timing" subnode for every supported
  14. EMC clock rate. The "timing" subnodes should have the clock rate in Hz as
  15. their unit address.
  16. Required properties for "timing" nodes :
  17. - clock-frequency : Should contain the memory clock rate in Hz.
  18. - The following properties contain EMC timing characterization values
  19. (specified in the board documentation) :
  20. - nvidia,emc-auto-cal-config : EMC_AUTO_CAL_CONFIG
  21. - nvidia,emc-auto-cal-config2 : EMC_AUTO_CAL_CONFIG2
  22. - nvidia,emc-auto-cal-config3 : EMC_AUTO_CAL_CONFIG3
  23. - nvidia,emc-auto-cal-interval : EMC_AUTO_CAL_INTERVAL
  24. - nvidia,emc-bgbias-ctl0 : EMC_BGBIAS_CTL0
  25. - nvidia,emc-cfg : EMC_CFG
  26. - nvidia,emc-cfg-2 : EMC_CFG_2
  27. - nvidia,emc-ctt-term-ctrl : EMC_CTT_TERM_CTRL
  28. - nvidia,emc-mode-1 : Mode Register 1
  29. - nvidia,emc-mode-2 : Mode Register 2
  30. - nvidia,emc-mode-4 : Mode Register 4
  31. - nvidia,emc-mode-reset : Mode Register 0
  32. - nvidia,emc-mrs-wait-cnt : EMC_MRS_WAIT_CNT
  33. - nvidia,emc-sel-dpd-ctrl : EMC_SEL_DPD_CTRL
  34. - nvidia,emc-xm2dqspadctrl2 : EMC_XM2DQSPADCTRL2
  35. - nvidia,emc-zcal-cnt-long : EMC_ZCAL_WAIT_CNT after clock change
  36. - nvidia,emc-zcal-interval : EMC_ZCAL_INTERVAL
  37. - nvidia,emc-configuration : EMC timing characterization data. These are the
  38. registers (see section "15.6.2 EMC Registers" in the TRM) whose values need to
  39. be specified, according to the board documentation:
  40. EMC_RC
  41. EMC_RFC
  42. EMC_RFC_SLR
  43. EMC_RAS
  44. EMC_RP
  45. EMC_R2W
  46. EMC_W2R
  47. EMC_R2P
  48. EMC_W2P
  49. EMC_RD_RCD
  50. EMC_WR_RCD
  51. EMC_RRD
  52. EMC_REXT
  53. EMC_WEXT
  54. EMC_WDV
  55. EMC_WDV_MASK
  56. EMC_QUSE
  57. EMC_QUSE_WIDTH
  58. EMC_IBDLY
  59. EMC_EINPUT
  60. EMC_EINPUT_DURATION
  61. EMC_PUTERM_EXTRA
  62. EMC_PUTERM_WIDTH
  63. EMC_PUTERM_ADJ
  64. EMC_CDB_CNTL_1
  65. EMC_CDB_CNTL_2
  66. EMC_CDB_CNTL_3
  67. EMC_QRST
  68. EMC_QSAFE
  69. EMC_RDV
  70. EMC_RDV_MASK
  71. EMC_REFRESH
  72. EMC_BURST_REFRESH_NUM
  73. EMC_PRE_REFRESH_REQ_CNT
  74. EMC_PDEX2WR
  75. EMC_PDEX2RD
  76. EMC_PCHG2PDEN
  77. EMC_ACT2PDEN
  78. EMC_AR2PDEN
  79. EMC_RW2PDEN
  80. EMC_TXSR
  81. EMC_TXSRDLL
  82. EMC_TCKE
  83. EMC_TCKESR
  84. EMC_TPD
  85. EMC_TFAW
  86. EMC_TRPAB
  87. EMC_TCLKSTABLE
  88. EMC_TCLKSTOP
  89. EMC_TREFBW
  90. EMC_FBIO_CFG6
  91. EMC_ODT_WRITE
  92. EMC_ODT_READ
  93. EMC_FBIO_CFG5
  94. EMC_CFG_DIG_DLL
  95. EMC_CFG_DIG_DLL_PERIOD
  96. EMC_DLL_XFORM_DQS0
  97. EMC_DLL_XFORM_DQS1
  98. EMC_DLL_XFORM_DQS2
  99. EMC_DLL_XFORM_DQS3
  100. EMC_DLL_XFORM_DQS4
  101. EMC_DLL_XFORM_DQS5
  102. EMC_DLL_XFORM_DQS6
  103. EMC_DLL_XFORM_DQS7
  104. EMC_DLL_XFORM_DQS8
  105. EMC_DLL_XFORM_DQS9
  106. EMC_DLL_XFORM_DQS10
  107. EMC_DLL_XFORM_DQS11
  108. EMC_DLL_XFORM_DQS12
  109. EMC_DLL_XFORM_DQS13
  110. EMC_DLL_XFORM_DQS14
  111. EMC_DLL_XFORM_DQS15
  112. EMC_DLL_XFORM_QUSE0
  113. EMC_DLL_XFORM_QUSE1
  114. EMC_DLL_XFORM_QUSE2
  115. EMC_DLL_XFORM_QUSE3
  116. EMC_DLL_XFORM_QUSE4
  117. EMC_DLL_XFORM_QUSE5
  118. EMC_DLL_XFORM_QUSE6
  119. EMC_DLL_XFORM_QUSE7
  120. EMC_DLL_XFORM_ADDR0
  121. EMC_DLL_XFORM_ADDR1
  122. EMC_DLL_XFORM_ADDR2
  123. EMC_DLL_XFORM_ADDR3
  124. EMC_DLL_XFORM_ADDR4
  125. EMC_DLL_XFORM_ADDR5
  126. EMC_DLL_XFORM_QUSE8
  127. EMC_DLL_XFORM_QUSE9
  128. EMC_DLL_XFORM_QUSE10
  129. EMC_DLL_XFORM_QUSE11
  130. EMC_DLL_XFORM_QUSE12
  131. EMC_DLL_XFORM_QUSE13
  132. EMC_DLL_XFORM_QUSE14
  133. EMC_DLL_XFORM_QUSE15
  134. EMC_DLI_TRIM_TXDQS0
  135. EMC_DLI_TRIM_TXDQS1
  136. EMC_DLI_TRIM_TXDQS2
  137. EMC_DLI_TRIM_TXDQS3
  138. EMC_DLI_TRIM_TXDQS4
  139. EMC_DLI_TRIM_TXDQS5
  140. EMC_DLI_TRIM_TXDQS6
  141. EMC_DLI_TRIM_TXDQS7
  142. EMC_DLI_TRIM_TXDQS8
  143. EMC_DLI_TRIM_TXDQS9
  144. EMC_DLI_TRIM_TXDQS10
  145. EMC_DLI_TRIM_TXDQS11
  146. EMC_DLI_TRIM_TXDQS12
  147. EMC_DLI_TRIM_TXDQS13
  148. EMC_DLI_TRIM_TXDQS14
  149. EMC_DLI_TRIM_TXDQS15
  150. EMC_DLL_XFORM_DQ0
  151. EMC_DLL_XFORM_DQ1
  152. EMC_DLL_XFORM_DQ2
  153. EMC_DLL_XFORM_DQ3
  154. EMC_DLL_XFORM_DQ4
  155. EMC_DLL_XFORM_DQ5
  156. EMC_DLL_XFORM_DQ6
  157. EMC_DLL_XFORM_DQ7
  158. EMC_XM2CMDPADCTRL
  159. EMC_XM2CMDPADCTRL4
  160. EMC_XM2CMDPADCTRL5
  161. EMC_XM2DQPADCTRL2
  162. EMC_XM2DQPADCTRL3
  163. EMC_XM2CLKPADCTRL
  164. EMC_XM2CLKPADCTRL2
  165. EMC_XM2COMPPADCTRL
  166. EMC_XM2VTTGENPADCTRL
  167. EMC_XM2VTTGENPADCTRL2
  168. EMC_XM2VTTGENPADCTRL3
  169. EMC_XM2DQSPADCTRL3
  170. EMC_XM2DQSPADCTRL4
  171. EMC_XM2DQSPADCTRL5
  172. EMC_XM2DQSPADCTRL6
  173. EMC_DSR_VTTGEN_DRV
  174. EMC_TXDSRVTTGEN
  175. EMC_FBIO_SPARE
  176. EMC_ZCAL_WAIT_CNT
  177. EMC_MRS_WAIT_CNT2
  178. EMC_CTT
  179. EMC_CTT_DURATION
  180. EMC_CFG_PIPE
  181. EMC_DYN_SELF_REF_CONTROL
  182. EMC_QPOP
  183. Example SoC include file:
  184. / {
  185. emc@0,7001b000 {
  186. compatible = "nvidia,tegra124-emc";
  187. reg = <0x0 0x7001b000 0x0 0x1000>;
  188. nvidia,memory-controller = <&mc>;
  189. };
  190. };
  191. Example board file:
  192. / {
  193. emc@0,7001b000 {
  194. emc-timings-3 {
  195. nvidia,ram-code = <3>;
  196. timing-12750000 {
  197. clock-frequency = <12750000>;
  198. nvidia,emc-zcal-cnt-long = <0x00000042>;
  199. nvidia,emc-auto-cal-interval = <0x001fffff>;
  200. nvidia,emc-ctt-term-ctrl = <0x00000802>;
  201. nvidia,emc-cfg = <0x73240000>;
  202. nvidia,emc-cfg-2 = <0x000008c5>;
  203. nvidia,emc-sel-dpd-ctrl = <0x00040128>;
  204. nvidia,emc-bgbias-ctl0 = <0x00000008>;
  205. nvidia,emc-auto-cal-config = <0xa1430000>;
  206. nvidia,emc-auto-cal-config2 = <0x00000000>;
  207. nvidia,emc-auto-cal-config3 = <0x00000000>;
  208. nvidia,emc-mode-reset = <0x80001221>;
  209. nvidia,emc-mode-1 = <0x80100003>;
  210. nvidia,emc-mode-2 = <0x80200008>;
  211. nvidia,emc-mode-4 = <0x00000000>;
  212. nvidia,emc-configuration = <
  213. 0x00000000 /* EMC_RC */
  214. 0x00000003 /* EMC_RFC */
  215. 0x00000000 /* EMC_RFC_SLR */
  216. 0x00000000 /* EMC_RAS */
  217. 0x00000000 /* EMC_RP */
  218. 0x00000004 /* EMC_R2W */
  219. 0x0000000a /* EMC_W2R */
  220. 0x00000003 /* EMC_R2P */
  221. 0x0000000b /* EMC_W2P */
  222. 0x00000000 /* EMC_RD_RCD */
  223. 0x00000000 /* EMC_WR_RCD */
  224. 0x00000003 /* EMC_RRD */
  225. 0x00000003 /* EMC_REXT */
  226. 0x00000000 /* EMC_WEXT */
  227. 0x00000006 /* EMC_WDV */
  228. 0x00000006 /* EMC_WDV_MASK */
  229. 0x00000006 /* EMC_QUSE */
  230. 0x00000002 /* EMC_QUSE_WIDTH */
  231. 0x00000000 /* EMC_IBDLY */
  232. 0x00000005 /* EMC_EINPUT */
  233. 0x00000005 /* EMC_EINPUT_DURATION */
  234. 0x00010000 /* EMC_PUTERM_EXTRA */
  235. 0x00000003 /* EMC_PUTERM_WIDTH */
  236. 0x00000000 /* EMC_PUTERM_ADJ */
  237. 0x00000000 /* EMC_CDB_CNTL_1 */
  238. 0x00000000 /* EMC_CDB_CNTL_2 */
  239. 0x00000000 /* EMC_CDB_CNTL_3 */
  240. 0x00000004 /* EMC_QRST */
  241. 0x0000000c /* EMC_QSAFE */
  242. 0x0000000d /* EMC_RDV */
  243. 0x0000000f /* EMC_RDV_MASK */
  244. 0x00000060 /* EMC_REFRESH */
  245. 0x00000000 /* EMC_BURST_REFRESH_NUM */
  246. 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */
  247. 0x00000002 /* EMC_PDEX2WR */
  248. 0x00000002 /* EMC_PDEX2RD */
  249. 0x00000001 /* EMC_PCHG2PDEN */
  250. 0x00000000 /* EMC_ACT2PDEN */
  251. 0x00000007 /* EMC_AR2PDEN */
  252. 0x0000000f /* EMC_RW2PDEN */
  253. 0x00000005 /* EMC_TXSR */
  254. 0x00000005 /* EMC_TXSRDLL */
  255. 0x00000004 /* EMC_TCKE */
  256. 0x00000005 /* EMC_TCKESR */
  257. 0x00000004 /* EMC_TPD */
  258. 0x00000000 /* EMC_TFAW */
  259. 0x00000000 /* EMC_TRPAB */
  260. 0x00000005 /* EMC_TCLKSTABLE */
  261. 0x00000005 /* EMC_TCLKSTOP */
  262. 0x00000064 /* EMC_TREFBW */
  263. 0x00000000 /* EMC_FBIO_CFG6 */
  264. 0x00000000 /* EMC_ODT_WRITE */
  265. 0x00000000 /* EMC_ODT_READ */
  266. 0x106aa298 /* EMC_FBIO_CFG5 */
  267. 0x002c00a0 /* EMC_CFG_DIG_DLL */
  268. 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
  269. 0x00064000 /* EMC_DLL_XFORM_DQS0 */
  270. 0x00064000 /* EMC_DLL_XFORM_DQS1 */
  271. 0x00064000 /* EMC_DLL_XFORM_DQS2 */
  272. 0x00064000 /* EMC_DLL_XFORM_DQS3 */
  273. 0x00064000 /* EMC_DLL_XFORM_DQS4 */
  274. 0x00064000 /* EMC_DLL_XFORM_DQS5 */
  275. 0x00064000 /* EMC_DLL_XFORM_DQS6 */
  276. 0x00064000 /* EMC_DLL_XFORM_DQS7 */
  277. 0x00064000 /* EMC_DLL_XFORM_DQS8 */
  278. 0x00064000 /* EMC_DLL_XFORM_DQS9 */
  279. 0x00064000 /* EMC_DLL_XFORM_DQS10 */
  280. 0x00064000 /* EMC_DLL_XFORM_DQS11 */
  281. 0x00064000 /* EMC_DLL_XFORM_DQS12 */
  282. 0x00064000 /* EMC_DLL_XFORM_DQS13 */
  283. 0x00064000 /* EMC_DLL_XFORM_DQS14 */
  284. 0x00064000 /* EMC_DLL_XFORM_DQS15 */
  285. 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
  286. 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
  287. 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
  288. 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
  289. 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
  290. 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
  291. 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
  292. 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
  293. 0x00000000 /* EMC_DLL_XFORM_ADDR0 */
  294. 0x00000000 /* EMC_DLL_XFORM_ADDR1 */
  295. 0x00000000 /* EMC_DLL_XFORM_ADDR2 */
  296. 0x00000000 /* EMC_DLL_XFORM_ADDR3 */
  297. 0x00000000 /* EMC_DLL_XFORM_ADDR4 */
  298. 0x00000000 /* EMC_DLL_XFORM_ADDR5 */
  299. 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
  300. 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
  301. 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
  302. 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
  303. 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
  304. 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
  305. 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
  306. 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
  307. 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
  308. 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
  309. 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
  310. 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
  311. 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
  312. 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
  313. 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
  314. 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
  315. 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
  316. 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
  317. 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
  318. 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
  319. 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
  320. 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
  321. 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
  322. 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
  323. 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
  324. 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
  325. 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
  326. 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
  327. 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */
  328. 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */
  329. 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */
  330. 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */
  331. 0x10000280 /* EMC_XM2CMDPADCTRL */
  332. 0x00000000 /* EMC_XM2CMDPADCTRL4 */
  333. 0x00111111 /* EMC_XM2CMDPADCTRL5 */
  334. 0x00000000 /* EMC_XM2DQPADCTRL2 */
  335. 0x00000000 /* EMC_XM2DQPADCTRL3 */
  336. 0x77ffc081 /* EMC_XM2CLKPADCTRL */
  337. 0x00000e0e /* EMC_XM2CLKPADCTRL2 */
  338. 0x81f1f108 /* EMC_XM2COMPPADCTRL */
  339. 0x07070004 /* EMC_XM2VTTGENPADCTRL */
  340. 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */
  341. 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
  342. 0x51451400 /* EMC_XM2DQSPADCTRL3 */
  343. 0x00514514 /* EMC_XM2DQSPADCTRL4 */
  344. 0x00514514 /* EMC_XM2DQSPADCTRL5 */
  345. 0x51451400 /* EMC_XM2DQSPADCTRL6 */
  346. 0x0000003f /* EMC_DSR_VTTGEN_DRV */
  347. 0x00000007 /* EMC_TXDSRVTTGEN */
  348. 0x00000000 /* EMC_FBIO_SPARE */
  349. 0x00000042 /* EMC_ZCAL_WAIT_CNT */
  350. 0x000e000e /* EMC_MRS_WAIT_CNT2 */
  351. 0x00000000 /* EMC_CTT */
  352. 0x00000003 /* EMC_CTT_DURATION */
  353. 0x0000f2f3 /* EMC_CFG_PIPE */
  354. 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */
  355. 0x0000000a /* EMC_QPOP */
  356. >;
  357. };
  358. };
  359. };
  360. };