gpio-control-nand.txt 1.6 KB

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  1. GPIO assisted NAND flash
  2. The GPIO assisted NAND flash uses a memory mapped interface to
  3. read/write the NAND commands and data and GPIO pins for the control
  4. signals.
  5. Required properties:
  6. - compatible : "gpio-control-nand"
  7. - reg : should specify localbus chip select and size used for the chip. The
  8. resource describes the data bus connected to the NAND flash and all accesses
  9. are made in native endianness.
  10. - #address-cells, #size-cells : Must be present if the device has sub-nodes
  11. representing partitions.
  12. - gpios : Specifies the GPIO pins to control the NAND device. The order of
  13. GPIO references is: RDY, nCE, ALE, CLE, and an optional nWP.
  14. Optional properties:
  15. - bank-width : Width (in bytes) of the device. If not present, the width
  16. defaults to 1 byte.
  17. - chip-delay : chip dependent delay for transferring data from array to
  18. read registers (tR). If not present then a default of 20us is used.
  19. - gpio-control-nand,io-sync-reg : A 64-bit physical address for a read
  20. location used to guard against bus reordering with regards to accesses to
  21. the GPIO's and the NAND flash data bus. If present, then after changing
  22. GPIO state and before and after command byte writes, this register will be
  23. read to ensure that the GPIO accesses have completed.
  24. The device tree may optionally contain sub-nodes describing partitions of the
  25. address space. See partition.txt for more detail.
  26. Examples:
  27. gpio-nand@1,0 {
  28. compatible = "gpio-control-nand";
  29. reg = <1 0x0000 0x2>;
  30. #address-cells = <1>;
  31. #size-cells = <1>;
  32. gpios = <&banka 1 0>, /* RDY */
  33. <&banka 2 0>, /* nCE */
  34. <&banka 3 0>, /* ALE */
  35. <&banka 4 0>, /* CLE */
  36. <0>; /* nWP */
  37. partition@0 {
  38. ...
  39. };
  40. };