altera-pcie.txt 1.7 KB

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  1. * Altera PCIe controller
  2. Required properties:
  3. - compatible : should contain "altr,pcie-root-port-1.0"
  4. - reg: a list of physical base address and length for TXS and CRA.
  5. - reg-names: must include the following entries:
  6. "Txs": TX slave port region
  7. "Cra": Control register access region
  8. - interrupt-parent: interrupt source phandle.
  9. - interrupts: specifies the interrupt source of the parent interrupt controller.
  10. The format of the interrupt specifier depends on the parent interrupt
  11. controller.
  12. - device_type: must be "pci"
  13. - #address-cells: set to <3>
  14. - #size-cells: set to <2>
  15. - #interrupt-cells: set to <1>
  16. - ranges: describes the translation of addresses for root ports and standard
  17. PCI regions.
  18. - interrupt-map-mask and interrupt-map: standard PCI properties to define the
  19. mapping of the PCIe interface to interrupt numbers.
  20. Optional properties:
  21. - msi-parent: Link to the hardware entity that serves as the MSI controller for this PCIe
  22. controller.
  23. - bus-range: PCI bus numbers covered
  24. Example
  25. pcie_0: pcie@0xc00000000 {
  26. compatible = "altr,pcie-root-port-1.0";
  27. reg = <0xc0000000 0x20000000>,
  28. <0xff220000 0x00004000>;
  29. reg-names = "Txs", "Cra";
  30. interrupt-parent = <&hps_0_arm_gic_0>;
  31. interrupts = <0 40 4>;
  32. interrupt-controller;
  33. #interrupt-cells = <1>;
  34. bus-range = <0x0 0xFF>;
  35. device_type = "pci";
  36. msi-parent = <&msi_to_gic_gen_0>;
  37. #address-cells = <3>;
  38. #size-cells = <2>;
  39. interrupt-map-mask = <0 0 0 7>;
  40. interrupt-map = <0 0 0 1 &pcie_0 1>,
  41. <0 0 0 2 &pcie_0 2>,
  42. <0 0 0 3 &pcie_0 3>,
  43. <0 0 0 4 &pcie_0 4>;
  44. ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000
  45. 0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>;
  46. };