fsl,imx27-pinctrl.txt 3.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121
  1. * Freescale IMX27 IOMUX Controller
  2. Required properties:
  3. - compatible: "fsl,imx27-iomuxc"
  4. The iomuxc driver node should define subnodes containing of pinctrl configuration subnodes.
  5. Required properties for pin configuration node:
  6. - fsl,pins: three integers array, represents a group of pins mux and config
  7. setting. The format is fsl,pins = <PIN MUX_ID CONFIG>.
  8. PIN is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable
  9. configurable pins each. PIN is PORT * 32 + PORT_PIN, PORT_PIN is the pin
  10. number on the specific port (between 0 and 31).
  11. MUX_ID is
  12. function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10)
  13. function value is used to select the pin function.
  14. Possible values:
  15. 0 - Primary function
  16. 1 - Alternate function
  17. 2 - GPIO
  18. Registers: GIUS (GPIO In Use), GPR (General Purpose Register)
  19. direction defines the data direction of the pin.
  20. Possible values:
  21. 0 - Input
  22. 1 - Output
  23. Register: DDIR
  24. gpio_oconf configures the gpio submodule output signal. This does not
  25. have any effect unless GPIO function is selected. A/B/C_IN are output
  26. signals of function blocks A,B and C. Specific function blocks are
  27. described in the reference manual.
  28. Possible values:
  29. 0 - A_IN
  30. 1 - B_IN
  31. 2 - C_IN
  32. 3 - Data Register
  33. Registers: OCR1, OCR2
  34. gpio_iconfa/b configures the gpio submodule input to functionblocks A and
  35. B. GPIO function should be selected if this is configured.
  36. Possible values:
  37. 0 - GPIO_IN
  38. 1 - Interrupt Status Register
  39. 2 - Pulldown
  40. 3 - Pullup
  41. Registers ICONFA1, ICONFA2, ICONFB1 and ICONFB2
  42. CONFIG can be 0 or 1, meaning Pullup disable/enable.
  43. The iomux controller has gpio child nodes which are embedded in the iomux
  44. control registers. They have to be defined as child nodes of the iomux device
  45. node. If gpio subnodes are defined "#address-cells", "#size-cells" and "ranges"
  46. properties for the iomux device node are required.
  47. Example:
  48. iomuxc: iomuxc@10015000 {
  49. compatible = "fsl,imx27-iomuxc";
  50. reg = <0x10015000 0x600>;
  51. #address-cells = <1>;
  52. #size-cells = <1>;
  53. ranges;
  54. gpio1: gpio@10015000 {
  55. ...
  56. };
  57. ...
  58. uart {
  59. pinctrl_uart1: uart-1 {
  60. fsl,pins = <
  61. 0x8c 0x004 0x0 /* UART1_TXD__UART1_TXD */
  62. 0x8d 0x000 0x0 /* UART1_RXD__UART1_RXD */
  63. 0x8e 0x004 0x0 /* UART1_CTS__UART1_CTS */
  64. 0x8f 0x000 0x0 /* UART1_RTS__UART1_RTS */
  65. >;
  66. };
  67. ...
  68. };
  69. };
  70. For convenience there are macros defined in imx27-pinfunc.h which provide PIN
  71. and MUX_ID. They are structured as MX27_PAD_<Pad name>__<Signal name>. The names
  72. are defined in the i.MX27 reference manual.
  73. The above example using macros:
  74. iomuxc: iomuxc@10015000 {
  75. compatible = "fsl,imx27-iomuxc";
  76. reg = <0x10015000 0x600>;
  77. #address-cells = <1>;
  78. #size-cells = <1>;
  79. ranges;
  80. gpio1: gpio@10015000 {
  81. ...
  82. };
  83. ...
  84. uart {
  85. pinctrl_uart1: uart-1 {
  86. fsl,pins = <
  87. MX27_PAD_UART1_TXD__UART1_TXD 0x0
  88. MX27_PAD_UART1_RXD__UART1_RXD 0x0
  89. MX27_PAD_UART1_CTS__UART1_CTS 0x0
  90. MX27_PAD_UART1_RTS__UART1_RTS 0x0
  91. >;
  92. };
  93. ...
  94. };
  95. };