lantiq,pinctrl-xway.txt 3.1 KB

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  1. Lantiq XWAY pinmux controller
  2. Required properties:
  3. - compatible: "lantiq,pinctrl-xway" or "lantiq,pinctrl-xr9"
  4. - reg: Should contain the physical address and length of the gpio/pinmux
  5. register range
  6. Please refer to pinctrl-bindings.txt in this directory for details of the
  7. common pinctrl bindings used by client devices, including the meaning of the
  8. phrase "pin configuration node".
  9. Lantiq's pin configuration nodes act as a container for an arbitrary number of
  10. subnodes. Each of these subnodes represents some desired configuration for a
  11. pin, a group, or a list of pins or groups. This configuration can include the
  12. mux function to select on those group(s), and two pin configuration parameters:
  13. pull-up and open-drain
  14. The name of each subnode is not important as long as it is unique; all subnodes
  15. should be enumerated and processed purely based on their content.
  16. Each subnode only affects those parameters that are explicitly listed. In
  17. other words, a subnode that lists a mux function but no pin configuration
  18. parameters implies no information about any pin configuration parameters.
  19. Similarly, a pin subnode that describes a pullup parameter implies no
  20. information about e.g. the mux function.
  21. We support 2 types of nodes.
  22. Definition of mux function groups:
  23. Required subnode-properties:
  24. - lantiq,groups : An array of strings. Each string contains the name of a group.
  25. Valid values for these names are listed below.
  26. - lantiq,function: A string containing the name of the function to mux to the
  27. group. Valid values for function names are listed below.
  28. Valid values for group and function names:
  29. mux groups:
  30. exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1,
  31. ebu wait, nand ale, nand cs1, nand cle, spi, spi_cs1, spi_cs2, spi_cs3,
  32. spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi , gpt1, gpt2,
  33. gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, gnt2, gnt3, req1, req2,
  34. req3
  35. additional mux groups (XR9 only):
  36. mdio, nand rdy, nand rd, exin3, exin4, gnt4, req4
  37. functions:
  38. spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, mdio
  39. Definition of pin configurations:
  40. Required subnode-properties:
  41. - lantiq,pins : An array of strings. Each string contains the name of a pin.
  42. Valid values for these names are listed below.
  43. Optional subnode-properties:
  44. - lantiq,pull: Integer, representing the pull-down/up to apply to the pin.
  45. 0: none, 1: down, 2: up.
  46. - lantiq,open-drain: Boolean, enables open-drain on the defined pin.
  47. Valid values for XWAY pin names:
  48. Pinconf pins can be referenced via the names io0-io31.
  49. Valid values for XR9 pin names:
  50. Pinconf pins can be referenced via the names io0-io55.
  51. Example:
  52. gpio: pinmux@E100B10 {
  53. compatible = "lantiq,pinctrl-xway";
  54. pinctrl-names = "default";
  55. pinctrl-0 = <&state_default>;
  56. #gpio-cells = <2>;
  57. gpio-controller;
  58. reg = <0xE100B10 0xA0>;
  59. state_default: pinmux {
  60. stp {
  61. lantiq,groups = "stp";
  62. lantiq,function = "stp";
  63. };
  64. pci {
  65. lantiq,groups = "gnt1";
  66. lantiq,function = "pci";
  67. };
  68. conf_out {
  69. lantiq,pins = "io4", "io5", "io6"; /* stp */
  70. lantiq,open-drain;
  71. lantiq,pull = <0>;
  72. };
  73. };
  74. };