marvell,dove-pinctrl.txt 4.5 KB

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  1. * Marvell Dove SoC pinctrl driver for mpp
  2. Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
  3. part and usage.
  4. Required properties:
  5. - compatible: "marvell,dove-pinctrl"
  6. - clocks: (optional) phandle of pdma clock
  7. - reg: register specifiers of MPP, MPP4, and PMU MPP registers
  8. Available mpp pins/groups and functions:
  9. Note: brackets (x) are not part of the mpp name for marvell,function and given
  10. only for more detailed description in this document.
  11. Note: pmu* also allows for Power Management functions listed below
  12. name pins functions
  13. ================================================================================
  14. mpp0 0 gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm), pmu*
  15. mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm), pmu*
  16. mpp2 2 gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
  17. uart1(rts), pmu*
  18. mpp3 3 gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act),
  19. uart1(cts), lcd-spi(cs1), pmu*
  20. mpp4 4 gpio, pmu, uart3(rts), sdio1(cd), spi1(miso), pmu*
  21. mpp5 5 gpio, pmu, uart3(cts), sdio1(wp), spi1(cs), pmu*
  22. mpp6 6 gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi), pmu*
  23. mpp7 7 gpio, pmu, uart3(rxd), sdio1(ledctrl), spi1(sck), pmu*
  24. mpp8 8 gpio, pmu, watchdog(rstout), pmu*
  25. mpp9 9 gpio, pmu, pex1(clkreq), pmu*
  26. mpp10 10 gpio, pmu, ssp(sclk), pmu*
  27. mpp11 11 gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
  28. sdio1(ledctrl), pex0(clkreq), pmu*
  29. mpp12 12 gpio, pmu, uart2(rts), audio0(extclk), sdio1(cd),
  30. sata(act), pmu*
  31. mpp13 13 gpio, pmu, uart2(cts), audio1(extclk), sdio1(wp),
  32. ssp(extclk), pmu*
  33. mpp14 14 gpio, pmu, uart2(txd), sdio1(buspwr), ssp(rxd), pmu*
  34. mpp15 15 gpio, pmu, uart2(rxd), sdio1(ledctrl), ssp(sfrm), pmu*
  35. mpp16 16 gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)
  36. mpp17 17 gpio, uart3(cts), sdio0(wp), ac97(sdi2), twsi(sda),
  37. ac97-1(sysclko)
  38. mpp18 18 gpio, uart3(txd), sdio0(buspwr), ac97(sdi3), lcd0(pwm)
  39. mpp19 19 gpio, uart3(rxd), sdio0(ledctrl), twsi(sck)
  40. mpp20 20 gpio, sdio0(cd), sdio1(cd), spi1(miso), lcd-spi(miso),
  41. ac97(sysclko)
  42. mpp21 21 gpio, sdio0(wp), sdio1(wp), spi1(cs), lcd-spi(cs0),
  43. uart1(cts), ssp(sfrm)
  44. mpp22 22 gpio, sdio0(buspwr), sdio1(buspwr), spi1(mosi),
  45. lcd-spi(mosi), uart1(cts), ssp(txd)
  46. mpp23 23 gpio, sdio0(ledctrl), sdio1(ledctrl), spi1(sck),
  47. lcd-spi(sck), ssp(sclk)
  48. mpp_camera 24-39 gpio, camera
  49. mpp_sdio0 40-45 gpio, sdio0
  50. mpp_sdio1 46-51 gpio, sdio1
  51. mpp_audio1 52-57 gpio, i2s1/spdifo, i2s1, spdifo, twsi, ssp/spdifo, ssp,
  52. ssp/twsi
  53. mpp_spi0 58-61 gpio, spi0
  54. mpp_uart1 62-63 gpio, uart1
  55. mpp_nand 64-71 gpo, nand
  56. audio0 - i2s, ac97
  57. twsi - none, opt1, opt2, opt3
  58. Power Management functions (pmu*):
  59. pmu-nc Pin not driven by any PM function
  60. pmu-low Pin driven low (0)
  61. pmu-high Pin driven high (1)
  62. pmic(sdi) Pin is used for PMIC SDI
  63. cpu-pwr-down Pin is used for CPU_PWRDWN
  64. standby-pwr-down Pin is used for STBY_PWRDWN
  65. core-pwr-good Pin is used for CORE_PWR_GOOD (Pins 0-7 only)
  66. cpu-pwr-good Pin is used for CPU_PWR_GOOD (Pins 8-15 only)
  67. bat-fault Pin is used for BATTERY_FAULT
  68. ext0-wakeup Pin is used for EXT0_WU
  69. ext1-wakeup Pin is used for EXT0_WU
  70. ext2-wakeup Pin is used for EXT0_WU
  71. pmu-blink Pin is used for blink function
  72. Notes:
  73. * group "mpp_audio1" allows the following functions and gpio pins:
  74. - gpio : gpio on pins 52-57
  75. - i2s1/spdifo : audio1 i2s on pins 52-55 and spdifo on 57, no gpios
  76. - i2s1 : audio1 i2s on pins 52-55, gpio on pins 56,57
  77. - spdifo : spdifo on pin 57, gpio on pins 52-55
  78. - twsi : twsi on pins 56,57, gpio on pins 52-55
  79. - ssp/spdifo : ssp on pins 52-55, spdifo on pin 57, no gpios
  80. - ssp : ssp on pins 52-55, gpio on pins 56,57
  81. - ssp/twsi : ssp on pins 52-55, twsi on pins 56,57, no gpios
  82. * group "audio0" internally muxes i2s0 or ac97 controller to the dedicated
  83. audio0 pins.
  84. * group "twsi" internally muxes twsi controller to the dedicated or option pins.