pinctrl-st.txt 5.1 KB

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  1. *ST pin controller.
  2. Each multi-function pin is controlled, driven and routed through the
  3. PIO multiplexing block. Each pin supports GPIO functionality (ALT0)
  4. and multiple alternate functions(ALT1 - ALTx) that directly connect
  5. the pin to different hardware blocks.
  6. When a pin is in GPIO mode, Output Enable (OE), Open Drain(OD), and
  7. Pull Up (PU) are driven by the related PIO block.
  8. ST pinctrl driver controls PIO multiplexing block and also interacts with
  9. gpio driver to configure a pin.
  10. GPIO bank can have one of the two possible types of interrupt-wirings.
  11. First type is via irqmux, single interrupt is used by multiple gpio banks. This
  12. reduces number of overall interrupts numbers required. All these banks belong to
  13. a single pincontroller.
  14. _________
  15. | |----> [gpio-bank (n) ]
  16. | |----> [gpio-bank (n + 1)]
  17. [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
  18. | |----> [gpio-bank (... )]
  19. |_________|----> [gpio-bank (n + 7)]
  20. Second type has a dedicated interrupt per gpio bank.
  21. [irqN]----> [gpio-bank (n)]
  22. Pin controller node:
  23. Required properties:
  24. - compatible : should be "st,<SOC>-<pio-block>-pinctrl"
  25. like st,stih415-sbc-pinctrl, st,stih415-front-pinctrl and so on.
  26. - st,syscfg : Should be a phandle of the syscfg node.
  27. - st,retime-pin-mask : Should be mask to specify which pins can be retimed.
  28. If the property is not present, it is assumed that all the pins in the
  29. bank are capable of retiming. Retiming is mainly used to improve the
  30. IO timing margins of external synchronous interfaces.
  31. - ranges : defines mapping between pin controller node (parent) to gpio-bank
  32. node (children).
  33. Optional properties:
  34. - interrupts : Interrupt number of the irqmux. If the interrupt is shared
  35. with other gpio banks via irqmux.
  36. a irqline and gpio banks.
  37. - reg : irqmux memory resource. If irqmux is present.
  38. - reg-names : irqmux resource should be named as "irqmux".
  39. GPIO controller/bank node.
  40. Required properties:
  41. - gpio-controller : Indicates this device is a GPIO controller
  42. - #gpio-cells : Should be one. The first cell is the pin number.
  43. - st,bank-name : Should be a name string for this bank as specified in
  44. datasheet.
  45. Optional properties:
  46. - interrupts : Interrupt number for this gpio bank. If there is a dedicated
  47. interrupt wired up for this gpio bank.
  48. - interrupt-controller : Indicates this device is a interrupt controller. GPIO
  49. bank can be an interrupt controller iff one of the interrupt type either via
  50. irqmux or a dedicated interrupt per bank is specified.
  51. - #interrupt-cells: the value of this property should be 2.
  52. - First Cell: represents the external gpio interrupt number local to the
  53. gpio interrupt space of the controller.
  54. - Second Cell: flags to identify the type of the interrupt
  55. - 1 = rising edge triggered
  56. - 2 = falling edge triggered
  57. - 3 = rising and falling edge triggered
  58. - 4 = high level triggered
  59. - 8 = low level triggered
  60. for related macros look in:
  61. include/dt-bindings/interrupt-controller/irq.h
  62. Example:
  63. pin-controller-sbc {
  64. #address-cells = <1>;
  65. #size-cells = <1>;
  66. compatible = "st,stih415-sbc-pinctrl";
  67. st,syscfg = <&syscfg_sbc>;
  68. reg = <0xfe61f080 0x4>;
  69. reg-names = "irqmux";
  70. interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
  71. interrupt-names = "irqmux";
  72. ranges = <0 0xfe610000 0x5000>;
  73. PIO0: gpio@fe610000 {
  74. gpio-controller;
  75. #gpio-cells = <1>;
  76. interrupt-controller;
  77. #interrupt-cells = <2>;
  78. reg = <0 0x100>;
  79. st,bank-name = "PIO0";
  80. };
  81. ...
  82. pin-functions nodes follow...
  83. };
  84. Contents of function subnode node:
  85. ----------------------
  86. Required properties for pin configuration node:
  87. - st,pins : Child node with list of pins with configuration.
  88. Below is the format of how each pin conf should look like.
  89. <bank offset mux mode rt_type rt_delay rt_clk>
  90. Every PIO is represented with 4-7 parameters depending on retime configuration.
  91. Each parameter is explained as below.
  92. -bank : Should be bank phandle to which this PIO belongs.
  93. -offset : Offset in the PIO bank.
  94. -mux : Should be alternate function number associated this pin.
  95. Use same numbers from datasheet.
  96. -mode :pin configuration is selected from one of the below values.
  97. IN
  98. IN_PU
  99. OUT
  100. BIDIR
  101. BIDIR_PU
  102. -rt_type Retiming Configuration for the pin.
  103. Possible retime configuration are:
  104. ------- -------------
  105. value args
  106. ------- -------------
  107. NICLK <delay> <clk>
  108. ICLK_IO <delay> <clk>
  109. BYPASS <delay>
  110. DE_IO <delay> <clk>
  111. SE_ICLK_IO <delay> <clk>
  112. SE_NICLK_IO <delay> <clk>
  113. - delay is retime delay in pico seconds as mentioned in data sheet.
  114. - rt_clk :clk to be use for retime.
  115. Possible values are:
  116. CLK_A
  117. CLK_B
  118. CLK_C
  119. CLK_D
  120. Example of mmcclk pin which is a bi-direction pull pu with retime config
  121. as non inverted clock retimed with CLK_B and delay of 0 pico seconds:
  122. pin-controller {
  123. ...
  124. mmc0 {
  125. pinctrl_mmc: mmc {
  126. st,pins {
  127. mmcclk = <&PIO13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>;
  128. ...
  129. };
  130. };
  131. ...
  132. };
  133. };
  134. sdhci0:sdhci@fe810000{
  135. ...
  136. interrupt-parent = <&PIO3>;
  137. #interrupt-cells = <2>;
  138. interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; /* Interrupt line via PIO3-3 */
  139. interrupt-names = "card-detect";
  140. pinctrl-names = "default";
  141. pinctrl-0 = <&pinctrl_mmc>;
  142. };