fsl-sai.txt 2.7 KB

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  1. Freescale Synchronous Audio Interface (SAI).
  2. The SAI is based on I2S module that used communicating with audio codecs,
  3. which provides a synchronous audio interface that supports fullduplex
  4. serial interfaces with frame synchronization such as I2S, AC97, TDM, and
  5. codec/DSP interfaces.
  6. Required properties:
  7. - compatible : Compatible list, contains "fsl,vf610-sai" or
  8. "fsl,imx6sx-sai".
  9. - reg : Offset and length of the register set for the device.
  10. - clocks : Must contain an entry for each entry in clock-names.
  11. - clock-names : Must include the "bus" for register access and
  12. "mclk1", "mclk2", "mclk3" for bit clock and frame
  13. clock providing.
  14. - dmas : Generic dma devicetree binding as described in
  15. Documentation/devicetree/bindings/dma/dma.txt.
  16. - dma-names : Two dmas have to be defined, "tx" and "rx".
  17. - pinctrl-names : Must contain a "default" entry.
  18. - pinctrl-NNN : One property must exist for each entry in
  19. pinctrl-names. See ../pinctrl/pinctrl-bindings.txt
  20. for details of the property values.
  21. - big-endian : Boolean property, required if all the FTM_PWM
  22. registers are big-endian rather than little-endian.
  23. - lsb-first : Configures whether the LSB or the MSB is transmitted
  24. first for the fifo data. If this property is absent,
  25. the MSB is transmitted first as default, or the LSB
  26. is transmitted first.
  27. - fsl,sai-synchronous-rx: This is a boolean property. If present, indicating
  28. that SAI will work in the synchronous mode (sync Tx
  29. with Rx) which means both the transimitter and the
  30. receiver will send and receive data by following
  31. receiver's bit clocks and frame sync clocks.
  32. - fsl,sai-asynchronous: This is a boolean property. If present, indicating
  33. that SAI will work in the asynchronous mode, which
  34. means both transimitter and receiver will send and
  35. receive data by following their own bit clocks and
  36. frame sync clocks separately.
  37. Note:
  38. - If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the
  39. default synchronous mode (sync Rx with Tx) will be used, which means both
  40. transimitter and receiver will send and receive data by following clocks
  41. of transimitter.
  42. - fsl,sai-asynchronous and fsl,sai-synchronous-rx are exclusive.
  43. Example:
  44. sai2: sai@40031000 {
  45. compatible = "fsl,vf610-sai";
  46. reg = <0x40031000 0x1000>;
  47. pinctrl-names = "default";
  48. pinctrl-0 = <&pinctrl_sai2_1>;
  49. clocks = <&clks VF610_CLK_PLATFORM_BUS>,
  50. <&clks VF610_CLK_SAI2>,
  51. <&clks 0>, <&clks 0>;
  52. clock-names = "bus", "mclk1", "mclk2", "mclk3";
  53. dma-names = "tx", "rx";
  54. dmas = <&edma0 0 VF610_EDMA_MUXID0_SAI2_TX>,
  55. <&edma0 0 VF610_EDMA_MUXID0_SAI2_RX>;
  56. big-endian;
  57. lsb-first;
  58. };