spi-bus.txt 3.6 KB

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  1. SPI (Serial Peripheral Interface) busses
  2. SPI busses can be described with a node for the SPI master device
  3. and a set of child nodes for each SPI slave on the bus. For this
  4. discussion, it is assumed that the system's SPI controller is in
  5. SPI master mode. This binding does not describe SPI controllers
  6. in slave mode.
  7. The SPI master node requires the following properties:
  8. - #address-cells - number of cells required to define a chip select
  9. address on the SPI bus.
  10. - #size-cells - should be zero.
  11. - compatible - name of SPI bus controller following generic names
  12. recommended practice.
  13. - cs-gpios - (optional) gpios chip select.
  14. No other properties are required in the SPI bus node. It is assumed
  15. that a driver for an SPI bus device will understand that it is an SPI bus.
  16. However, the binding does not attempt to define the specific method for
  17. assigning chip select numbers. Since SPI chip select configuration is
  18. flexible and non-standardized, it is left out of this binding with the
  19. assumption that board specific platform code will be used to manage
  20. chip selects. Individual drivers can define additional properties to
  21. support describing the chip select layout.
  22. Optional property:
  23. - num-cs : total number of chipselects
  24. If cs-gpios is used the number of chip select will automatically increased
  25. with max(cs-gpios > hw cs)
  26. So if for example the controller has 2 CS lines, and the cs-gpios
  27. property looks like this:
  28. cs-gpios = <&gpio1 0 0> <0> <&gpio1 1 0> <&gpio1 2 0>;
  29. Then it should be configured so that num_chipselect = 4 with the
  30. following mapping:
  31. cs0 : &gpio1 0 0
  32. cs1 : native
  33. cs2 : &gpio1 1 0
  34. cs3 : &gpio1 2 0
  35. SPI slave nodes must be children of the SPI master node and can
  36. contain the following properties.
  37. - reg - (required) chip select address of device.
  38. - compatible - (required) name of SPI device following generic names
  39. recommended practice
  40. - spi-max-frequency - (required) Maximum SPI clocking speed of device in Hz
  41. - spi-cpol - (optional) Empty property indicating device requires
  42. inverse clock polarity (CPOL) mode
  43. - spi-cpha - (optional) Empty property indicating device requires
  44. shifted clock phase (CPHA) mode
  45. - spi-cs-high - (optional) Empty property indicating device requires
  46. chip select active high
  47. - spi-3wire - (optional) Empty property indicating device requires
  48. 3-wire mode.
  49. - spi-lsb-first - (optional) Empty property indicating device requires
  50. LSB first mode.
  51. - spi-tx-bus-width - (optional) The bus width(number of data wires) that
  52. used for MOSI. Defaults to 1 if not present.
  53. - spi-rx-bus-width - (optional) The bus width(number of data wires) that
  54. used for MISO. Defaults to 1 if not present.
  55. Some SPI controllers and devices support Dual and Quad SPI transfer mode.
  56. It allows data in the SPI system to be transferred in 2 wires(DUAL) or 4 wires(QUAD).
  57. Now the value that spi-tx-bus-width and spi-rx-bus-width can receive is
  58. only 1(SINGLE), 2(DUAL) and 4(QUAD).
  59. Dual/Quad mode is not allowed when 3-wire mode is used.
  60. If a gpio chipselect is used for the SPI slave the gpio number will be passed
  61. via the SPI master node cs-gpios property.
  62. SPI example for an MPC5200 SPI bus:
  63. spi@f00 {
  64. #address-cells = <1>;
  65. #size-cells = <0>;
  66. compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
  67. reg = <0xf00 0x20>;
  68. interrupts = <2 13 0 2 14 0>;
  69. interrupt-parent = <&mpc5200_pic>;
  70. ethernet-switch@0 {
  71. compatible = "micrel,ks8995m";
  72. spi-max-frequency = <1000000>;
  73. reg = <0>;
  74. };
  75. codec@1 {
  76. compatible = "ti,tlv320aic26";
  77. spi-max-frequency = <100000>;
  78. reg = <1>;
  79. };
  80. };