dwc3.txt 2.7 KB

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  1. synopsys DWC3 CORE
  2. DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties
  3. as described in 'usb/generic.txt'
  4. Required properties:
  5. - compatible: must be "snps,dwc3"
  6. - reg : Address and length of the register set for the device
  7. - interrupts: Interrupts used by the dwc3 controller.
  8. Optional properties:
  9. - usb-phy : array of phandle for the PHY device. The first element
  10. in the array is expected to be a handle to the USB2/HS PHY and
  11. the second element is expected to be a handle to the USB3/SS PHY
  12. - phys: from the *Generic PHY* bindings
  13. - phy-names: from the *Generic PHY* bindings
  14. - tx-fifo-resize: determines if the FIFO *has* to be reallocated.
  15. - snps,usb3_lpm_capable: determines if platform is USB3 LPM capable
  16. - snps,disable_scramble_quirk: true when SW should disable data scrambling.
  17. Only really useful for FPGA builds.
  18. - snps,has-lpm-erratum: true when DWC3 was configured with LPM Erratum enabled
  19. - snps,lpm-nyet-threshold: LPM NYET threshold
  20. - snps,u2exit_lfps_quirk: set if we want to enable u2exit lfps quirk
  21. - snps,u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
  22. - snps,req_p1p2p3_quirk: when set, the core will always request for
  23. P1/P2/P3 transition sequence.
  24. - snps,del_p1p2p3_quirk: when set core will delay P1/P2/P3 until a certain
  25. amount of 8B10B errors occur.
  26. - snps,del_phy_power_chg_quirk: when set core will delay PHY power change
  27. from P0 to P1/P2/P3.
  28. - snps,lfps_filter_quirk: when set core will filter LFPS reception.
  29. - snps,rx_detect_poll_quirk: when set core will disable a 400us delay to start
  30. Polling LFPS after RX.Detect.
  31. - snps,tx_de_emphasis_quirk: when set core will set Tx de-emphasis value.
  32. - snps,tx_de_emphasis: the value driven to the PHY is controlled by the
  33. LTSSM during USB3 Compliance mode.
  34. - snps,dis_u3_susphy_quirk: when set core will disable USB3 suspend phy.
  35. - snps,dis_u2_susphy_quirk: when set core will disable USB2 suspend phy.
  36. - snps,dis_enblslpm_quirk: when set clears the enblslpm in GUSB2PHYCFG,
  37. disabling the suspend signal to the PHY.
  38. - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal
  39. utmi_l1_suspend_n, false when asserts utmi_sleep_n
  40. - snps,hird-threshold: HIRD threshold
  41. - snps,hsphy_interface: High-Speed PHY interface selection between "utmi" for
  42. UTMI+ and "ulpi" for ULPI when the DWC_USB3_HSPHY_INTERFACE has value 3.
  43. - snps,quirk-frame-length-adjustment: Value for GFLADJ_30MHZ field of GFLADJ
  44. register for post-silicon frame length adjustment when the
  45. fladj_30mhz_sdbnd signal is invalid or incorrect.
  46. This is usually a subnode to DWC3 glue to which it is connected.
  47. dwc3@4a030000 {
  48. compatible = "snps,dwc3";
  49. reg = <0x4a030000 0xcfff>;
  50. interrupts = <0 92 4>
  51. usb-phy = <&usb2_phy>, <&usb3,phy>;
  52. tx-fifo-resize;
  53. };