ce4100.txt 1.2 KB

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  1. CE4100 Device Tree Bindings
  2. ---------------------------
  3. The CE4100 SoC uses for in core peripherals the following compatible
  4. format: <vendor>,<chip>-<device>.
  5. Many of the "generic" devices like HPET or IO APIC have the ce4100
  6. name in their compatible property because they first appeared in this
  7. SoC.
  8. The CPU node
  9. ------------
  10. cpu@0 {
  11. device_type = "cpu";
  12. compatible = "intel,ce4100";
  13. reg = <0>;
  14. lapic = <&lapic0>;
  15. };
  16. The reg property describes the CPU number. The lapic property points to
  17. the local APIC timer.
  18. The SoC node
  19. ------------
  20. This node describes the in-core peripherals. Required property:
  21. compatible = "intel,ce4100-cp";
  22. The PCI node
  23. ------------
  24. This node describes the PCI bus on the SoC. Its property should be
  25. compatible = "intel,ce4100-pci", "pci";
  26. If the OS is using the IO-APIC for interrupt routing then the reported
  27. interrupt numbers for devices is no longer true. In order to obtain the
  28. correct interrupt number, the child node which represents the device has
  29. to contain the interrupt property. Besides the interrupt property it has
  30. to contain at least the reg property containing the PCI bus address and
  31. compatible property according to "PCI Bus Binding Revision 2.1".