smc37c93x.c 6.2 KB

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  1. /*
  2. * SMC 37C93X initialization code
  3. */
  4. #include <linux/kernel.h>
  5. #include <linux/mm.h>
  6. #include <linux/init.h>
  7. #include <linux/delay.h>
  8. #include <asm/hwrpb.h>
  9. #include <asm/io.h>
  10. #include <asm/segment.h>
  11. #define SMC_DEBUG 0
  12. #if SMC_DEBUG
  13. # define DBG_DEVS(args) printk args
  14. #else
  15. # define DBG_DEVS(args)
  16. #endif
  17. #define KB 1024
  18. #define MB (1024*KB)
  19. #define GB (1024*MB)
  20. /* device "activate" register contents */
  21. #define DEVICE_ON 1
  22. #define DEVICE_OFF 0
  23. /* configuration on/off keys */
  24. #define CONFIG_ON_KEY 0x55
  25. #define CONFIG_OFF_KEY 0xaa
  26. /* configuration space device definitions */
  27. #define FDC 0
  28. #define IDE1 1
  29. #define IDE2 2
  30. #define PARP 3
  31. #define SER1 4
  32. #define SER2 5
  33. #define RTCL 6
  34. #define KYBD 7
  35. #define AUXIO 8
  36. /* Chip register offsets from base */
  37. #define CONFIG_CONTROL 0x02
  38. #define INDEX_ADDRESS 0x03
  39. #define LOGICAL_DEVICE_NUMBER 0x07
  40. #define DEVICE_ID 0x20
  41. #define DEVICE_REV 0x21
  42. #define POWER_CONTROL 0x22
  43. #define POWER_MGMT 0x23
  44. #define OSC 0x24
  45. #define ACTIVATE 0x30
  46. #define ADDR_HI 0x60
  47. #define ADDR_LO 0x61
  48. #define INTERRUPT_SEL 0x70
  49. #define INTERRUPT_SEL_2 0x72 /* KYBD/MOUS only */
  50. #define DMA_CHANNEL_SEL 0x74 /* FDC/PARP only */
  51. #define FDD_MODE_REGISTER 0x90
  52. #define FDD_OPTION_REGISTER 0x91
  53. /* values that we read back that are expected ... */
  54. #define VALID_DEVICE_ID 2
  55. /* default device addresses */
  56. #define KYBD_INTERRUPT 1
  57. #define MOUS_INTERRUPT 12
  58. #define COM2_BASE 0x2f8
  59. #define COM2_INTERRUPT 3
  60. #define COM1_BASE 0x3f8
  61. #define COM1_INTERRUPT 4
  62. #define PARP_BASE 0x3bc
  63. #define PARP_INTERRUPT 7
  64. static unsigned long __init SMCConfigState(unsigned long baseAddr)
  65. {
  66. unsigned char devId;
  67. unsigned long configPort;
  68. unsigned long indexPort;
  69. unsigned long dataPort;
  70. int i;
  71. configPort = indexPort = baseAddr;
  72. dataPort = configPort + 1;
  73. #define NUM_RETRIES 5
  74. for (i = 0; i < NUM_RETRIES; i++)
  75. {
  76. outb(CONFIG_ON_KEY, configPort);
  77. outb(CONFIG_ON_KEY, configPort);
  78. outb(DEVICE_ID, indexPort);
  79. devId = inb(dataPort);
  80. if (devId == VALID_DEVICE_ID) {
  81. outb(DEVICE_REV, indexPort);
  82. /* unsigned char devRev = */ inb(dataPort);
  83. break;
  84. }
  85. else
  86. udelay(100);
  87. }
  88. return (i != NUM_RETRIES) ? baseAddr : 0L;
  89. }
  90. static void __init SMCRunState(unsigned long baseAddr)
  91. {
  92. outb(CONFIG_OFF_KEY, baseAddr);
  93. }
  94. static unsigned long __init SMCDetectUltraIO(void)
  95. {
  96. unsigned long baseAddr;
  97. baseAddr = 0x3F0;
  98. if ( ( baseAddr = SMCConfigState( baseAddr ) ) == 0x3F0 ) {
  99. return( baseAddr );
  100. }
  101. baseAddr = 0x370;
  102. if ( ( baseAddr = SMCConfigState( baseAddr ) ) == 0x370 ) {
  103. return( baseAddr );
  104. }
  105. return( ( unsigned long )0 );
  106. }
  107. static void __init SMCEnableDevice(unsigned long baseAddr,
  108. unsigned long device,
  109. unsigned long portaddr,
  110. unsigned long interrupt)
  111. {
  112. unsigned long indexPort;
  113. unsigned long dataPort;
  114. indexPort = baseAddr;
  115. dataPort = baseAddr + 1;
  116. outb(LOGICAL_DEVICE_NUMBER, indexPort);
  117. outb(device, dataPort);
  118. outb(ADDR_LO, indexPort);
  119. outb(( portaddr & 0xFF ), dataPort);
  120. outb(ADDR_HI, indexPort);
  121. outb((portaddr >> 8) & 0xFF, dataPort);
  122. outb(INTERRUPT_SEL, indexPort);
  123. outb(interrupt, dataPort);
  124. outb(ACTIVATE, indexPort);
  125. outb(DEVICE_ON, dataPort);
  126. }
  127. static void __init SMCEnableKYBD(unsigned long baseAddr)
  128. {
  129. unsigned long indexPort;
  130. unsigned long dataPort;
  131. indexPort = baseAddr;
  132. dataPort = baseAddr + 1;
  133. outb(LOGICAL_DEVICE_NUMBER, indexPort);
  134. outb(KYBD, dataPort);
  135. outb(INTERRUPT_SEL, indexPort); /* Primary interrupt select */
  136. outb(KYBD_INTERRUPT, dataPort);
  137. outb(INTERRUPT_SEL_2, indexPort); /* Secondary interrupt select */
  138. outb(MOUS_INTERRUPT, dataPort);
  139. outb(ACTIVATE, indexPort);
  140. outb(DEVICE_ON, dataPort);
  141. }
  142. static void __init SMCEnableFDC(unsigned long baseAddr)
  143. {
  144. unsigned long indexPort;
  145. unsigned long dataPort;
  146. unsigned char oldValue;
  147. indexPort = baseAddr;
  148. dataPort = baseAddr + 1;
  149. outb(LOGICAL_DEVICE_NUMBER, indexPort);
  150. outb(FDC, dataPort);
  151. outb(FDD_MODE_REGISTER, indexPort);
  152. oldValue = inb(dataPort);
  153. oldValue |= 0x0E; /* Enable burst mode */
  154. outb(oldValue, dataPort);
  155. outb(INTERRUPT_SEL, indexPort); /* Primary interrupt select */
  156. outb(0x06, dataPort );
  157. outb(DMA_CHANNEL_SEL, indexPort); /* DMA channel select */
  158. outb(0x02, dataPort);
  159. outb(ACTIVATE, indexPort);
  160. outb(DEVICE_ON, dataPort);
  161. }
  162. #if SMC_DEBUG
  163. static void __init SMCReportDeviceStatus(unsigned long baseAddr)
  164. {
  165. unsigned long indexPort;
  166. unsigned long dataPort;
  167. unsigned char currentControl;
  168. indexPort = baseAddr;
  169. dataPort = baseAddr + 1;
  170. outb(POWER_CONTROL, indexPort);
  171. currentControl = inb(dataPort);
  172. printk(currentControl & (1 << FDC)
  173. ? "\t+FDC Enabled\n" : "\t-FDC Disabled\n");
  174. printk(currentControl & (1 << IDE1)
  175. ? "\t+IDE1 Enabled\n" : "\t-IDE1 Disabled\n");
  176. printk(currentControl & (1 << IDE2)
  177. ? "\t+IDE2 Enabled\n" : "\t-IDE2 Disabled\n");
  178. printk(currentControl & (1 << PARP)
  179. ? "\t+PARP Enabled\n" : "\t-PARP Disabled\n");
  180. printk(currentControl & (1 << SER1)
  181. ? "\t+SER1 Enabled\n" : "\t-SER1 Disabled\n");
  182. printk(currentControl & (1 << SER2)
  183. ? "\t+SER2 Enabled\n" : "\t-SER2 Disabled\n");
  184. printk( "\n" );
  185. }
  186. #endif
  187. int __init SMC93x_Init(void)
  188. {
  189. unsigned long SMCUltraBase;
  190. unsigned long flags;
  191. local_irq_save(flags);
  192. if ((SMCUltraBase = SMCDetectUltraIO()) != 0UL) {
  193. #if SMC_DEBUG
  194. SMCReportDeviceStatus(SMCUltraBase);
  195. #endif
  196. SMCEnableDevice(SMCUltraBase, SER1, COM1_BASE, COM1_INTERRUPT);
  197. DBG_DEVS(("SMC FDC37C93X: SER1 done\n"));
  198. SMCEnableDevice(SMCUltraBase, SER2, COM2_BASE, COM2_INTERRUPT);
  199. DBG_DEVS(("SMC FDC37C93X: SER2 done\n"));
  200. SMCEnableDevice(SMCUltraBase, PARP, PARP_BASE, PARP_INTERRUPT);
  201. DBG_DEVS(("SMC FDC37C93X: PARP done\n"));
  202. /* On PC164, IDE on the SMC is not enabled;
  203. CMD646 (PCI) on MB */
  204. SMCEnableKYBD(SMCUltraBase);
  205. DBG_DEVS(("SMC FDC37C93X: KYB done\n"));
  206. SMCEnableFDC(SMCUltraBase);
  207. DBG_DEVS(("SMC FDC37C93X: FDC done\n"));
  208. #if SMC_DEBUG
  209. SMCReportDeviceStatus(SMCUltraBase);
  210. #endif
  211. SMCRunState(SMCUltraBase);
  212. local_irq_restore(flags);
  213. printk("SMC FDC37C93X Ultra I/O Controller found @ 0x%lx\n",
  214. SMCUltraBase);
  215. return 1;
  216. }
  217. else {
  218. local_irq_restore(flags);
  219. DBG_DEVS(("No SMC FDC37C93X Ultra I/O Controller found\n"));
  220. return 0;
  221. }
  222. }