vdk_axs10x_mb.dtsi 2.2 KB

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  1. /*
  2. * Support for peripherals on the AXS10x mainboard (VDK version)
  3. *
  4. * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. / {
  11. axs10x_mb_vdk {
  12. compatible = "simple-bus";
  13. #address-cells = <1>;
  14. #size-cells = <1>;
  15. ranges = <0x00000000 0xe0000000 0x10000000>;
  16. interrupt-parent = <&mb_intc>;
  17. clocks {
  18. apbclk: apbclk {
  19. compatible = "fixed-clock";
  20. clock-frequency = <50000000>;
  21. #clock-cells = <0>;
  22. };
  23. };
  24. ethernet@0x18000 {
  25. #interrupt-cells = <1>;
  26. compatible = "snps,dwmac";
  27. reg = < 0x18000 0x2000 >;
  28. interrupts = < 4 >;
  29. interrupt-names = "macirq";
  30. phy-mode = "rgmii";
  31. snps,phy-addr = < 0 >; // VDK model phy address is 0
  32. snps,pbl = < 32 >;
  33. clocks = <&apbclk>;
  34. clock-names = "stmmaceth";
  35. };
  36. ehci@0x40000 {
  37. compatible = "generic-ehci";
  38. reg = < 0x40000 0x100 >;
  39. interrupts = < 8 >;
  40. };
  41. uart@0x20000 {
  42. compatible = "snps,dw-apb-uart";
  43. reg = <0x20000 0x100>;
  44. clock-frequency = <2403200>;
  45. interrupts = <17>;
  46. baud = <115200>;
  47. reg-shift = <2>;
  48. reg-io-width = <4>;
  49. };
  50. uart@0x21000 {
  51. compatible = "snps,dw-apb-uart";
  52. reg = <0x21000 0x100>;
  53. clock-frequency = <2403200>;
  54. interrupts = <18>;
  55. baud = <115200>;
  56. reg-shift = <2>;
  57. reg-io-width = <4>;
  58. };
  59. uart@0x22000 {
  60. compatible = "snps,dw-apb-uart";
  61. reg = <0x22000 0x100>;
  62. clock-frequency = <2403200>;
  63. interrupts = <19>;
  64. baud = <115200>;
  65. reg-shift = <2>;
  66. reg-io-width = <4>;
  67. };
  68. /* PGU output directly sent to virtual LCD screen; hdmi controller not modelled */
  69. pgu@0x17000 {
  70. compatible = "snps,arcpgufb";
  71. reg = <0x17000 0x400>;
  72. clock-frequency = <51000000>; /* PGU'clock is initated in init function */
  73. /* interrupts = <5>; PGU interrupts not used, this vector is used for ps2 below */
  74. };
  75. /* VDK has additional ps2 keyboard/mouse interface integrated in LCD screen model */
  76. ps2: ps2@e0017400 {
  77. compatible = "snps,arc_ps2";
  78. reg = <0x17400 0x14>;
  79. interrupts = <5>;
  80. interrupt-names = "arc_ps2_irq";
  81. };
  82. };
  83. };