apm-shadowcat.dtsi 6.6 KB

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  1. /*
  2. * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC
  3. *
  4. * Copyright (C) 2015, Applied Micro Circuits Corporation
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation; either version 2 of
  9. * the License, or (at your option) any later version.
  10. */
  11. / {
  12. compatible = "apm,xgene-shadowcat";
  13. interrupt-parent = <&gic>;
  14. #address-cells = <2>;
  15. #size-cells = <2>;
  16. cpus {
  17. #address-cells = <2>;
  18. #size-cells = <0>;
  19. cpu@000 {
  20. device_type = "cpu";
  21. compatible = "apm,strega", "arm,armv8";
  22. reg = <0x0 0x000>;
  23. enable-method = "spin-table";
  24. cpu-release-addr = <0x1 0x0000fff8>;
  25. };
  26. cpu@001 {
  27. device_type = "cpu";
  28. compatible = "apm,strega", "arm,armv8";
  29. reg = <0x0 0x001>;
  30. enable-method = "spin-table";
  31. cpu-release-addr = <0x1 0x0000fff8>;
  32. };
  33. cpu@100 {
  34. device_type = "cpu";
  35. compatible = "apm,strega", "arm,armv8";
  36. reg = <0x0 0x100>;
  37. enable-method = "spin-table";
  38. cpu-release-addr = <0x1 0x0000fff8>;
  39. };
  40. cpu@101 {
  41. device_type = "cpu";
  42. compatible = "apm,strega", "arm,armv8";
  43. reg = <0x0 0x101>;
  44. enable-method = "spin-table";
  45. cpu-release-addr = <0x1 0x0000fff8>;
  46. };
  47. cpu@200 {
  48. device_type = "cpu";
  49. compatible = "apm,strega", "arm,armv8";
  50. reg = <0x0 0x200>;
  51. enable-method = "spin-table";
  52. cpu-release-addr = <0x1 0x0000fff8>;
  53. };
  54. cpu@201 {
  55. device_type = "cpu";
  56. compatible = "apm,strega", "arm,armv8";
  57. reg = <0x0 0x201>;
  58. enable-method = "spin-table";
  59. cpu-release-addr = <0x1 0x0000fff8>;
  60. };
  61. cpu@300 {
  62. device_type = "cpu";
  63. compatible = "apm,strega", "arm,armv8";
  64. reg = <0x0 0x300>;
  65. enable-method = "spin-table";
  66. cpu-release-addr = <0x1 0x0000fff8>;
  67. };
  68. cpu@301 {
  69. device_type = "cpu";
  70. compatible = "apm,strega", "arm,armv8";
  71. reg = <0x0 0x301>;
  72. enable-method = "spin-table";
  73. cpu-release-addr = <0x1 0x0000fff8>;
  74. };
  75. };
  76. gic: interrupt-controller@78090000 {
  77. compatible = "arm,cortex-a15-gic";
  78. #interrupt-cells = <3>;
  79. #address-cells = <2>;
  80. #size-cells = <2>;
  81. interrupt-controller;
  82. interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
  83. ranges = <0 0 0 0x79000000 0x0 0x800000>; /* MSI Range */
  84. reg = <0x0 0x78090000 0x0 0x10000>, /* GIC Dist */
  85. <0x0 0x780A0000 0x0 0x20000>, /* GIC CPU */
  86. <0x0 0x780C0000 0x0 0x10000>, /* GIC VCPU Control */
  87. <0x0 0x780E0000 0x0 0x20000>; /* GIC VCPU */
  88. };
  89. pmu {
  90. compatible = "arm,armv8-pmuv3";
  91. interrupts = <1 12 0xff04>;
  92. };
  93. timer {
  94. compatible = "arm,armv8-timer";
  95. interrupts = <1 0 0xff04>, /* Secure Phys IRQ */
  96. <1 13 0xff04>, /* Non-secure Phys IRQ */
  97. <1 14 0xff04>, /* Virt IRQ */
  98. <1 15 0xff04>; /* Hyp IRQ */
  99. clock-frequency = <50000000>;
  100. };
  101. soc {
  102. compatible = "simple-bus";
  103. #address-cells = <2>;
  104. #size-cells = <2>;
  105. ranges;
  106. clocks {
  107. #address-cells = <2>;
  108. #size-cells = <2>;
  109. ranges;
  110. refclk: refclk {
  111. compatible = "fixed-clock";
  112. #clock-cells = <1>;
  113. clock-frequency = <100000000>;
  114. clock-output-names = "refclk";
  115. };
  116. socpll: socpll@17000120 {
  117. compatible = "apm,xgene-socpll-clock";
  118. #clock-cells = <1>;
  119. clocks = <&refclk 0>;
  120. reg = <0x0 0x17000120 0x0 0x1000>;
  121. clock-output-names = "socpll";
  122. };
  123. socplldiv2: socplldiv2 {
  124. compatible = "fixed-factor-clock";
  125. #clock-cells = <1>;
  126. clocks = <&socpll 0>;
  127. clock-mult = <1>;
  128. clock-div = <2>;
  129. clock-output-names = "socplldiv2";
  130. };
  131. pcie0clk: pcie0clk@1f2bc000 {
  132. compatible = "apm,xgene-device-clock";
  133. #clock-cells = <1>;
  134. clocks = <&socplldiv2 0>;
  135. reg = <0x0 0x1f2bc000 0x0 0x1000>;
  136. reg-names = "csr-reg";
  137. clock-output-names = "pcie0clk";
  138. };
  139. xge0clk: xge0clk@1f61c000 {
  140. compatible = "apm,xgene-device-clock";
  141. #clock-cells = <1>;
  142. clocks = <&socplldiv2 0>;
  143. reg = <0x0 0x1f61c000 0x0 0x1000>;
  144. reg-names = "csr-reg";
  145. enable-mask = <0x3>;
  146. csr-mask = <0x3>;
  147. clock-output-names = "xge0clk";
  148. };
  149. xge1clk: xge1clk@1f62c000 {
  150. compatible = "apm,xgene-device-clock";
  151. #clock-cells = <1>;
  152. clocks = <&socplldiv2 0>;
  153. reg = <0x0 0x1f62c000 0x0 0x1000>;
  154. reg-names = "csr-reg";
  155. enable-mask = <0x3>;
  156. csr-mask = <0x3>;
  157. clock-output-names = "xge1clk";
  158. };
  159. };
  160. scu: system-clk-controller@17000000 {
  161. compatible = "apm,xgene-scu","syscon";
  162. reg = <0x0 0x17000000 0x0 0x400>;
  163. };
  164. reboot: reboot@17000014 {
  165. compatible = "syscon-reboot";
  166. regmap = <&scu>;
  167. offset = <0x14>;
  168. mask = <0x1>;
  169. };
  170. serial0: serial@10600000 {
  171. device_type = "serial";
  172. compatible = "ns16550";
  173. reg = <0 0x10600000 0x0 0x1000>;
  174. reg-shift = <2>;
  175. clock-frequency = <10000000>;
  176. interrupt-parent = <&gic>;
  177. interrupts = <0x0 0x4c 0x4>;
  178. };
  179. sata1: sata@1a000000 {
  180. compatible = "apm,xgene-ahci";
  181. reg = <0x0 0x1a000000 0x0 0x1000>,
  182. <0x0 0x1f200000 0x0 0x1000>,
  183. <0x0 0x1f20d000 0x0 0x1000>,
  184. <0x0 0x1f20e000 0x0 0x1000>;
  185. interrupts = <0x0 0x5a 0x4>;
  186. dma-coherent;
  187. };
  188. sata2: sata@1a200000 {
  189. compatible = "apm,xgene-ahci";
  190. reg = <0x0 0x1a200000 0x0 0x1000>,
  191. <0x0 0x1f210000 0x0 0x1000>,
  192. <0x0 0x1f21d000 0x0 0x1000>,
  193. <0x0 0x1f21e000 0x0 0x1000>;
  194. interrupts = <0x0 0x5b 0x4>;
  195. dma-coherent;
  196. };
  197. sata3: sata@1a400000 {
  198. compatible = "apm,xgene-ahci";
  199. reg = <0x0 0x1a400000 0x0 0x1000>,
  200. <0x0 0x1f220000 0x0 0x1000>,
  201. <0x0 0x1f22d000 0x0 0x1000>,
  202. <0x0 0x1f22e000 0x0 0x1000>;
  203. interrupts = <0x0 0x5c 0x4>;
  204. dma-coherent;
  205. };
  206. sbgpio: sbgpio@17001000{
  207. compatible = "apm,xgene-gpio-sb";
  208. reg = <0x0 0x17001000 0x0 0x400>;
  209. #gpio-cells = <2>;
  210. gpio-controller;
  211. interrupts = <0x0 0x28 0x1>,
  212. <0x0 0x29 0x1>,
  213. <0x0 0x2a 0x1>,
  214. <0x0 0x2b 0x1>,
  215. <0x0 0x2c 0x1>,
  216. <0x0 0x2d 0x1>,
  217. <0x0 0x2e 0x1>,
  218. <0x0 0x2f 0x1>;
  219. };
  220. sgenet0: ethernet@1f610000 {
  221. compatible = "apm,xgene2-sgenet";
  222. status = "disabled";
  223. reg = <0x0 0x1f610000 0x0 0x10000>,
  224. <0x0 0x1f600000 0x0 0Xd100>,
  225. <0x0 0x20000000 0x0 0X20000>;
  226. interrupts = <0 96 4>,
  227. <0 97 4>;
  228. dma-coherent;
  229. clocks = <&xge0clk 0>;
  230. local-mac-address = [00 01 73 00 00 01];
  231. phy-connection-type = "sgmii";
  232. };
  233. xgenet1: ethernet@1f620000 {
  234. compatible = "apm,xgene2-xgenet";
  235. status = "disabled";
  236. reg = <0x0 0x1f620000 0x0 0x10000>,
  237. <0x0 0x1f600000 0x0 0Xd100>,
  238. <0x0 0x20000000 0x0 0X220000>;
  239. interrupts = <0 108 4>,
  240. <0 109 4>;
  241. port-id = <1>;
  242. dma-coherent;
  243. clocks = <&xge1clk 0>;
  244. local-mac-address = [00 01 73 00 00 02];
  245. phy-connection-type = "xgmii";
  246. };
  247. };
  248. };