vexpress-v2f-1xv7-ca53x2.dts 5.3 KB

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  1. /*
  2. * ARM Ltd. Versatile Express
  3. *
  4. * LogicTile Express 20MG
  5. * V2F-1XV7
  6. *
  7. * Cortex-A53 (2 cores) Soft Macrocell Model
  8. *
  9. * HBI-0247C
  10. */
  11. /dts-v1/;
  12. #include <dt-bindings/interrupt-controller/arm-gic.h>
  13. / {
  14. model = "V2F-1XV7 Cortex-A53x2 SMM";
  15. arm,hbi = <0x247>;
  16. arm,vexpress,site = <0xf>;
  17. compatible = "arm,vexpress,v2f-1xv7,ca53x2", "arm,vexpress,v2f-1xv7", "arm,vexpress";
  18. interrupt-parent = <&gic>;
  19. #address-cells = <2>;
  20. #size-cells = <2>;
  21. chosen {
  22. stdout-path = "serial0:38400n8";
  23. };
  24. aliases {
  25. serial0 = &v2m_serial0;
  26. serial1 = &v2m_serial1;
  27. serial2 = &v2m_serial2;
  28. serial3 = &v2m_serial3;
  29. i2c0 = &v2m_i2c_dvi;
  30. i2c1 = &v2m_i2c_pcie;
  31. };
  32. cpus {
  33. #address-cells = <2>;
  34. #size-cells = <0>;
  35. cpu@0 {
  36. device_type = "cpu";
  37. compatible = "arm,cortex-a53", "arm,armv8";
  38. reg = <0 0>;
  39. next-level-cache = <&L2_0>;
  40. };
  41. cpu@1 {
  42. device_type = "cpu";
  43. compatible = "arm,cortex-a53", "arm,armv8";
  44. reg = <0 1>;
  45. next-level-cache = <&L2_0>;
  46. };
  47. L2_0: l2-cache0 {
  48. compatible = "cache";
  49. };
  50. };
  51. memory@80000000 {
  52. device_type = "memory";
  53. reg = <0 0x80000000 0 0x80000000>; /* 2GB @ 2GB */
  54. };
  55. gic: interrupt-controller@2c001000 {
  56. compatible = "arm,gic-400";
  57. #interrupt-cells = <3>;
  58. #address-cells = <0>;
  59. interrupt-controller;
  60. reg = <0 0x2c001000 0 0x1000>,
  61. <0 0x2c002000 0 0x2000>,
  62. <0 0x2c004000 0 0x2000>,
  63. <0 0x2c006000 0 0x2000>;
  64. interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  65. };
  66. timer {
  67. compatible = "arm,armv8-timer";
  68. interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  69. <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  70. <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  71. <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  72. };
  73. pmu {
  74. compatible = "arm,armv8-pmuv3";
  75. interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
  76. <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
  77. };
  78. dcc {
  79. compatible = "arm,vexpress,config-bus";
  80. arm,vexpress,config-bridge = <&v2m_sysreg>;
  81. smbclk: osc@4 {
  82. /* SMC clock */
  83. compatible = "arm,vexpress-osc";
  84. arm,vexpress-sysreg,func = <1 4>;
  85. freq-range = <40000000 40000000>;
  86. #clock-cells = <0>;
  87. clock-output-names = "smclk";
  88. };
  89. volt@0 {
  90. /* VIO to expansion board above */
  91. compatible = "arm,vexpress-volt";
  92. arm,vexpress-sysreg,func = <2 0>;
  93. regulator-name = "VIO_UP";
  94. regulator-min-microvolt = <800000>;
  95. regulator-max-microvolt = <1800000>;
  96. regulator-always-on;
  97. };
  98. volt@1 {
  99. /* 12V from power connector J6 */
  100. compatible = "arm,vexpress-volt";
  101. arm,vexpress-sysreg,func = <2 1>;
  102. regulator-name = "12";
  103. regulator-always-on;
  104. };
  105. temp@0 {
  106. /* FPGA temperature */
  107. compatible = "arm,vexpress-temp";
  108. arm,vexpress-sysreg,func = <4 0>;
  109. label = "FPGA";
  110. };
  111. };
  112. smb {
  113. compatible = "simple-bus";
  114. #address-cells = <2>;
  115. #size-cells = <1>;
  116. ranges = <0 0 0 0x08000000 0x04000000>,
  117. <1 0 0 0x14000000 0x04000000>,
  118. <2 0 0 0x18000000 0x04000000>,
  119. <3 0 0 0x1c000000 0x04000000>,
  120. <4 0 0 0x0c000000 0x04000000>,
  121. <5 0 0 0x10000000 0x04000000>;
  122. #interrupt-cells = <1>;
  123. interrupt-map-mask = <0 0 63>;
  124. interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  125. <0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
  126. <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
  127. <0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
  128. <0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
  129. <0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
  130. <0 0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
  131. <0 0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
  132. <0 0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
  133. <0 0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
  134. <0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
  135. <0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
  136. <0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
  137. <0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
  138. <0 0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
  139. <0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
  140. <0 0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
  141. <0 0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
  142. <0 0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
  143. <0 0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
  144. <0 0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
  145. <0 0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
  146. <0 0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
  147. <0 0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
  148. <0 0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
  149. <0 0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
  150. <0 0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
  151. <0 0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
  152. <0 0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
  153. <0 0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
  154. <0 0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
  155. <0 0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
  156. <0 0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
  157. <0 0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
  158. <0 0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
  159. <0 0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
  160. <0 0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
  161. <0 0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
  162. <0 0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
  163. <0 0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
  164. <0 0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
  165. <0 0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
  166. <0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
  167. /include/ "vexpress-v2m-rs1.dtsi"
  168. };
  169. };