exynos7.dtsi 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537
  1. /*
  2. * SAMSUNG EXYNOS7 SoC device tree source
  3. *
  4. * Copyright (c) 2014 Samsung Electronics Co., Ltd.
  5. * http://www.samsung.com
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <dt-bindings/clock/exynos7-clk.h>
  12. / {
  13. compatible = "samsung,exynos7";
  14. interrupt-parent = <&gic>;
  15. #address-cells = <2>;
  16. #size-cells = <2>;
  17. aliases {
  18. pinctrl0 = &pinctrl_alive;
  19. pinctrl1 = &pinctrl_bus0;
  20. pinctrl2 = &pinctrl_nfc;
  21. pinctrl3 = &pinctrl_touch;
  22. pinctrl4 = &pinctrl_ff;
  23. pinctrl5 = &pinctrl_ese;
  24. pinctrl6 = &pinctrl_fsys0;
  25. pinctrl7 = &pinctrl_fsys1;
  26. pinctrl8 = &pinctrl_bus1;
  27. };
  28. cpus {
  29. #address-cells = <1>;
  30. #size-cells = <0>;
  31. cpu@0 {
  32. device_type = "cpu";
  33. compatible = "arm,cortex-a57", "arm,armv8";
  34. reg = <0x0>;
  35. enable-method = "psci";
  36. };
  37. cpu@1 {
  38. device_type = "cpu";
  39. compatible = "arm,cortex-a57", "arm,armv8";
  40. reg = <0x1>;
  41. enable-method = "psci";
  42. };
  43. cpu@2 {
  44. device_type = "cpu";
  45. compatible = "arm,cortex-a57", "arm,armv8";
  46. reg = <0x2>;
  47. enable-method = "psci";
  48. };
  49. cpu@3 {
  50. device_type = "cpu";
  51. compatible = "arm,cortex-a57", "arm,armv8";
  52. reg = <0x3>;
  53. enable-method = "psci";
  54. };
  55. };
  56. psci {
  57. compatible = "arm,psci-0.2";
  58. method = "smc";
  59. };
  60. soc: soc {
  61. compatible = "simple-bus";
  62. #address-cells = <1>;
  63. #size-cells = <1>;
  64. ranges = <0 0 0 0x18000000>;
  65. chipid@10000000 {
  66. compatible = "samsung,exynos4210-chipid";
  67. reg = <0x10000000 0x100>;
  68. };
  69. fin_pll: xxti {
  70. compatible = "fixed-clock";
  71. clock-output-names = "fin_pll";
  72. #clock-cells = <0>;
  73. };
  74. gic: interrupt-controller@11001000 {
  75. compatible = "arm,gic-400";
  76. #interrupt-cells = <3>;
  77. #address-cells = <0>;
  78. interrupt-controller;
  79. reg = <0x11001000 0x1000>,
  80. <0x11002000 0x1000>,
  81. <0x11004000 0x2000>,
  82. <0x11006000 0x2000>;
  83. };
  84. clock_topc: clock-controller@10570000 {
  85. compatible = "samsung,exynos7-clock-topc";
  86. reg = <0x10570000 0x10000>;
  87. #clock-cells = <1>;
  88. };
  89. clock_top0: clock-controller@105d0000 {
  90. compatible = "samsung,exynos7-clock-top0";
  91. reg = <0x105d0000 0xb000>;
  92. #clock-cells = <1>;
  93. clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
  94. <&clock_topc DOUT_SCLK_BUS1_PLL>,
  95. <&clock_topc DOUT_SCLK_CC_PLL>,
  96. <&clock_topc DOUT_SCLK_MFC_PLL>;
  97. clock-names = "fin_pll", "dout_sclk_bus0_pll",
  98. "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
  99. "dout_sclk_mfc_pll";
  100. };
  101. clock_top1: clock-controller@105e0000 {
  102. compatible = "samsung,exynos7-clock-top1";
  103. reg = <0x105e0000 0xb000>;
  104. #clock-cells = <1>;
  105. clocks = <&fin_pll>, <&clock_topc DOUT_SCLK_BUS0_PLL>,
  106. <&clock_topc DOUT_SCLK_BUS1_PLL>,
  107. <&clock_topc DOUT_SCLK_CC_PLL>,
  108. <&clock_topc DOUT_SCLK_MFC_PLL>;
  109. clock-names = "fin_pll", "dout_sclk_bus0_pll",
  110. "dout_sclk_bus1_pll", "dout_sclk_cc_pll",
  111. "dout_sclk_mfc_pll";
  112. };
  113. clock_ccore: clock-controller@105b0000 {
  114. compatible = "samsung,exynos7-clock-ccore";
  115. reg = <0x105b0000 0xd00>;
  116. #clock-cells = <1>;
  117. clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_CCORE_133>;
  118. clock-names = "fin_pll", "dout_aclk_ccore_133";
  119. };
  120. clock_peric0: clock-controller@13610000 {
  121. compatible = "samsung,exynos7-clock-peric0";
  122. reg = <0x13610000 0xd00>;
  123. #clock-cells = <1>;
  124. clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC0>,
  125. <&clock_top0 CLK_SCLK_UART0>;
  126. clock-names = "fin_pll", "dout_aclk_peric0_66",
  127. "sclk_uart0";
  128. };
  129. clock_peric1: clock-controller@14c80000 {
  130. compatible = "samsung,exynos7-clock-peric1";
  131. reg = <0x14c80000 0xd00>;
  132. #clock-cells = <1>;
  133. clocks = <&fin_pll>, <&clock_top0 DOUT_ACLK_PERIC1>,
  134. <&clock_top0 CLK_SCLK_UART1>,
  135. <&clock_top0 CLK_SCLK_UART2>,
  136. <&clock_top0 CLK_SCLK_UART3>;
  137. clock-names = "fin_pll", "dout_aclk_peric1_66",
  138. "sclk_uart1", "sclk_uart2", "sclk_uart3";
  139. };
  140. clock_peris: clock-controller@10040000 {
  141. compatible = "samsung,exynos7-clock-peris";
  142. reg = <0x10040000 0xd00>;
  143. #clock-cells = <1>;
  144. clocks = <&fin_pll>, <&clock_topc DOUT_ACLK_PERIS>;
  145. clock-names = "fin_pll", "dout_aclk_peris_66";
  146. };
  147. clock_fsys0: clock-controller@10e90000 {
  148. compatible = "samsung,exynos7-clock-fsys0";
  149. reg = <0x10e90000 0xd00>;
  150. #clock-cells = <1>;
  151. clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS0_200>,
  152. <&clock_top1 DOUT_SCLK_MMC2>;
  153. clock-names = "fin_pll", "dout_aclk_fsys0_200",
  154. "dout_sclk_mmc2";
  155. };
  156. clock_fsys1: clock-controller@156e0000 {
  157. compatible = "samsung,exynos7-clock-fsys1";
  158. reg = <0x156e0000 0xd00>;
  159. #clock-cells = <1>;
  160. clocks = <&fin_pll>, <&clock_top1 DOUT_ACLK_FSYS1_200>,
  161. <&clock_top1 DOUT_SCLK_MMC0>,
  162. <&clock_top1 DOUT_SCLK_MMC1>;
  163. clock-names = "fin_pll", "dout_aclk_fsys1_200",
  164. "dout_sclk_mmc0", "dout_sclk_mmc1";
  165. };
  166. serial_0: serial@13630000 {
  167. compatible = "samsung,exynos4210-uart";
  168. reg = <0x13630000 0x100>;
  169. interrupts = <0 440 0>;
  170. clocks = <&clock_peric0 PCLK_UART0>,
  171. <&clock_peric0 SCLK_UART0>;
  172. clock-names = "uart", "clk_uart_baud0";
  173. status = "disabled";
  174. };
  175. serial_1: serial@14c20000 {
  176. compatible = "samsung,exynos4210-uart";
  177. reg = <0x14c20000 0x100>;
  178. interrupts = <0 456 0>;
  179. clocks = <&clock_peric1 PCLK_UART1>,
  180. <&clock_peric1 SCLK_UART1>;
  181. clock-names = "uart", "clk_uart_baud0";
  182. status = "disabled";
  183. };
  184. serial_2: serial@14c30000 {
  185. compatible = "samsung,exynos4210-uart";
  186. reg = <0x14c30000 0x100>;
  187. interrupts = <0 457 0>;
  188. clocks = <&clock_peric1 PCLK_UART2>,
  189. <&clock_peric1 SCLK_UART2>;
  190. clock-names = "uart", "clk_uart_baud0";
  191. status = "disabled";
  192. };
  193. serial_3: serial@14c40000 {
  194. compatible = "samsung,exynos4210-uart";
  195. reg = <0x14c40000 0x100>;
  196. interrupts = <0 458 0>;
  197. clocks = <&clock_peric1 PCLK_UART3>,
  198. <&clock_peric1 SCLK_UART3>;
  199. clock-names = "uart", "clk_uart_baud0";
  200. status = "disabled";
  201. };
  202. pinctrl_alive: pinctrl@10580000 {
  203. compatible = "samsung,exynos7-pinctrl";
  204. reg = <0x10580000 0x1000>;
  205. wakeup-interrupt-controller {
  206. compatible = "samsung,exynos7-wakeup-eint";
  207. interrupt-parent = <&gic>;
  208. interrupts = <0 16 0>;
  209. };
  210. };
  211. pinctrl_bus0: pinctrl@13470000 {
  212. compatible = "samsung,exynos7-pinctrl";
  213. reg = <0x13470000 0x1000>;
  214. interrupts = <0 383 0>;
  215. };
  216. pinctrl_nfc: pinctrl@14cd0000 {
  217. compatible = "samsung,exynos7-pinctrl";
  218. reg = <0x14cd0000 0x1000>;
  219. interrupts = <0 473 0>;
  220. };
  221. pinctrl_touch: pinctrl@14ce0000 {
  222. compatible = "samsung,exynos7-pinctrl";
  223. reg = <0x14ce0000 0x1000>;
  224. interrupts = <0 474 0>;
  225. };
  226. pinctrl_ff: pinctrl@14c90000 {
  227. compatible = "samsung,exynos7-pinctrl";
  228. reg = <0x14c90000 0x1000>;
  229. interrupts = <0 475 0>;
  230. };
  231. pinctrl_ese: pinctrl@14ca0000 {
  232. compatible = "samsung,exynos7-pinctrl";
  233. reg = <0x14ca0000 0x1000>;
  234. interrupts = <0 476 0>;
  235. };
  236. pinctrl_fsys0: pinctrl@10e60000 {
  237. compatible = "samsung,exynos7-pinctrl";
  238. reg = <0x10e60000 0x1000>;
  239. interrupts = <0 221 0>;
  240. };
  241. pinctrl_fsys1: pinctrl@15690000 {
  242. compatible = "samsung,exynos7-pinctrl";
  243. reg = <0x15690000 0x1000>;
  244. interrupts = <0 203 0>;
  245. };
  246. pinctrl_bus1: pinctrl@14870000 {
  247. compatible = "samsung,exynos7-pinctrl";
  248. reg = <0x14870000 0x1000>;
  249. interrupts = <0 384 0>;
  250. };
  251. hsi2c_0: hsi2c@13640000 {
  252. compatible = "samsung,exynos7-hsi2c";
  253. reg = <0x13640000 0x1000>;
  254. interrupts = <0 441 0>;
  255. #address-cells = <1>;
  256. #size-cells = <0>;
  257. pinctrl-names = "default";
  258. pinctrl-0 = <&hs_i2c0_bus>;
  259. clocks = <&clock_peric0 PCLK_HSI2C0>;
  260. clock-names = "hsi2c";
  261. status = "disabled";
  262. };
  263. hsi2c_1: hsi2c@13650000 {
  264. compatible = "samsung,exynos7-hsi2c";
  265. reg = <0x13650000 0x1000>;
  266. interrupts = <0 442 0>;
  267. #address-cells = <1>;
  268. #size-cells = <0>;
  269. pinctrl-names = "default";
  270. pinctrl-0 = <&hs_i2c1_bus>;
  271. clocks = <&clock_peric0 PCLK_HSI2C1>;
  272. clock-names = "hsi2c";
  273. status = "disabled";
  274. };
  275. hsi2c_2: hsi2c@14e60000 {
  276. compatible = "samsung,exynos7-hsi2c";
  277. reg = <0x14e60000 0x1000>;
  278. interrupts = <0 459 0>;
  279. #address-cells = <1>;
  280. #size-cells = <0>;
  281. pinctrl-names = "default";
  282. pinctrl-0 = <&hs_i2c2_bus>;
  283. clocks = <&clock_peric1 PCLK_HSI2C2>;
  284. clock-names = "hsi2c";
  285. status = "disabled";
  286. };
  287. hsi2c_3: hsi2c@14e70000 {
  288. compatible = "samsung,exynos7-hsi2c";
  289. reg = <0x14e70000 0x1000>;
  290. interrupts = <0 460 0>;
  291. #address-cells = <1>;
  292. #size-cells = <0>;
  293. pinctrl-names = "default";
  294. pinctrl-0 = <&hs_i2c3_bus>;
  295. clocks = <&clock_peric1 PCLK_HSI2C3>;
  296. clock-names = "hsi2c";
  297. status = "disabled";
  298. };
  299. hsi2c_4: hsi2c@13660000 {
  300. compatible = "samsung,exynos7-hsi2c";
  301. reg = <0x13660000 0x1000>;
  302. interrupts = <0 443 0>;
  303. #address-cells = <1>;
  304. #size-cells = <0>;
  305. pinctrl-names = "default";
  306. pinctrl-0 = <&hs_i2c4_bus>;
  307. clocks = <&clock_peric0 PCLK_HSI2C4>;
  308. clock-names = "hsi2c";
  309. status = "disabled";
  310. };
  311. hsi2c_5: hsi2c@13670000 {
  312. compatible = "samsung,exynos7-hsi2c";
  313. reg = <0x13670000 0x1000>;
  314. interrupts = <0 444 0>;
  315. #address-cells = <1>;
  316. #size-cells = <0>;
  317. pinctrl-names = "default";
  318. pinctrl-0 = <&hs_i2c5_bus>;
  319. clocks = <&clock_peric0 PCLK_HSI2C5>;
  320. clock-names = "hsi2c";
  321. status = "disabled";
  322. };
  323. hsi2c_6: hsi2c@14e00000 {
  324. compatible = "samsung,exynos7-hsi2c";
  325. reg = <0x14e00000 0x1000>;
  326. interrupts = <0 461 0>;
  327. #address-cells = <1>;
  328. #size-cells = <0>;
  329. pinctrl-names = "default";
  330. pinctrl-0 = <&hs_i2c6_bus>;
  331. clocks = <&clock_peric1 PCLK_HSI2C6>;
  332. clock-names = "hsi2c";
  333. status = "disabled";
  334. };
  335. hsi2c_7: hsi2c@13e10000 {
  336. compatible = "samsung,exynos7-hsi2c";
  337. reg = <0x13e10000 0x1000>;
  338. interrupts = <0 462 0>;
  339. #address-cells = <1>;
  340. #size-cells = <0>;
  341. pinctrl-names = "default";
  342. pinctrl-0 = <&hs_i2c7_bus>;
  343. clocks = <&clock_peric1 PCLK_HSI2C7>;
  344. clock-names = "hsi2c";
  345. status = "disabled";
  346. };
  347. hsi2c_8: hsi2c@14e20000 {
  348. compatible = "samsung,exynos7-hsi2c";
  349. reg = <0x14e20000 0x1000>;
  350. interrupts = <0 463 0>;
  351. #address-cells = <1>;
  352. #size-cells = <0>;
  353. pinctrl-names = "default";
  354. pinctrl-0 = <&hs_i2c8_bus>;
  355. clocks = <&clock_peric1 PCLK_HSI2C8>;
  356. clock-names = "hsi2c";
  357. status = "disabled";
  358. };
  359. hsi2c_9: hsi2c@13680000 {
  360. compatible = "samsung,exynos7-hsi2c";
  361. reg = <0x13680000 0x1000>;
  362. interrupts = <0 445 0>;
  363. #address-cells = <1>;
  364. #size-cells = <0>;
  365. pinctrl-names = "default";
  366. pinctrl-0 = <&hs_i2c9_bus>;
  367. clocks = <&clock_peric0 PCLK_HSI2C9>;
  368. clock-names = "hsi2c";
  369. status = "disabled";
  370. };
  371. hsi2c_10: hsi2c@13690000 {
  372. compatible = "samsung,exynos7-hsi2c";
  373. reg = <0x13690000 0x1000>;
  374. interrupts = <0 446 0>;
  375. #address-cells = <1>;
  376. #size-cells = <0>;
  377. pinctrl-names = "default";
  378. pinctrl-0 = <&hs_i2c10_bus>;
  379. clocks = <&clock_peric0 PCLK_HSI2C10>;
  380. clock-names = "hsi2c";
  381. status = "disabled";
  382. };
  383. hsi2c_11: hsi2c@136a0000 {
  384. compatible = "samsung,exynos7-hsi2c";
  385. reg = <0x136a0000 0x1000>;
  386. interrupts = <0 447 0>;
  387. #address-cells = <1>;
  388. #size-cells = <0>;
  389. pinctrl-names = "default";
  390. pinctrl-0 = <&hs_i2c11_bus>;
  391. clocks = <&clock_peric0 PCLK_HSI2C11>;
  392. clock-names = "hsi2c";
  393. status = "disabled";
  394. };
  395. timer {
  396. compatible = "arm,armv8-timer";
  397. interrupts = <1 13 0xff01>,
  398. <1 14 0xff01>,
  399. <1 11 0xff01>,
  400. <1 10 0xff01>;
  401. };
  402. pmu_system_controller: system-controller@105c0000 {
  403. compatible = "samsung,exynos7-pmu", "syscon";
  404. reg = <0x105c0000 0x5000>;
  405. };
  406. rtc: rtc@10590000 {
  407. compatible = "samsung,s3c6410-rtc";
  408. reg = <0x10590000 0x100>;
  409. interrupts = <0 355 0>, <0 356 0>;
  410. clocks = <&clock_ccore PCLK_RTC>;
  411. clock-names = "rtc";
  412. status = "disabled";
  413. };
  414. watchdog: watchdog@101d0000 {
  415. compatible = "samsung,exynos7-wdt";
  416. reg = <0x101d0000 0x100>;
  417. interrupts = <0 110 0>;
  418. clocks = <&clock_peris PCLK_WDT>;
  419. clock-names = "watchdog";
  420. samsung,syscon-phandle = <&pmu_system_controller>;
  421. status = "disabled";
  422. };
  423. mmc_0: mmc@15740000 {
  424. compatible = "samsung,exynos7-dw-mshc-smu";
  425. interrupts = <0 201 0>;
  426. #address-cells = <1>;
  427. #size-cells = <0>;
  428. reg = <0x15740000 0x2000>;
  429. clocks = <&clock_fsys1 ACLK_MMC0>,
  430. <&clock_top1 CLK_SCLK_MMC0>;
  431. clock-names = "biu", "ciu";
  432. fifo-depth = <0x40>;
  433. status = "disabled";
  434. };
  435. mmc_1: mmc@15750000 {
  436. compatible = "samsung,exynos7-dw-mshc";
  437. interrupts = <0 202 0>;
  438. #address-cells = <1>;
  439. #size-cells = <0>;
  440. reg = <0x15750000 0x2000>;
  441. clocks = <&clock_fsys1 ACLK_MMC1>,
  442. <&clock_top1 CLK_SCLK_MMC1>;
  443. clock-names = "biu", "ciu";
  444. fifo-depth = <0x40>;
  445. status = "disabled";
  446. };
  447. mmc_2: mmc@15560000 {
  448. compatible = "samsung,exynos7-dw-mshc-smu";
  449. interrupts = <0 216 0>;
  450. #address-cells = <1>;
  451. #size-cells = <0>;
  452. reg = <0x15560000 0x2000>;
  453. clocks = <&clock_fsys0 ACLK_MMC2>,
  454. <&clock_top1 CLK_SCLK_MMC2>;
  455. clock-names = "biu", "ciu";
  456. fifo-depth = <0x40>;
  457. status = "disabled";
  458. };
  459. adc: adc@13620000 {
  460. compatible = "samsung,exynos7-adc";
  461. reg = <0x13620000 0x100>;
  462. interrupts = <0 448 0>;
  463. clocks = <&clock_peric0 PCLK_ADCIF>;
  464. clock-names = "adc";
  465. #io-channel-cells = <1>;
  466. io-channel-ranges;
  467. status = "disabled";
  468. };
  469. pwm: pwm@136c0000 {
  470. compatible = "samsung,exynos4210-pwm";
  471. reg = <0x136c0000 0x100>;
  472. samsung,pwm-outputs = <0>, <1>, <2>, <3>;
  473. #pwm-cells = <3>;
  474. clocks = <&clock_peric0 PCLK_PWM>;
  475. clock-names = "timers";
  476. };
  477. };
  478. };
  479. #include "exynos7-pinctrl.dtsi"