berlin4ct.dtsi 7.1 KB

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  1. /*
  2. * Copyright (C) 2015 Marvell Technology Group Ltd.
  3. *
  4. * Author: Jisheng Zhang <jszhang@marvell.com>
  5. *
  6. * This file is dual-licensed: you can use it either under the terms
  7. * of the GPLv2 or the X11 license, at your option. Note that this dual
  8. * licensing only applies to this file, and not this project as a
  9. * whole.
  10. *
  11. * a) This library is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of the
  14. * License, or (at your option) any later version.
  15. *
  16. * This library is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * Or, alternatively,
  22. *
  23. * b) Permission is hereby granted, free of charge, to any person
  24. * obtaining a copy of this software and associated documentation
  25. * files (the "Software"), to deal in the Software without
  26. * restriction, including without limitation the rights to use,
  27. * copy, modify, merge, publish, distribute, sublicense, and/or
  28. * sell copies of the Software, and to permit persons to whom the
  29. * Software is furnished to do so, subject to the following
  30. * conditions:
  31. *
  32. * The above copyright notice and this permission notice shall be
  33. * included in all copies or substantial portions of the Software.
  34. *
  35. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42. * OTHER DEALINGS IN THE SOFTWARE.
  43. */
  44. #include <dt-bindings/interrupt-controller/arm-gic.h>
  45. / {
  46. compatible = "marvell,berlin4ct", "marvell,berlin";
  47. interrupt-parent = <&gic>;
  48. #address-cells = <2>;
  49. #size-cells = <2>;
  50. aliases {
  51. serial0 = &uart0;
  52. };
  53. psci {
  54. compatible = "arm,psci-0.2";
  55. method = "smc";
  56. };
  57. cpus {
  58. #address-cells = <1>;
  59. #size-cells = <0>;
  60. cpu0: cpu@0 {
  61. compatible = "arm,cortex-a53", "arm,armv8";
  62. device_type = "cpu";
  63. reg = <0x0>;
  64. enable-method = "psci";
  65. };
  66. cpu1: cpu@1 {
  67. compatible = "arm,cortex-a53", "arm,armv8";
  68. device_type = "cpu";
  69. reg = <0x1>;
  70. enable-method = "psci";
  71. };
  72. cpu2: cpu@2 {
  73. compatible = "arm,cortex-a53", "arm,armv8";
  74. device_type = "cpu";
  75. reg = <0x2>;
  76. enable-method = "psci";
  77. };
  78. cpu3: cpu@3 {
  79. compatible = "arm,cortex-a53", "arm,armv8";
  80. device_type = "cpu";
  81. reg = <0x3>;
  82. enable-method = "psci";
  83. };
  84. };
  85. osc: osc {
  86. compatible = "fixed-clock";
  87. #clock-cells = <0>;
  88. clock-frequency = <25000000>;
  89. };
  90. pmu {
  91. compatible = "arm,armv8-pmuv3";
  92. interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
  93. <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
  94. <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
  95. <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
  96. interrupt-affinity = <&cpu0>,
  97. <&cpu1>,
  98. <&cpu2>,
  99. <&cpu3>;
  100. };
  101. timer {
  102. compatible = "arm,armv8-timer";
  103. interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  104. <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  105. <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  106. <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  107. };
  108. soc {
  109. compatible = "simple-bus";
  110. #address-cells = <1>;
  111. #size-cells = <1>;
  112. ranges = <0 0 0xf7000000 0x1000000>;
  113. gic: interrupt-controller@901000 {
  114. compatible = "arm,gic-400";
  115. #interrupt-cells = <3>;
  116. interrupt-controller;
  117. reg = <0x901000 0x1000>,
  118. <0x902000 0x2000>,
  119. <0x904000 0x2000>,
  120. <0x906000 0x2000>;
  121. interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  122. };
  123. apb@e80000 {
  124. compatible = "simple-bus";
  125. #address-cells = <1>;
  126. #size-cells = <1>;
  127. ranges = <0 0xe80000 0x10000>;
  128. interrupt-parent = <&aic>;
  129. gpio0: gpio@0400 {
  130. compatible = "snps,dw-apb-gpio";
  131. reg = <0x0400 0x400>;
  132. #address-cells = <1>;
  133. #size-cells = <0>;
  134. porta: gpio-port@0 {
  135. compatible = "snps,dw-apb-gpio-port";
  136. gpio-controller;
  137. #gpio-cells = <2>;
  138. snps,nr-gpios = <32>;
  139. reg = <0>;
  140. interrupt-controller;
  141. #interrupt-cells = <2>;
  142. interrupts = <0>;
  143. };
  144. };
  145. gpio1: gpio@0800 {
  146. compatible = "snps,dw-apb-gpio";
  147. reg = <0x0800 0x400>;
  148. #address-cells = <1>;
  149. #size-cells = <0>;
  150. portb: gpio-port@1 {
  151. compatible = "snps,dw-apb-gpio-port";
  152. gpio-controller;
  153. #gpio-cells = <2>;
  154. snps,nr-gpios = <32>;
  155. reg = <0>;
  156. interrupt-controller;
  157. #interrupt-cells = <2>;
  158. interrupts = <1>;
  159. };
  160. };
  161. gpio2: gpio@0c00 {
  162. compatible = "snps,dw-apb-gpio";
  163. reg = <0x0c00 0x400>;
  164. #address-cells = <1>;
  165. #size-cells = <0>;
  166. portc: gpio-port@2 {
  167. compatible = "snps,dw-apb-gpio-port";
  168. gpio-controller;
  169. #gpio-cells = <2>;
  170. snps,nr-gpios = <32>;
  171. reg = <0>;
  172. interrupt-controller;
  173. #interrupt-cells = <2>;
  174. interrupts = <2>;
  175. };
  176. };
  177. gpio3: gpio@1000 {
  178. compatible = "snps,dw-apb-gpio";
  179. reg = <0x1000 0x400>;
  180. #address-cells = <1>;
  181. #size-cells = <0>;
  182. portd: gpio-port@3 {
  183. compatible = "snps,dw-apb-gpio-port";
  184. gpio-controller;
  185. #gpio-cells = <2>;
  186. snps,nr-gpios = <32>;
  187. reg = <0>;
  188. interrupt-controller;
  189. #interrupt-cells = <2>;
  190. interrupts = <3>;
  191. };
  192. };
  193. aic: interrupt-controller@3800 {
  194. compatible = "snps,dw-apb-ictl";
  195. reg = <0x3800 0x30>;
  196. interrupt-controller;
  197. #interrupt-cells = <1>;
  198. interrupt-parent = <&gic>;
  199. interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
  200. };
  201. };
  202. apb@fc0000 {
  203. compatible = "simple-bus";
  204. #address-cells = <1>;
  205. #size-cells = <1>;
  206. ranges = <0 0xfc0000 0x10000>;
  207. interrupt-parent = <&sic>;
  208. sic: interrupt-controller@1000 {
  209. compatible = "snps,dw-apb-ictl";
  210. reg = <0x1000 0x30>;
  211. interrupt-controller;
  212. #interrupt-cells = <1>;
  213. interrupt-parent = <&gic>;
  214. interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  215. };
  216. sm_gpio0: gpio@8000 {
  217. compatible = "snps,dw-apb-gpio";
  218. reg = <0x8000 0x400>;
  219. #address-cells = <1>;
  220. #size-cells = <0>;
  221. porte: gpio-port@4 {
  222. compatible = "snps,dw-apb-gpio-port";
  223. gpio-controller;
  224. #gpio-cells = <2>;
  225. snps,nr-gpios = <32>;
  226. reg = <0>;
  227. };
  228. };
  229. sm_gpio1: gpio@9000 {
  230. compatible = "snps,dw-apb-gpio";
  231. reg = <0x9000 0x400>;
  232. #address-cells = <1>;
  233. #size-cells = <0>;
  234. portf: gpio-port@5 {
  235. compatible = "snps,dw-apb-gpio-port";
  236. gpio-controller;
  237. #gpio-cells = <2>;
  238. snps,nr-gpios = <32>;
  239. reg = <0>;
  240. };
  241. };
  242. uart0: uart@d000 {
  243. compatible = "snps,dw-apb-uart";
  244. reg = <0xd000 0x100>;
  245. interrupts = <8>;
  246. clocks = <&osc>;
  247. reg-shift = <2>;
  248. status = "disabled";
  249. };
  250. };
  251. };
  252. };