rk3368.dtsi 23 KB

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  1. /*
  2. * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
  3. *
  4. * This file is dual-licensed: you can use it either under the terms
  5. * of the GPL or the X11 license, at your option. Note that this dual
  6. * licensing only applies to this file, and not this project as a
  7. * whole.
  8. *
  9. * a) This library is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of the
  12. * License, or (at your option) any later version.
  13. *
  14. * This library is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * Or, alternatively,
  20. *
  21. * b) Permission is hereby granted, free of charge, to any person
  22. * obtaining a copy of this software and associated documentation
  23. * files (the "Software"), to deal in the Software without
  24. * restriction, including without limitation the rights to use,
  25. * copy, modify, merge, publish, distribute, sublicense, and/or
  26. * sell copies of the Software, and to permit persons to whom the
  27. * Software is furnished to do so, subject to the following
  28. * conditions:
  29. *
  30. * The above copyright notice and this permission notice shall be
  31. * included in all copies or substantial portions of the Software.
  32. *
  33. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35. * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37. * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38. * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40. * OTHER DEALINGS IN THE SOFTWARE.
  41. */
  42. #include <dt-bindings/clock/rk3368-cru.h>
  43. #include <dt-bindings/gpio/gpio.h>
  44. #include <dt-bindings/interrupt-controller/irq.h>
  45. #include <dt-bindings/interrupt-controller/arm-gic.h>
  46. #include <dt-bindings/pinctrl/rockchip.h>
  47. / {
  48. compatible = "rockchip,rk3368";
  49. interrupt-parent = <&gic>;
  50. #address-cells = <2>;
  51. #size-cells = <2>;
  52. aliases {
  53. i2c0 = &i2c0;
  54. i2c1 = &i2c1;
  55. i2c2 = &i2c2;
  56. i2c3 = &i2c3;
  57. i2c4 = &i2c4;
  58. i2c5 = &i2c5;
  59. serial0 = &uart0;
  60. serial1 = &uart1;
  61. serial2 = &uart2;
  62. serial3 = &uart3;
  63. serial4 = &uart4;
  64. spi0 = &spi0;
  65. spi1 = &spi1;
  66. spi2 = &spi2;
  67. };
  68. cpus {
  69. #address-cells = <0x2>;
  70. #size-cells = <0x0>;
  71. cpu-map {
  72. cluster0 {
  73. core0 {
  74. cpu = <&cpu_b0>;
  75. };
  76. core1 {
  77. cpu = <&cpu_b1>;
  78. };
  79. core2 {
  80. cpu = <&cpu_b2>;
  81. };
  82. core3 {
  83. cpu = <&cpu_b3>;
  84. };
  85. };
  86. cluster1 {
  87. core0 {
  88. cpu = <&cpu_l0>;
  89. };
  90. core1 {
  91. cpu = <&cpu_l1>;
  92. };
  93. core2 {
  94. cpu = <&cpu_l2>;
  95. };
  96. core3 {
  97. cpu = <&cpu_l3>;
  98. };
  99. };
  100. };
  101. idle-states {
  102. entry-method = "psci";
  103. cpu_sleep: cpu-sleep-0 {
  104. compatible = "arm,idle-state";
  105. arm,psci-suspend-param = <0x1010000>;
  106. entry-latency-us = <0x3fffffff>;
  107. exit-latency-us = <0x40000000>;
  108. min-residency-us = <0xffffffff>;
  109. };
  110. };
  111. cpu_l0: cpu@0 {
  112. device_type = "cpu";
  113. compatible = "arm,cortex-a53", "arm,armv8";
  114. reg = <0x0 0x0>;
  115. cpu-idle-states = <&cpu_sleep>;
  116. enable-method = "psci";
  117. };
  118. cpu_l1: cpu@1 {
  119. device_type = "cpu";
  120. compatible = "arm,cortex-a53", "arm,armv8";
  121. reg = <0x0 0x1>;
  122. cpu-idle-states = <&cpu_sleep>;
  123. enable-method = "psci";
  124. };
  125. cpu_l2: cpu@2 {
  126. device_type = "cpu";
  127. compatible = "arm,cortex-a53", "arm,armv8";
  128. reg = <0x0 0x2>;
  129. cpu-idle-states = <&cpu_sleep>;
  130. enable-method = "psci";
  131. };
  132. cpu_l3: cpu@3 {
  133. device_type = "cpu";
  134. compatible = "arm,cortex-a53", "arm,armv8";
  135. reg = <0x0 0x3>;
  136. cpu-idle-states = <&cpu_sleep>;
  137. enable-method = "psci";
  138. };
  139. cpu_b0: cpu@100 {
  140. device_type = "cpu";
  141. compatible = "arm,cortex-a53", "arm,armv8";
  142. reg = <0x0 0x100>;
  143. cpu-idle-states = <&cpu_sleep>;
  144. enable-method = "psci";
  145. };
  146. cpu_b1: cpu@101 {
  147. device_type = "cpu";
  148. compatible = "arm,cortex-a53", "arm,armv8";
  149. reg = <0x0 0x101>;
  150. cpu-idle-states = <&cpu_sleep>;
  151. enable-method = "psci";
  152. };
  153. cpu_b2: cpu@102 {
  154. device_type = "cpu";
  155. compatible = "arm,cortex-a53", "arm,armv8";
  156. reg = <0x0 0x102>;
  157. cpu-idle-states = <&cpu_sleep>;
  158. enable-method = "psci";
  159. };
  160. cpu_b3: cpu@103 {
  161. device_type = "cpu";
  162. compatible = "arm,cortex-a53", "arm,armv8";
  163. reg = <0x0 0x103>;
  164. cpu-idle-states = <&cpu_sleep>;
  165. enable-method = "psci";
  166. };
  167. };
  168. arm-pmu {
  169. compatible = "arm,armv8-pmuv3";
  170. interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
  171. <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
  172. <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
  173. <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
  174. <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
  175. <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
  176. <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
  177. <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
  178. interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
  179. <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
  180. <&cpu_b2>, <&cpu_b3>;
  181. };
  182. psci {
  183. compatible = "arm,psci-0.2";
  184. method = "smc";
  185. };
  186. timer {
  187. compatible = "arm,armv8-timer";
  188. interrupts = <GIC_PPI 13
  189. (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
  190. <GIC_PPI 14
  191. (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
  192. <GIC_PPI 11
  193. (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
  194. <GIC_PPI 10
  195. (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
  196. };
  197. xin24m: oscillator {
  198. compatible = "fixed-clock";
  199. clock-frequency = <24000000>;
  200. clock-output-names = "xin24m";
  201. #clock-cells = <0>;
  202. };
  203. sdmmc: dwmmc@ff0c0000 {
  204. compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
  205. reg = <0x0 0xff0c0000 0x0 0x4000>;
  206. clock-freq-min-max = <400000 150000000>;
  207. clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
  208. clock-names = "biu", "ciu";
  209. fifo-depth = <0x100>;
  210. interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  211. status = "disabled";
  212. };
  213. sdio0: dwmmc@ff0d0000 {
  214. compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
  215. reg = <0x0 0xff0d0000 0x0 0x4000>;
  216. clock-freq-min-max = <400000 150000000>;
  217. clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
  218. <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
  219. clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
  220. fifo-depth = <0x100>;
  221. interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
  222. status = "disabled";
  223. };
  224. emmc: dwmmc@ff0f0000 {
  225. compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
  226. reg = <0x0 0xff0f0000 0x0 0x4000>;
  227. clock-freq-min-max = <400000 150000000>;
  228. clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
  229. clock-names = "biu", "ciu";
  230. fifo-depth = <0x100>;
  231. interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  232. status = "disabled";
  233. };
  234. saradc: saradc@ff100000 {
  235. compatible = "rockchip,saradc";
  236. reg = <0x0 0xff100000 0x0 0x100>;
  237. interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
  238. #io-channel-cells = <1>;
  239. clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
  240. clock-names = "saradc", "apb_pclk";
  241. resets = <&cru SRST_SARADC>;
  242. reset-names = "saradc-apb";
  243. status = "disabled";
  244. };
  245. spi0: spi@ff110000 {
  246. compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
  247. reg = <0x0 0xff110000 0x0 0x1000>;
  248. clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
  249. clock-names = "spiclk", "apb_pclk";
  250. interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
  251. pinctrl-names = "default";
  252. pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
  253. #address-cells = <1>;
  254. #size-cells = <0>;
  255. status = "disabled";
  256. };
  257. spi1: spi@ff120000 {
  258. compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
  259. reg = <0x0 0xff120000 0x0 0x1000>;
  260. clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
  261. clock-names = "spiclk", "apb_pclk";
  262. interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
  263. pinctrl-names = "default";
  264. pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
  265. #address-cells = <1>;
  266. #size-cells = <0>;
  267. status = "disabled";
  268. };
  269. spi2: spi@ff130000 {
  270. compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
  271. reg = <0x0 0xff130000 0x0 0x1000>;
  272. clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
  273. clock-names = "spiclk", "apb_pclk";
  274. interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
  275. pinctrl-names = "default";
  276. pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
  277. #address-cells = <1>;
  278. #size-cells = <0>;
  279. status = "disabled";
  280. };
  281. i2c1: i2c@ff140000 {
  282. compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
  283. reg = <0x0 0xff140000 0x0 0x1000>;
  284. interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
  285. #address-cells = <1>;
  286. #size-cells = <0>;
  287. clock-names = "i2c";
  288. clocks = <&cru PCLK_I2C1>;
  289. pinctrl-names = "default";
  290. pinctrl-0 = <&i2c1_xfer>;
  291. status = "disabled";
  292. };
  293. i2c3: i2c@ff150000 {
  294. compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
  295. reg = <0x0 0xff150000 0x0 0x1000>;
  296. interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
  297. #address-cells = <1>;
  298. #size-cells = <0>;
  299. clock-names = "i2c";
  300. clocks = <&cru PCLK_I2C3>;
  301. pinctrl-names = "default";
  302. pinctrl-0 = <&i2c3_xfer>;
  303. status = "disabled";
  304. };
  305. i2c4: i2c@ff160000 {
  306. compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
  307. reg = <0x0 0xff160000 0x0 0x1000>;
  308. interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
  309. #address-cells = <1>;
  310. #size-cells = <0>;
  311. clock-names = "i2c";
  312. clocks = <&cru PCLK_I2C4>;
  313. pinctrl-names = "default";
  314. pinctrl-0 = <&i2c4_xfer>;
  315. status = "disabled";
  316. };
  317. i2c5: i2c@ff170000 {
  318. compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
  319. reg = <0x0 0xff170000 0x0 0x1000>;
  320. interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
  321. #address-cells = <1>;
  322. #size-cells = <0>;
  323. clock-names = "i2c";
  324. clocks = <&cru PCLK_I2C5>;
  325. pinctrl-names = "default";
  326. pinctrl-0 = <&i2c5_xfer>;
  327. status = "disabled";
  328. };
  329. uart0: serial@ff180000 {
  330. compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
  331. reg = <0x0 0xff180000 0x0 0x100>;
  332. clock-frequency = <24000000>;
  333. clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
  334. clock-names = "baudclk", "apb_pclk";
  335. interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
  336. reg-shift = <2>;
  337. reg-io-width = <4>;
  338. status = "disabled";
  339. };
  340. uart1: serial@ff190000 {
  341. compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
  342. reg = <0x0 0xff190000 0x0 0x100>;
  343. clock-frequency = <24000000>;
  344. clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
  345. clock-names = "baudclk", "apb_pclk";
  346. interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
  347. reg-shift = <2>;
  348. reg-io-width = <4>;
  349. status = "disabled";
  350. };
  351. uart3: serial@ff1b0000 {
  352. compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
  353. reg = <0x0 0xff1b0000 0x0 0x100>;
  354. clock-frequency = <24000000>;
  355. clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
  356. clock-names = "baudclk", "apb_pclk";
  357. interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
  358. reg-shift = <2>;
  359. reg-io-width = <4>;
  360. status = "disabled";
  361. };
  362. uart4: serial@ff1c0000 {
  363. compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
  364. reg = <0x0 0xff1c0000 0x0 0x100>;
  365. clock-frequency = <24000000>;
  366. clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
  367. clock-names = "baudclk", "apb_pclk";
  368. interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
  369. reg-shift = <2>;
  370. reg-io-width = <4>;
  371. status = "disabled";
  372. };
  373. gmac: ethernet@ff290000 {
  374. compatible = "rockchip,rk3368-gmac";
  375. reg = <0x0 0xff290000 0x0 0x10000>;
  376. interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
  377. interrupt-names = "macirq";
  378. rockchip,grf = <&grf>;
  379. clocks = <&cru SCLK_MAC>,
  380. <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
  381. <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
  382. <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
  383. clock-names = "stmmaceth",
  384. "mac_clk_rx", "mac_clk_tx",
  385. "clk_mac_ref", "clk_mac_refout",
  386. "aclk_mac", "pclk_mac";
  387. status = "disabled";
  388. };
  389. usb_host0_ehci: usb@ff500000 {
  390. compatible = "generic-ehci";
  391. reg = <0x0 0xff500000 0x0 0x100>;
  392. interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
  393. clocks = <&cru HCLK_HOST0>;
  394. clock-names = "usbhost";
  395. status = "disabled";
  396. };
  397. usb_otg: usb@ff580000 {
  398. compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
  399. "snps,dwc2";
  400. reg = <0x0 0xff580000 0x0 0x40000>;
  401. interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
  402. clocks = <&cru HCLK_OTG0>;
  403. clock-names = "otg";
  404. dr_mode = "otg";
  405. g-np-tx-fifo-size = <16>;
  406. g-rx-fifo-size = <275>;
  407. g-tx-fifo-size = <256 128 128 64 64 32>;
  408. g-use-dma;
  409. status = "disabled";
  410. };
  411. i2c0: i2c@ff650000 {
  412. compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
  413. reg = <0x0 0xff650000 0x0 0x1000>;
  414. clocks = <&cru PCLK_I2C0>;
  415. clock-names = "i2c";
  416. interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
  417. pinctrl-names = "default";
  418. pinctrl-0 = <&i2c0_xfer>;
  419. #address-cells = <1>;
  420. #size-cells = <0>;
  421. status = "disabled";
  422. };
  423. i2c2: i2c@ff660000 {
  424. compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
  425. reg = <0x0 0xff660000 0x0 0x1000>;
  426. interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
  427. #address-cells = <1>;
  428. #size-cells = <0>;
  429. clock-names = "i2c";
  430. clocks = <&cru PCLK_I2C2>;
  431. pinctrl-names = "default";
  432. pinctrl-0 = <&i2c2_xfer>;
  433. status = "disabled";
  434. };
  435. uart2: serial@ff690000 {
  436. compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
  437. reg = <0x0 0xff690000 0x0 0x100>;
  438. clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
  439. clock-names = "baudclk", "apb_pclk";
  440. interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
  441. pinctrl-names = "default";
  442. pinctrl-0 = <&uart2_xfer>;
  443. reg-shift = <2>;
  444. reg-io-width = <4>;
  445. status = "disabled";
  446. };
  447. pmugrf: syscon@ff738000 {
  448. compatible = "rockchip,rk3368-pmugrf", "syscon";
  449. reg = <0x0 0xff738000 0x0 0x1000>;
  450. };
  451. cru: clock-controller@ff760000 {
  452. compatible = "rockchip,rk3368-cru";
  453. reg = <0x0 0xff760000 0x0 0x1000>;
  454. rockchip,grf = <&grf>;
  455. #clock-cells = <1>;
  456. #reset-cells = <1>;
  457. };
  458. grf: syscon@ff770000 {
  459. compatible = "rockchip,rk3368-grf", "syscon";
  460. reg = <0x0 0xff770000 0x0 0x1000>;
  461. };
  462. wdt: watchdog@ff800000 {
  463. compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
  464. reg = <0x0 0xff800000 0x0 0x100>;
  465. clocks = <&cru PCLK_WDT>;
  466. interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
  467. status = "disabled";
  468. };
  469. gic: interrupt-controller@ffb71000 {
  470. compatible = "arm,gic-400";
  471. interrupt-controller;
  472. #interrupt-cells = <3>;
  473. #address-cells = <0>;
  474. reg = <0x0 0xffb71000 0x0 0x1000>,
  475. <0x0 0xffb72000 0x0 0x2000>,
  476. <0x0 0xffb74000 0x0 0x2000>,
  477. <0x0 0xffb76000 0x0 0x2000>;
  478. interrupts = <GIC_PPI 9
  479. (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
  480. };
  481. pinctrl: pinctrl {
  482. compatible = "rockchip,rk3368-pinctrl";
  483. rockchip,grf = <&grf>;
  484. rockchip,pmu = <&pmugrf>;
  485. #address-cells = <0x2>;
  486. #size-cells = <0x2>;
  487. ranges;
  488. gpio0: gpio0@ff750000 {
  489. compatible = "rockchip,gpio-bank";
  490. reg = <0x0 0xff750000 0x0 0x100>;
  491. clocks = <&cru PCLK_GPIO0>;
  492. interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
  493. gpio-controller;
  494. #gpio-cells = <0x2>;
  495. interrupt-controller;
  496. #interrupt-cells = <0x2>;
  497. };
  498. gpio1: gpio1@ff780000 {
  499. compatible = "rockchip,gpio-bank";
  500. reg = <0x0 0xff780000 0x0 0x100>;
  501. clocks = <&cru PCLK_GPIO1>;
  502. interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
  503. gpio-controller;
  504. #gpio-cells = <0x2>;
  505. interrupt-controller;
  506. #interrupt-cells = <0x2>;
  507. };
  508. gpio2: gpio2@ff790000 {
  509. compatible = "rockchip,gpio-bank";
  510. reg = <0x0 0xff790000 0x0 0x100>;
  511. clocks = <&cru PCLK_GPIO2>;
  512. interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
  513. gpio-controller;
  514. #gpio-cells = <0x2>;
  515. interrupt-controller;
  516. #interrupt-cells = <0x2>;
  517. };
  518. gpio3: gpio3@ff7a0000 {
  519. compatible = "rockchip,gpio-bank";
  520. reg = <0x0 0xff7a0000 0x0 0x100>;
  521. clocks = <&cru PCLK_GPIO3>;
  522. interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
  523. gpio-controller;
  524. #gpio-cells = <0x2>;
  525. interrupt-controller;
  526. #interrupt-cells = <0x2>;
  527. };
  528. pcfg_pull_up: pcfg-pull-up {
  529. bias-pull-up;
  530. };
  531. pcfg_pull_down: pcfg-pull-down {
  532. bias-pull-down;
  533. };
  534. pcfg_pull_none: pcfg-pull-none {
  535. bias-disable;
  536. };
  537. pcfg_pull_none_12ma: pcfg-pull-none-12ma {
  538. bias-disable;
  539. drive-strength = <12>;
  540. };
  541. emmc {
  542. emmc_clk: emmc-clk {
  543. rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
  544. };
  545. emmc_cmd: emmc-cmd {
  546. rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
  547. };
  548. emmc_pwr: emmc-pwr {
  549. rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
  550. };
  551. emmc_bus1: emmc-bus1 {
  552. rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
  553. };
  554. emmc_bus4: emmc-bus4 {
  555. rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
  556. <1 19 RK_FUNC_2 &pcfg_pull_up>,
  557. <1 20 RK_FUNC_2 &pcfg_pull_up>,
  558. <1 21 RK_FUNC_2 &pcfg_pull_up>;
  559. };
  560. emmc_bus8: emmc-bus8 {
  561. rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
  562. <1 19 RK_FUNC_2 &pcfg_pull_up>,
  563. <1 20 RK_FUNC_2 &pcfg_pull_up>,
  564. <1 21 RK_FUNC_2 &pcfg_pull_up>,
  565. <1 22 RK_FUNC_2 &pcfg_pull_up>,
  566. <1 23 RK_FUNC_2 &pcfg_pull_up>,
  567. <1 24 RK_FUNC_2 &pcfg_pull_up>,
  568. <1 25 RK_FUNC_2 &pcfg_pull_up>;
  569. };
  570. };
  571. gmac {
  572. rgmii_pins: rgmii-pins {
  573. rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
  574. <3 24 RK_FUNC_1 &pcfg_pull_none>,
  575. <3 19 RK_FUNC_1 &pcfg_pull_none>,
  576. <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
  577. <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
  578. <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
  579. <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
  580. <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
  581. <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
  582. <3 15 RK_FUNC_1 &pcfg_pull_none>,
  583. <3 16 RK_FUNC_1 &pcfg_pull_none>,
  584. <3 17 RK_FUNC_1 &pcfg_pull_none>,
  585. <3 18 RK_FUNC_1 &pcfg_pull_none>,
  586. <3 25 RK_FUNC_1 &pcfg_pull_none>,
  587. <3 20 RK_FUNC_1 &pcfg_pull_none>;
  588. };
  589. rmii_pins: rmii-pins {
  590. rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
  591. <3 24 RK_FUNC_1 &pcfg_pull_none>,
  592. <3 19 RK_FUNC_1 &pcfg_pull_none>,
  593. <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
  594. <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
  595. <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
  596. <3 15 RK_FUNC_1 &pcfg_pull_none>,
  597. <3 16 RK_FUNC_1 &pcfg_pull_none>,
  598. <3 20 RK_FUNC_1 &pcfg_pull_none>,
  599. <3 21 RK_FUNC_1 &pcfg_pull_none>;
  600. };
  601. };
  602. i2c0 {
  603. i2c0_xfer: i2c0-xfer {
  604. rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
  605. <0 7 RK_FUNC_1 &pcfg_pull_none>;
  606. };
  607. };
  608. i2c1 {
  609. i2c1_xfer: i2c1-xfer {
  610. rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
  611. <2 22 RK_FUNC_1 &pcfg_pull_none>;
  612. };
  613. };
  614. i2c2 {
  615. i2c2_xfer: i2c2-xfer {
  616. rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
  617. <3 31 RK_FUNC_2 &pcfg_pull_none>;
  618. };
  619. };
  620. i2c3 {
  621. i2c3_xfer: i2c3-xfer {
  622. rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
  623. <1 17 RK_FUNC_1 &pcfg_pull_none>;
  624. };
  625. };
  626. i2c4 {
  627. i2c4_xfer: i2c4-xfer {
  628. rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
  629. <3 25 RK_FUNC_2 &pcfg_pull_none>;
  630. };
  631. };
  632. i2c5 {
  633. i2c5_xfer: i2c5-xfer {
  634. rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
  635. <3 27 RK_FUNC_2 &pcfg_pull_none>;
  636. };
  637. };
  638. sdio0 {
  639. sdio0_bus1: sdio0-bus1 {
  640. rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
  641. };
  642. sdio0_bus4: sdio0-bus4 {
  643. rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
  644. <2 29 RK_FUNC_1 &pcfg_pull_up>,
  645. <2 30 RK_FUNC_1 &pcfg_pull_up>,
  646. <2 31 RK_FUNC_1 &pcfg_pull_up>;
  647. };
  648. sdio0_cmd: sdio0-cmd {
  649. rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
  650. };
  651. sdio0_clk: sdio0-clk {
  652. rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
  653. };
  654. sdio0_cd: sdio0-cd {
  655. rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
  656. };
  657. sdio0_wp: sdio0-wp {
  658. rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
  659. };
  660. sdio0_pwr: sdio0-pwr {
  661. rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
  662. };
  663. sdio0_bkpwr: sdio0-bkpwr {
  664. rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
  665. };
  666. sdio0_int: sdio0-int {
  667. rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
  668. };
  669. };
  670. sdmmc {
  671. sdmmc_clk: sdmmc-clk {
  672. rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
  673. };
  674. sdmmc_cmd: sdmmc-cmd {
  675. rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
  676. };
  677. sdmmc_cd: sdmcc-cd {
  678. rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
  679. };
  680. sdmmc_bus1: sdmmc-bus1 {
  681. rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
  682. };
  683. sdmmc_bus4: sdmmc-bus4 {
  684. rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
  685. <2 6 RK_FUNC_1 &pcfg_pull_up>,
  686. <2 7 RK_FUNC_1 &pcfg_pull_up>,
  687. <2 8 RK_FUNC_1 &pcfg_pull_up>;
  688. };
  689. };
  690. spi0 {
  691. spi0_clk: spi0-clk {
  692. rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
  693. };
  694. spi0_cs0: spi0-cs0 {
  695. rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
  696. };
  697. spi0_cs1: spi0-cs1 {
  698. rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
  699. };
  700. spi0_tx: spi0-tx {
  701. rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
  702. };
  703. spi0_rx: spi0-rx {
  704. rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
  705. };
  706. };
  707. spi1 {
  708. spi1_clk: spi1-clk {
  709. rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
  710. };
  711. spi1_cs0: spi1-cs0 {
  712. rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
  713. };
  714. spi1_cs1: spi1-cs1 {
  715. rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
  716. };
  717. spi1_rx: spi1-rx {
  718. rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
  719. };
  720. spi1_tx: spi1-tx {
  721. rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
  722. };
  723. };
  724. spi2 {
  725. spi2_clk: spi2-clk {
  726. rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
  727. };
  728. spi2_cs0: spi2-cs0 {
  729. rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
  730. };
  731. spi2_rx: spi2-rx {
  732. rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
  733. };
  734. spi2_tx: spi2-tx {
  735. rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
  736. };
  737. };
  738. uart0 {
  739. uart0_xfer: uart0-xfer {
  740. rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
  741. <2 25 RK_FUNC_1 &pcfg_pull_none>;
  742. };
  743. uart0_cts: uart0-cts {
  744. rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
  745. };
  746. uart0_rts: uart0-rts {
  747. rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
  748. };
  749. };
  750. uart1 {
  751. uart1_xfer: uart1-xfer {
  752. rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
  753. <0 21 RK_FUNC_3 &pcfg_pull_none>;
  754. };
  755. uart1_cts: uart1-cts {
  756. rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
  757. };
  758. uart1_rts: uart1-rts {
  759. rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
  760. };
  761. };
  762. uart2 {
  763. uart2_xfer: uart2-xfer {
  764. rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
  765. <2 5 RK_FUNC_2 &pcfg_pull_none>;
  766. };
  767. /* no rts / cts for uart2 */
  768. };
  769. uart3 {
  770. uart3_xfer: uart3-xfer {
  771. rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
  772. <3 30 RK_FUNC_3 &pcfg_pull_none>;
  773. };
  774. uart3_cts: uart3-cts {
  775. rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
  776. };
  777. uart3_rts: uart3-rts {
  778. rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
  779. };
  780. };
  781. uart4 {
  782. uart4_xfer: uart4-xfer {
  783. rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
  784. <0 26 RK_FUNC_3 &pcfg_pull_none>;
  785. };
  786. uart4_cts: uart4-cts {
  787. rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
  788. };
  789. uart4_rts: uart4-rts {
  790. rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
  791. };
  792. };
  793. };
  794. };