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- /*
- * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
- #include <dt-bindings/clock/rk3368-cru.h>
- #include <dt-bindings/gpio/gpio.h>
- #include <dt-bindings/interrupt-controller/irq.h>
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/pinctrl/rockchip.h>
- / {
- compatible = "rockchip,rk3368";
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
- aliases {
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c4 = &i2c4;
- i2c5 = &i2c5;
- serial0 = &uart0;
- serial1 = &uart1;
- serial2 = &uart2;
- serial3 = &uart3;
- serial4 = &uart4;
- spi0 = &spi0;
- spi1 = &spi1;
- spi2 = &spi2;
- };
- cpus {
- #address-cells = <0x2>;
- #size-cells = <0x0>;
- cpu-map {
- cluster0 {
- core0 {
- cpu = <&cpu_b0>;
- };
- core1 {
- cpu = <&cpu_b1>;
- };
- core2 {
- cpu = <&cpu_b2>;
- };
- core3 {
- cpu = <&cpu_b3>;
- };
- };
- cluster1 {
- core0 {
- cpu = <&cpu_l0>;
- };
- core1 {
- cpu = <&cpu_l1>;
- };
- core2 {
- cpu = <&cpu_l2>;
- };
- core3 {
- cpu = <&cpu_l3>;
- };
- };
- };
- idle-states {
- entry-method = "psci";
- cpu_sleep: cpu-sleep-0 {
- compatible = "arm,idle-state";
- arm,psci-suspend-param = <0x1010000>;
- entry-latency-us = <0x3fffffff>;
- exit-latency-us = <0x40000000>;
- min-residency-us = <0xffffffff>;
- };
- };
- cpu_l0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
- reg = <0x0 0x0>;
- cpu-idle-states = <&cpu_sleep>;
- enable-method = "psci";
- };
- cpu_l1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
- reg = <0x0 0x1>;
- cpu-idle-states = <&cpu_sleep>;
- enable-method = "psci";
- };
- cpu_l2: cpu@2 {
- device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
- reg = <0x0 0x2>;
- cpu-idle-states = <&cpu_sleep>;
- enable-method = "psci";
- };
- cpu_l3: cpu@3 {
- device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
- reg = <0x0 0x3>;
- cpu-idle-states = <&cpu_sleep>;
- enable-method = "psci";
- };
- cpu_b0: cpu@100 {
- device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
- reg = <0x0 0x100>;
- cpu-idle-states = <&cpu_sleep>;
- enable-method = "psci";
- };
- cpu_b1: cpu@101 {
- device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
- reg = <0x0 0x101>;
- cpu-idle-states = <&cpu_sleep>;
- enable-method = "psci";
- };
- cpu_b2: cpu@102 {
- device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
- reg = <0x0 0x102>;
- cpu-idle-states = <&cpu_sleep>;
- enable-method = "psci";
- };
- cpu_b3: cpu@103 {
- device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
- reg = <0x0 0x103>;
- cpu-idle-states = <&cpu_sleep>;
- enable-method = "psci";
- };
- };
- arm-pmu {
- compatible = "arm,armv8-pmuv3";
- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
- <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
- <&cpu_b2>, <&cpu_b3>;
- };
- psci {
- compatible = "arm,psci-0.2";
- method = "smc";
- };
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13
- (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 14
- (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 11
- (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 10
- (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
- };
- xin24m: oscillator {
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- clock-output-names = "xin24m";
- #clock-cells = <0>;
- };
- sdmmc: dwmmc@ff0c0000 {
- compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
- reg = <0x0 0xff0c0000 0x0 0x4000>;
- clock-freq-min-max = <400000 150000000>;
- clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
- clock-names = "biu", "ciu";
- fifo-depth = <0x100>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
- sdio0: dwmmc@ff0d0000 {
- compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
- reg = <0x0 0xff0d0000 0x0 0x4000>;
- clock-freq-min-max = <400000 150000000>;
- clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
- <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
- fifo-depth = <0x100>;
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
- emmc: dwmmc@ff0f0000 {
- compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
- reg = <0x0 0xff0f0000 0x0 0x4000>;
- clock-freq-min-max = <400000 150000000>;
- clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
- clock-names = "biu", "ciu";
- fifo-depth = <0x100>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
- saradc: saradc@ff100000 {
- compatible = "rockchip,saradc";
- reg = <0x0 0xff100000 0x0 0x100>;
- interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
- #io-channel-cells = <1>;
- clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
- clock-names = "saradc", "apb_pclk";
- resets = <&cru SRST_SARADC>;
- reset-names = "saradc-apb";
- status = "disabled";
- };
- spi0: spi@ff110000 {
- compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
- reg = <0x0 0xff110000 0x0 0x1000>;
- clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
- clock-names = "spiclk", "apb_pclk";
- interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
- spi1: spi@ff120000 {
- compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
- reg = <0x0 0xff120000 0x0 0x1000>;
- clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
- clock-names = "spiclk", "apb_pclk";
- interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
- spi2: spi@ff130000 {
- compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
- reg = <0x0 0xff130000 0x0 0x1000>;
- clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
- clock-names = "spiclk", "apb_pclk";
- interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
- i2c1: i2c@ff140000 {
- compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
- reg = <0x0 0xff140000 0x0 0x1000>;
- interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "i2c";
- clocks = <&cru PCLK_I2C1>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_xfer>;
- status = "disabled";
- };
- i2c3: i2c@ff150000 {
- compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
- reg = <0x0 0xff150000 0x0 0x1000>;
- interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "i2c";
- clocks = <&cru PCLK_I2C3>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3_xfer>;
- status = "disabled";
- };
- i2c4: i2c@ff160000 {
- compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
- reg = <0x0 0xff160000 0x0 0x1000>;
- interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "i2c";
- clocks = <&cru PCLK_I2C4>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c4_xfer>;
- status = "disabled";
- };
- i2c5: i2c@ff170000 {
- compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
- reg = <0x0 0xff170000 0x0 0x1000>;
- interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "i2c";
- clocks = <&cru PCLK_I2C5>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c5_xfer>;
- status = "disabled";
- };
- uart0: serial@ff180000 {
- compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
- reg = <0x0 0xff180000 0x0 0x100>;
- clock-frequency = <24000000>;
- clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
- clock-names = "baudclk", "apb_pclk";
- interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
- uart1: serial@ff190000 {
- compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
- reg = <0x0 0xff190000 0x0 0x100>;
- clock-frequency = <24000000>;
- clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
- clock-names = "baudclk", "apb_pclk";
- interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
- uart3: serial@ff1b0000 {
- compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
- reg = <0x0 0xff1b0000 0x0 0x100>;
- clock-frequency = <24000000>;
- clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
- clock-names = "baudclk", "apb_pclk";
- interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
- uart4: serial@ff1c0000 {
- compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
- reg = <0x0 0xff1c0000 0x0 0x100>;
- clock-frequency = <24000000>;
- clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
- clock-names = "baudclk", "apb_pclk";
- interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
- gmac: ethernet@ff290000 {
- compatible = "rockchip,rk3368-gmac";
- reg = <0x0 0xff290000 0x0 0x10000>;
- interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
- rockchip,grf = <&grf>;
- clocks = <&cru SCLK_MAC>,
- <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
- <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
- <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
- clock-names = "stmmaceth",
- "mac_clk_rx", "mac_clk_tx",
- "clk_mac_ref", "clk_mac_refout",
- "aclk_mac", "pclk_mac";
- status = "disabled";
- };
- usb_host0_ehci: usb@ff500000 {
- compatible = "generic-ehci";
- reg = <0x0 0xff500000 0x0 0x100>;
- interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_HOST0>;
- clock-names = "usbhost";
- status = "disabled";
- };
- usb_otg: usb@ff580000 {
- compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
- "snps,dwc2";
- reg = <0x0 0xff580000 0x0 0x40000>;
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru HCLK_OTG0>;
- clock-names = "otg";
- dr_mode = "otg";
- g-np-tx-fifo-size = <16>;
- g-rx-fifo-size = <275>;
- g-tx-fifo-size = <256 128 128 64 64 32>;
- g-use-dma;
- status = "disabled";
- };
- i2c0: i2c@ff650000 {
- compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
- reg = <0x0 0xff650000 0x0 0x1000>;
- clocks = <&cru PCLK_I2C0>;
- clock-names = "i2c";
- interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_xfer>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
- i2c2: i2c@ff660000 {
- compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
- reg = <0x0 0xff660000 0x0 0x1000>;
- interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "i2c";
- clocks = <&cru PCLK_I2C2>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_xfer>;
- status = "disabled";
- };
- uart2: serial@ff690000 {
- compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
- reg = <0x0 0xff690000 0x0 0x100>;
- clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
- clock-names = "baudclk", "apb_pclk";
- interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_xfer>;
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
- };
- pmugrf: syscon@ff738000 {
- compatible = "rockchip,rk3368-pmugrf", "syscon";
- reg = <0x0 0xff738000 0x0 0x1000>;
- };
- cru: clock-controller@ff760000 {
- compatible = "rockchip,rk3368-cru";
- reg = <0x0 0xff760000 0x0 0x1000>;
- rockchip,grf = <&grf>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
- grf: syscon@ff770000 {
- compatible = "rockchip,rk3368-grf", "syscon";
- reg = <0x0 0xff770000 0x0 0x1000>;
- };
- wdt: watchdog@ff800000 {
- compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
- reg = <0x0 0xff800000 0x0 0x100>;
- clocks = <&cru PCLK_WDT>;
- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
- gic: interrupt-controller@ffb71000 {
- compatible = "arm,gic-400";
- interrupt-controller;
- #interrupt-cells = <3>;
- #address-cells = <0>;
- reg = <0x0 0xffb71000 0x0 0x1000>,
- <0x0 0xffb72000 0x0 0x2000>,
- <0x0 0xffb74000 0x0 0x2000>,
- <0x0 0xffb76000 0x0 0x2000>;
- interrupts = <GIC_PPI 9
- (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
- };
- pinctrl: pinctrl {
- compatible = "rockchip,rk3368-pinctrl";
- rockchip,grf = <&grf>;
- rockchip,pmu = <&pmugrf>;
- #address-cells = <0x2>;
- #size-cells = <0x2>;
- ranges;
- gpio0: gpio0@ff750000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xff750000 0x0 0x100>;
- clocks = <&cru PCLK_GPIO0>;
- interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <0x2>;
- interrupt-controller;
- #interrupt-cells = <0x2>;
- };
- gpio1: gpio1@ff780000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xff780000 0x0 0x100>;
- clocks = <&cru PCLK_GPIO1>;
- interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <0x2>;
- interrupt-controller;
- #interrupt-cells = <0x2>;
- };
- gpio2: gpio2@ff790000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xff790000 0x0 0x100>;
- clocks = <&cru PCLK_GPIO2>;
- interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <0x2>;
- interrupt-controller;
- #interrupt-cells = <0x2>;
- };
- gpio3: gpio3@ff7a0000 {
- compatible = "rockchip,gpio-bank";
- reg = <0x0 0xff7a0000 0x0 0x100>;
- clocks = <&cru PCLK_GPIO3>;
- interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <0x2>;
- interrupt-controller;
- #interrupt-cells = <0x2>;
- };
- pcfg_pull_up: pcfg-pull-up {
- bias-pull-up;
- };
- pcfg_pull_down: pcfg-pull-down {
- bias-pull-down;
- };
- pcfg_pull_none: pcfg-pull-none {
- bias-disable;
- };
- pcfg_pull_none_12ma: pcfg-pull-none-12ma {
- bias-disable;
- drive-strength = <12>;
- };
- emmc {
- emmc_clk: emmc-clk {
- rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
- };
- emmc_cmd: emmc-cmd {
- rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
- };
- emmc_pwr: emmc-pwr {
- rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
- };
- emmc_bus1: emmc-bus1 {
- rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
- };
- emmc_bus4: emmc-bus4 {
- rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
- <1 19 RK_FUNC_2 &pcfg_pull_up>,
- <1 20 RK_FUNC_2 &pcfg_pull_up>,
- <1 21 RK_FUNC_2 &pcfg_pull_up>;
- };
- emmc_bus8: emmc-bus8 {
- rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
- <1 19 RK_FUNC_2 &pcfg_pull_up>,
- <1 20 RK_FUNC_2 &pcfg_pull_up>,
- <1 21 RK_FUNC_2 &pcfg_pull_up>,
- <1 22 RK_FUNC_2 &pcfg_pull_up>,
- <1 23 RK_FUNC_2 &pcfg_pull_up>,
- <1 24 RK_FUNC_2 &pcfg_pull_up>,
- <1 25 RK_FUNC_2 &pcfg_pull_up>;
- };
- };
- gmac {
- rgmii_pins: rgmii-pins {
- rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
- <3 24 RK_FUNC_1 &pcfg_pull_none>,
- <3 19 RK_FUNC_1 &pcfg_pull_none>,
- <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
- <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
- <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
- <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
- <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
- <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
- <3 15 RK_FUNC_1 &pcfg_pull_none>,
- <3 16 RK_FUNC_1 &pcfg_pull_none>,
- <3 17 RK_FUNC_1 &pcfg_pull_none>,
- <3 18 RK_FUNC_1 &pcfg_pull_none>,
- <3 25 RK_FUNC_1 &pcfg_pull_none>,
- <3 20 RK_FUNC_1 &pcfg_pull_none>;
- };
- rmii_pins: rmii-pins {
- rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
- <3 24 RK_FUNC_1 &pcfg_pull_none>,
- <3 19 RK_FUNC_1 &pcfg_pull_none>,
- <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
- <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
- <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
- <3 15 RK_FUNC_1 &pcfg_pull_none>,
- <3 16 RK_FUNC_1 &pcfg_pull_none>,
- <3 20 RK_FUNC_1 &pcfg_pull_none>,
- <3 21 RK_FUNC_1 &pcfg_pull_none>;
- };
- };
- i2c0 {
- i2c0_xfer: i2c0-xfer {
- rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
- <0 7 RK_FUNC_1 &pcfg_pull_none>;
- };
- };
- i2c1 {
- i2c1_xfer: i2c1-xfer {
- rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
- <2 22 RK_FUNC_1 &pcfg_pull_none>;
- };
- };
- i2c2 {
- i2c2_xfer: i2c2-xfer {
- rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
- <3 31 RK_FUNC_2 &pcfg_pull_none>;
- };
- };
- i2c3 {
- i2c3_xfer: i2c3-xfer {
- rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
- <1 17 RK_FUNC_1 &pcfg_pull_none>;
- };
- };
- i2c4 {
- i2c4_xfer: i2c4-xfer {
- rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
- <3 25 RK_FUNC_2 &pcfg_pull_none>;
- };
- };
- i2c5 {
- i2c5_xfer: i2c5-xfer {
- rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
- <3 27 RK_FUNC_2 &pcfg_pull_none>;
- };
- };
- sdio0 {
- sdio0_bus1: sdio0-bus1 {
- rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
- };
- sdio0_bus4: sdio0-bus4 {
- rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
- <2 29 RK_FUNC_1 &pcfg_pull_up>,
- <2 30 RK_FUNC_1 &pcfg_pull_up>,
- <2 31 RK_FUNC_1 &pcfg_pull_up>;
- };
- sdio0_cmd: sdio0-cmd {
- rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
- };
- sdio0_clk: sdio0-clk {
- rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
- };
- sdio0_cd: sdio0-cd {
- rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
- };
- sdio0_wp: sdio0-wp {
- rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
- };
- sdio0_pwr: sdio0-pwr {
- rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
- };
- sdio0_bkpwr: sdio0-bkpwr {
- rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
- };
- sdio0_int: sdio0-int {
- rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
- };
- };
- sdmmc {
- sdmmc_clk: sdmmc-clk {
- rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
- };
- sdmmc_cmd: sdmmc-cmd {
- rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
- };
- sdmmc_cd: sdmcc-cd {
- rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
- };
- sdmmc_bus1: sdmmc-bus1 {
- rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
- };
- sdmmc_bus4: sdmmc-bus4 {
- rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
- <2 6 RK_FUNC_1 &pcfg_pull_up>,
- <2 7 RK_FUNC_1 &pcfg_pull_up>,
- <2 8 RK_FUNC_1 &pcfg_pull_up>;
- };
- };
- spi0 {
- spi0_clk: spi0-clk {
- rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
- };
- spi0_cs0: spi0-cs0 {
- rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
- };
- spi0_cs1: spi0-cs1 {
- rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
- };
- spi0_tx: spi0-tx {
- rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
- };
- spi0_rx: spi0-rx {
- rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
- };
- };
- spi1 {
- spi1_clk: spi1-clk {
- rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
- };
- spi1_cs0: spi1-cs0 {
- rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
- };
- spi1_cs1: spi1-cs1 {
- rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
- };
- spi1_rx: spi1-rx {
- rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
- };
- spi1_tx: spi1-tx {
- rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
- };
- };
- spi2 {
- spi2_clk: spi2-clk {
- rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
- };
- spi2_cs0: spi2-cs0 {
- rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
- };
- spi2_rx: spi2-rx {
- rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
- };
- spi2_tx: spi2-tx {
- rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
- };
- };
- uart0 {
- uart0_xfer: uart0-xfer {
- rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
- <2 25 RK_FUNC_1 &pcfg_pull_none>;
- };
- uart0_cts: uart0-cts {
- rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
- };
- uart0_rts: uart0-rts {
- rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
- };
- };
- uart1 {
- uart1_xfer: uart1-xfer {
- rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
- <0 21 RK_FUNC_3 &pcfg_pull_none>;
- };
- uart1_cts: uart1-cts {
- rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
- };
- uart1_rts: uart1-rts {
- rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
- };
- };
- uart2 {
- uart2_xfer: uart2-xfer {
- rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
- <2 5 RK_FUNC_2 &pcfg_pull_none>;
- };
- /* no rts / cts for uart2 */
- };
- uart3 {
- uart3_xfer: uart3-xfer {
- rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
- <3 30 RK_FUNC_3 &pcfg_pull_none>;
- };
- uart3_cts: uart3-cts {
- rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
- };
- uart3_rts: uart3-rts {
- rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
- };
- };
- uart4 {
- uart4_xfer: uart4-xfer {
- rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
- <0 26 RK_FUNC_3 &pcfg_pull_none>;
- };
- uart4_cts: uart4-cts {
- rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
- };
- uart4_rts: uart4-rts {
- rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
- };
- };
- };
- };
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